369 	u32 src_clk_period, dst_clk_period; /* in picoseconds */  in tegra210_emc_r21021_set_clock()  local
403 	src_clk_period = 1000000000 / last->rate;  in tegra210_emc_r21021_set_clock()
436 		src_clk_period, dst_clk_period);  in tegra210_emc_r21021_set_clock()
606 	if (src_clk_period > 50000 && dram_type == DRAM_TYPE_LPDDR4)  in tegra210_emc_r21021_set_clock()
645 		if (src_clk_period >= 1000000 / 1866) /* 535.91 ps */  in tegra210_emc_r21021_set_clock()
648 		if (src_clk_period >= 1000000 / 1600) /* 625.00 ps */  in tegra210_emc_r21021_set_clock()
651 		if (src_clk_period >= 1000000 / 1333) /* 750.19 ps */  in tegra210_emc_r21021_set_clock()
654 		if (src_clk_period >= 1000000 / 1066) /* 938.09 ps */  in tegra210_emc_r21021_set_clock()
657 		deltaTWATM = max_t(u32, div_o3(7500, src_clk_period), 8);  in tegra210_emc_r21021_set_clock()
668 		tRTM = fake->dram_timings[RL] + div_o3(3600, src_clk_period) +  in tegra210_emc_r21021_set_clock()
669 			max_t(u32, div_o3(7500, src_clk_period), 8) + tRPST +  in tegra210_emc_r21021_set_clock()
1056 		value = (1000 * fake->dram_timings[T_RP]) / src_clk_period;  in tegra210_emc_r21021_set_clock()
1058 		ccfifo_writel(emc, 0, 0, tFC_lpddr4 / src_clk_period);  in tegra210_emc_r21021_set_clock()
1066 					src_clk_period;  in tegra210_emc_r21021_set_clock()
1089 		delay = ((1000 * fake->dram_timings[T_RP] / src_clk_period) +  in tegra210_emc_r21021_set_clock()
1090 			 (1000 * fake->dram_timings[T_RFC] / src_clk_period));  in tegra210_emc_r21021_set_clock()
1107 	ramp_down_wait = tegra210_emc_dvfs_power_ramp_down(emc, src_clk_period,  in tegra210_emc_r21021_set_clock()