369 	u32 src_clk_period, dst_clk_period; /* in picoseconds */  in tegra210_emc_r21021_set_clock()  local
404 	dst_clk_period = 1000000000 / next->rate;  in tegra210_emc_r21021_set_clock()
406 	if (dst_clk_period <= zqcal_before_cc_cutoff)  in tegra210_emc_r21021_set_clock()
411 	tZQCAL_lpddr4_fc_adj /= dst_clk_period;  in tegra210_emc_r21021_set_clock()
436 		src_clk_period, dst_clk_period);  in tegra210_emc_r21021_set_clock()
618 		zq_wait_long = max((u32)1, div_o3(1000000, dst_clk_period));  in tegra210_emc_r21021_set_clock()
621 				   div_o3(360000, dst_clk_period)) + 4;  in tegra210_emc_r21021_set_clock()
624 				   div_o3(320000, dst_clk_period) + 2);  in tegra210_emc_r21021_set_clock()
1012 		    dst_clk_period <= zqcal_before_cc_cutoff) {  in tegra210_emc_r21021_set_clock()
1126 	ramp_up_wait = tegra210_emc_dvfs_power_ramp_up(emc, dst_clk_period, 0);  in tegra210_emc_r21021_set_clock()
1152 	if (dst_clk_period <= zqcal_before_cc_cutoff) {  in tegra210_emc_r21021_set_clock()
1154 			(s32)dst_clk_period;  in tegra210_emc_r21021_set_clock()
1159 			       dst_clk_period);  in tegra210_emc_r21021_set_clock()
1164 		dst_clk_period);  in tegra210_emc_r21021_set_clock()
1172 			       dst_clk_period);  in tegra210_emc_r21021_set_clock()
1175 			if (dst_clk_period > zqcal_before_cc_cutoff)  in tegra210_emc_r21021_set_clock()
1190 			if (dst_clk_period > zqcal_before_cc_cutoff)  in tegra210_emc_r21021_set_clock()
1211 				      tZQCAL_lpddr4 / dst_clk_period);  in tegra210_emc_r21021_set_clock()
1213 			if (dst_clk_period > zqcal_before_cc_cutoff)  in tegra210_emc_r21021_set_clock()
1274 			value = div_o3(value, dst_clk_period);  in tegra210_emc_r21021_set_clock()
1315 			delay = (1250000 - ramp_up_wait) / dst_clk_period;  in tegra210_emc_r21021_set_clock()