20 #define INFO            (1 << 0)  macro
376 	emc_dbg(emc, INFO, "Running clock change.\n");  in tegra210_emc_r21021_set_clock()
427 	emc_dbg(emc, INFO, "Clock change version: %d\n",  in tegra210_emc_r21021_set_clock()
429 	emc_dbg(emc, INFO, "DRAM type = %d\n", dram_type);  in tegra210_emc_r21021_set_clock()
430 	emc_dbg(emc, INFO, "DRAM dev #: %u\n", emc->num_devices);  in tegra210_emc_r21021_set_clock()
431 	emc_dbg(emc, INFO, "Next EMC clksrc: 0x%08x\n", clksrc);  in tegra210_emc_r21021_set_clock()
432 	emc_dbg(emc, INFO, "DLL clksrc:      0x%08x\n", next->dll_clk_src);  in tegra210_emc_r21021_set_clock()
433 	emc_dbg(emc, INFO, "last rate: %u, next rate %u\n", last->rate,  in tegra210_emc_r21021_set_clock()
435 	emc_dbg(emc, INFO, "last period: %u, next period: %u\n",  in tegra210_emc_r21021_set_clock()
437 	emc_dbg(emc, INFO, "  shared_zq_resistor: %d\n", !!shared_zq_resistor);  in tegra210_emc_r21021_set_clock()
438 	emc_dbg(emc, INFO, "  num_channels: %u\n", emc->num_channels);  in tegra210_emc_r21021_set_clock()
439 	emc_dbg(emc, INFO, "  opt_dll_mode: %d\n", opt_dll_mode);  in tegra210_emc_r21021_set_clock()
572 		emc_dbg(emc, INFO, "Prelock enabled for target frequency.\n");  in tegra210_emc_r21021_set_clock()
574 		emc_dbg(emc, INFO, "DLL out: 0x%03x\n", value);  in tegra210_emc_r21021_set_clock()
576 		emc_dbg(emc, INFO, "Disabling DLL for target frequency.\n");  in tegra210_emc_r21021_set_clock()
672 		emc_dbg(emc, INFO, "tRTM = %u, EMC_RP = %u\n", tRTM,  in tegra210_emc_r21021_set_clock()
723 			emc_dbg(emc, INFO, "Skipped WAR\n");  in tegra210_emc_r21021_set_clock()
1162 	emc_dbg(emc, INFO, "tZQCAL_lpddr4_fc_adj = %u\n", tZQCAL_lpddr4_fc_adj);  in tegra210_emc_r21021_set_clock()
1163 	emc_dbg(emc, INFO, "dst_clk_period = %u\n",  in tegra210_emc_r21021_set_clock()
1165 	emc_dbg(emc, INFO, "next->dram_timings[T_PDEX] = %u\n",  in tegra210_emc_r21021_set_clock()
1167 	emc_dbg(emc, INFO, "zq_latch_dvfs_wait_time = %d\n",  in tegra210_emc_r21021_set_clock()