Lines Matching full:next
78 ({ next->ptfv_list[(dev)] = \
79 next->ptfv_list[(dev)] / \
80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
86 ({ next->ptfv_list[(dev)] += \
102 next->ptfv_list[dqs] = \
104 (next->ptfv_list[dqs] * \
105 next->ptfv_list[w])) / \
106 (next->ptfv_list[w] + 1); \
109 __stringify(dev), nval, next->ptfv_list[dqs]); \
184 struct tegra210_emc_timing *next) in periodic_compensation_handler() argument
190 u32 i, samples = next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; in periodic_compensation_handler()
194 if (!next->periodic_training) in periodic_compensation_handler()
199 (next->ptfv_list[PTFV_CONFIG_CTRL_INDEX] & in periodic_compensation_handler()
207 __COPY_EMA(next, last, idx); in periodic_compensation_handler()
211 __MOVAVG(next, idx) = 0; in periodic_compensation_handler()
214 /* Generate next sample of data. */ in periodic_compensation_handler()
225 over |= tegra210_emc_compare_update_delay(next, in periodic_compensation_handler()
226 __MOVAVG_AC(next, idx), idx); in periodic_compensation_handler()
235 over |= tegra210_emc_compare_update_delay(next, in periodic_compensation_handler()
236 __MOVAVG_AC(next, idx), idx); in periodic_compensation_handler()
359 struct tegra210_emc_timing *fake, *last = emc->last, *next = emc->next; in tegra210_emc_r21021_set_clock() local
364 u32 tFC_lpddr4 = 1000 * next->dram_timings[T_FC_LPDDR4]; in tegra210_emc_r21021_set_clock()
388 if ((next->burst_regs[EMC_ZCAL_INTERVAL_INDEX] != 0 && in tegra210_emc_r21021_set_clock()
394 opt_dll_mode = tegra210_emc_get_dll_state(next); in tegra210_emc_r21021_set_clock()
396 if ((next->burst_regs[EMC_FBIO_CFG5_INDEX] & BIT(25)) && in tegra210_emc_r21021_set_clock()
404 dst_clk_period = 1000000000 / next->rate; in tegra210_emc_r21021_set_clock()
417 emc_cfg = next->burst_regs[EMC_CFG_INDEX]; in tegra210_emc_r21021_set_clock()
420 emc_sel_dpd_ctrl = next->emc_sel_dpd_ctrl; in tegra210_emc_r21021_set_clock()
431 emc_dbg(emc, INFO, "Next EMC clksrc: 0x%08x\n", clksrc); in tegra210_emc_r21021_set_clock()
432 emc_dbg(emc, INFO, "DLL clksrc: 0x%08x\n", next->dll_clk_src); in tegra210_emc_r21021_set_clock()
433 emc_dbg(emc, INFO, "last rate: %u, next rate %u\n", last->rate, in tegra210_emc_r21021_set_clock()
434 next->rate); in tegra210_emc_r21021_set_clock()
435 emc_dbg(emc, INFO, "last period: %u, next period: %u\n", in tegra210_emc_r21021_set_clock()
460 emc_auto_cal_config = next->emc_auto_cal_config; in tegra210_emc_r21021_set_clock()
476 if (next->periodic_training) { in tegra210_emc_r21021_set_clock()
477 tegra210_emc_reset_dram_clktree_values(next); in tegra210_emc_r21021_set_clock()
489 if (periodic_compensation_handler(emc, DVFS_SEQUENCE, fake, next)) in tegra210_emc_r21021_set_clock()
499 emc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp & in tegra210_emc_r21021_set_clock()
504 ((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
508 ((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
513 (next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
516 (next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
536 ((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
540 ((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
543 next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX]; in tegra210_emc_r21021_set_clock()
570 if (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] & in tegra210_emc_r21021_set_clock()
587 emc_writel(emc, next->emc_auto_cal_config2, EMC_AUTO_CAL_CONFIG2); in tegra210_emc_r21021_set_clock()
588 emc_writel(emc, next->emc_auto_cal_config3, EMC_AUTO_CAL_CONFIG3); in tegra210_emc_r21021_set_clock()
589 emc_writel(emc, next->emc_auto_cal_config4, EMC_AUTO_CAL_CONFIG4); in tegra210_emc_r21021_set_clock()
590 emc_writel(emc, next->emc_auto_cal_config5, EMC_AUTO_CAL_CONFIG5); in tegra210_emc_r21021_set_clock()
591 emc_writel(emc, next->emc_auto_cal_config6, EMC_AUTO_CAL_CONFIG6); in tegra210_emc_r21021_set_clock()
592 emc_writel(emc, next->emc_auto_cal_config7, EMC_AUTO_CAL_CONFIG7); in tegra210_emc_r21021_set_clock()
593 emc_writel(emc, next->emc_auto_cal_config8, EMC_AUTO_CAL_CONFIG8); in tegra210_emc_r21021_set_clock()
609 emc_writel(emc, next->emc_cfg_2, EMC_CFG_2); in tegra210_emc_r21021_set_clock()
620 zq_wait_long = max(next->min_mrs_wait, in tegra210_emc_r21021_set_clock()
673 next->burst_regs[EMC_RP_INDEX]); in tegra210_emc_r21021_set_clock()
728 mr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x80; in tegra210_emc_r21021_set_clock()
729 mr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0x00; in tegra210_emc_r21021_set_clock()
731 mr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x40; in tegra210_emc_r21021_set_clock()
732 mr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0xc0; in tegra210_emc_r21021_set_clock()
737 emc_writel(emc, next->emc_mrw, EMC_MRW); in tegra210_emc_r21021_set_clock()
738 emc_writel(emc, next->emc_mrw2, EMC_MRW2); in tegra210_emc_r21021_set_clock()
748 for (i = 0; i < next->num_burst; i++) { in tegra210_emc_r21021_set_clock()
755 value = next->burst_regs[i]; in tegra210_emc_r21021_set_clock()
816 tegra210_emc_adjust_timing(emc, next); in tegra210_emc_r21021_set_clock()
820 (next->run_clocks & EMC_MRW_MRW_OP_MASK); in tegra210_emc_r21021_set_clock()
827 for (i = 0; i < next->num_burst_per_ch; i++) { in tegra210_emc_r21021_set_clock()
852 next->burst_reg_per_ch[i], burst[i].offset); in tegra210_emc_r21021_set_clock()
854 next->burst_reg_per_ch[i], in tegra210_emc_r21021_set_clock()
861 for (i = 0; i < next->vref_num; i++) { in tegra210_emc_r21021_set_clock()
872 next->vref_perch_regs[i], vref[i].offset); in tegra210_emc_r21021_set_clock()
873 emc_channel_writel(emc, vref[i].bank, next->vref_perch_regs[i], in tegra210_emc_r21021_set_clock()
880 for (i = 0; i < next->num_trim; i++) { in tegra210_emc_r21021_set_clock()
897 value = tegra210_emc_compensate(next, offsets[i]); in tegra210_emc_r21021_set_clock()
905 next->trim_regs[i], offsets[i]); in tegra210_emc_r21021_set_clock()
906 emc_writel(emc, next->trim_regs[i], offsets[i]); in tegra210_emc_r21021_set_clock()
913 for (i = 0; i < next->num_trim_per_ch; i++) { in tegra210_emc_r21021_set_clock()
937 value = tegra210_emc_compensate(next, offset); in tegra210_emc_r21021_set_clock()
945 next->trim_perch_regs[i], offset); in tegra210_emc_r21021_set_clock()
947 next->trim_perch_regs[i], offset); in tegra210_emc_r21021_set_clock()
953 for (i = 0; i < next->num_mc_regs; i++) { in tegra210_emc_r21021_set_clock()
955 u32 *values = next->burst_mc_regs; in tegra210_emc_r21021_set_clock()
963 if (next->rate < last->rate) { in tegra210_emc_r21021_set_clock()
968 for (i = 0; i < next->num_up_down; i++) { in tegra210_emc_r21021_set_clock()
970 next->la_scale_regs[i], la[i]); in tegra210_emc_r21021_set_clock()
971 mc_writel(emc->mc, next->la_scale_regs[i], la[i]); in tegra210_emc_r21021_set_clock()
984 value = next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX]; in tegra210_emc_r21021_set_clock()
1014 ccfifo_writel(emc, (next->burst_regs[EMC_MRW6_INDEX] & in tegra210_emc_r21021_set_clock()
1018 ccfifo_writel(emc, (next->burst_regs[EMC_MRW14_INDEX] & in tegra210_emc_r21021_set_clock()
1025 (next->burst_regs[EMC_MRW7_INDEX] & in tegra210_emc_r21021_set_clock()
1030 (next->burst_regs[EMC_MRW15_INDEX] & in tegra210_emc_r21021_set_clock()
1158 div_o3(1000 * next->dram_timings[T_PDEX], in tegra210_emc_r21021_set_clock()
1165 emc_dbg(emc, INFO, "next->dram_timings[T_PDEX] = %u\n", in tegra210_emc_r21021_set_clock()
1166 next->dram_timings[T_PDEX]); in tegra210_emc_r21021_set_clock()
1171 delay = div_o3(1000 * next->dram_timings[T_PDEX], in tegra210_emc_r21021_set_clock()
1251 ccfifo_writel(emc, next->emc_mrw2, EMC_MRW2, 0); in tegra210_emc_r21021_set_clock()
1252 ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1254 ccfifo_writel(emc, next->emc_mrw4, EMC_MRW4, 0); in tegra210_emc_r21021_set_clock()
1257 ccfifo_writel(emc, next->emc_emrs & in tegra210_emc_r21021_set_clock()
1259 ccfifo_writel(emc, next->emc_emrs2 & in tegra210_emc_r21021_set_clock()
1261 ccfifo_writel(emc, next->emc_mrs | in tegra210_emc_r21021_set_clock()
1320 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX], in tegra210_emc_r21021_set_clock()
1349 ccfifo_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX], in tegra210_emc_r21021_set_clock()
1353 ccfifo_writel(emc, next->burst_regs[EMC_CFG_INDEX] & in tegra210_emc_r21021_set_clock()
1370 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
1375 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
1407 if (next->rate > last->rate) { in tegra210_emc_r21021_set_clock()
1408 for (i = 0; i < next->num_up_down; i++) in tegra210_emc_r21021_set_clock()
1409 mc_writel(emc->mc, next->la_scale_regs[i], in tegra210_emc_r21021_set_clock()
1423 emc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX], in tegra210_emc_r21021_set_clock()
1425 emc_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX], in tegra210_emc_r21021_set_clock()
1436 emc_writel(emc, next->burst_regs[EMC_MRS_WAIT_CNT_INDEX], in tegra210_emc_r21021_set_clock()
1439 emc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX], in tegra210_emc_r21021_set_clock()
1451 emc_writel(emc, next->burst_regs[EMC_CFG_INDEX], EMC_CFG); in tegra210_emc_r21021_set_clock()
1453 emc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp, in tegra210_emc_r21021_set_clock()
1455 emc_writel(emc, next->emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL); in tegra210_emc_r21021_set_clock()
1465 next->burst_regs[EMC_PMACRO_AUTOCAL_CFG_COMMON_INDEX], in tegra210_emc_r21021_set_clock()
1496 if (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] & EMC_CFG_DIG_DLL_CFG_DLL_EN) { in tegra210_emc_r21021_set_clock()
1508 emc_writel(emc, next->emc_auto_cal_config, EMC_AUTO_CAL_CONFIG); in tegra210_emc_r21021_set_clock()