Lines Matching +full:emc +full:- +full:timings +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/interconnect-provider.h>
36 #define EMC_INTSTATUS 0x000
37 #define EMC_INTMASK 0x004
38 #define EMC_DBG 0x008
39 #define EMC_ADR_CFG_0 0x010
40 #define EMC_TIMING_CONTROL 0x028
41 #define EMC_RC 0x02c
42 #define EMC_RFC 0x030
43 #define EMC_RAS 0x034
44 #define EMC_RP 0x038
45 #define EMC_R2W 0x03c
46 #define EMC_W2R 0x040
47 #define EMC_R2P 0x044
48 #define EMC_W2P 0x048
49 #define EMC_RD_RCD 0x04c
50 #define EMC_WR_RCD 0x050
51 #define EMC_RRD 0x054
52 #define EMC_REXT 0x058
53 #define EMC_WDV 0x05c
54 #define EMC_QUSE 0x060
55 #define EMC_QRST 0x064
56 #define EMC_QSAFE 0x068
57 #define EMC_RDV 0x06c
58 #define EMC_REFRESH 0x070
59 #define EMC_BURST_REFRESH_NUM 0x074
60 #define EMC_PDEX2WR 0x078
61 #define EMC_PDEX2RD 0x07c
62 #define EMC_PCHG2PDEN 0x080
63 #define EMC_ACT2PDEN 0x084
64 #define EMC_AR2PDEN 0x088
65 #define EMC_RW2PDEN 0x08c
66 #define EMC_TXSR 0x090
67 #define EMC_TCKE 0x094
68 #define EMC_TFAW 0x098
69 #define EMC_TRPAB 0x09c
70 #define EMC_TCLKSTABLE 0x0a0
71 #define EMC_TCLKSTOP 0x0a4
72 #define EMC_TREFBW 0x0a8
73 #define EMC_QUSE_EXTRA 0x0ac
74 #define EMC_ODT_WRITE 0x0b0
75 #define EMC_ODT_READ 0x0b4
76 #define EMC_MRR 0x0ec
77 #define EMC_FBIO_CFG5 0x104
78 #define EMC_FBIO_CFG6 0x114
79 #define EMC_STAT_CONTROL 0x160
80 #define EMC_STAT_LLMC_CONTROL 0x178
81 #define EMC_STAT_PWR_CLOCK_LIMIT 0x198
82 #define EMC_STAT_PWR_CLOCKS 0x19c
83 #define EMC_STAT_PWR_COUNT 0x1a0
84 #define EMC_AUTO_CAL_INTERVAL 0x2a8
85 #define EMC_CFG_2 0x2b8
86 #define EMC_CFG_DIG_DLL 0x2bc
87 #define EMC_DLL_XFORM_DQS 0x2c0
88 #define EMC_DLL_XFORM_QUSE 0x2c4
89 #define EMC_ZCAL_REF_CNT 0x2e0
90 #define EMC_ZCAL_WAIT_CNT 0x2e4
91 #define EMC_CFG_CLKTRIM_0 0x2d0
92 #define EMC_CFG_CLKTRIM_1 0x2d4
93 #define EMC_CFG_CLKTRIM_2 0x2d8
95 #define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
99 #define EMC_TIMING_UPDATE BIT(0)
105 #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
112 #define EMC_FBIO_CFG5_DRAM_TYPE GENMASK(1, 0)
116 #define EMC_MRR_MRR_DATA GENMASK(15, 0)
206 struct emc_timing *timings;
216 * There are multiple sources in the EMC driver which could request
221 /* protect shared rate-change code path */
237 struct tegra_emc *emc = data;
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
247 dev_err_ratelimited(emc->dev,
251 writel_relaxed(status, emc->regs + EMC_INTSTATUS);
256 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
262 for (i = 0; i < emc->num_timings; i++) {
263 if (emc->timings[i].rate >= rate) {
264 timing = &emc->timings[i];
270 dev_err(emc->dev, "no timing for rate %lu\n", rate);
277 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
279 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
283 return -EINVAL;
285 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
286 __func__, timing->rate, rate);
289 for (i = 0; i < ARRAY_SIZE(timing->data); i++)
290 writel_relaxed(timing->data[i],
291 emc->regs + emc_timing_registers[i]);
294 readl_relaxed(emc->regs + emc_timing_registers[i - 1]);
296 return 0;
299 static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
304 dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
309 emc->regs + EMC_TIMING_CONTROL);
310 return 0;
313 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
317 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
321 return 0;
327 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
333 err = emc_prepare_timing_change(emc, cnd->new_rate);
337 err = emc_prepare_timing_change(emc, cnd->old_rate);
341 err = emc_complete_timing_change(emc, true);
345 err = emc_complete_timing_change(emc, false);
355 static int load_one_timing_from_dt(struct tegra_emc *emc,
362 if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
363 dev_err(emc->dev, "incompatible DT node: %pOF\n", node);
364 return -EINVAL;
367 err = of_property_read_u32(node, "clock-frequency", &rate);
369 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
374 err = of_property_read_u32_array(node, "nvidia,emc-registers",
375 timing->data,
378 dev_err(emc->dev,
379 "timing %pOF: failed to read emc timing data: %d\n",
385 * The EMC clock rate is twice the bus rate, and the bus rate is
388 timing->rate = rate * 2 * 1000;
390 dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",
391 __func__, node, timing->rate);
393 return 0;
401 if (a->rate < b->rate)
402 return -1;
404 if (a->rate > b->rate)
407 return 0;
410 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
419 dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node);
420 return -EINVAL;
423 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
425 if (!emc->timings)
426 return -ENOMEM;
428 timing = emc->timings;
434 err = load_one_timing_from_dt(emc, timing++, child);
438 emc->num_timings++;
441 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
444 dev_info_once(emc->dev,
445 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
446 emc->num_timings,
448 emc->timings[0].rate / 1000000,
449 emc->timings[emc->num_timings - 1].rate / 1000000);
451 return 0;
455 tegra_emc_find_node_by_ram_code(struct tegra_emc *emc)
457 struct device *dev = emc->dev;
462 if (emc->mrr_error) {
463 dev_warn(dev, "memory timings skipped due to MRR error\n");
467 if (of_get_child_count(dev->of_node) == 0) {
468 dev_info_once(dev, "device-tree doesn't have memory timings\n");
472 if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code"))
473 return of_node_get(dev->of_node);
477 for_each_child_of_node(dev->of_node, np) {
478 if (!of_node_name_eq(np, "emc-tables"))
480 err = of_property_read_u32(np, "nvidia,ram-code", &value);
491 if (info->manufacturer_id >= 0 &&
492 info->manufacturer_id != emc->manufacturer_id)
495 if (info->revision_id1 >= 0 &&
496 info->revision_id1 != emc->revision_id1)
499 if (info->revision_id2 >= 0 &&
500 info->revision_id2 != emc->revision_id2)
503 if (info->density != emc->basic_conf4.density)
506 if (info->io_width != emc->basic_conf4.io_width)
509 if (info->arch_type != emc->basic_conf4.arch_type)
529 dev_err(dev, "no memory timings for RAM code %u found in device tree\n",
535 static int emc_read_lpddr_mode_register(struct tegra_emc *emc,
541 u32 val, mr_mask = 0xff;
544 /* clear data-valid interrupt status */
545 writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS);
551 writel_relaxed(val, emc->regs + EMC_MRR);
553 /* wait for the LPDDR2 data-valid interrupt */
554 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val,
558 dev_err(emc->dev, "mode register %u read failed: %d\n",
560 emc->mrr_error = true;
565 val = readl_relaxed(emc->regs + EMC_MRR);
568 return 0;
571 static void emc_read_lpddr_sdram_info(struct tegra_emc *emc,
576 emc_read_lpddr_mode_register(emc, emem_dev, 5, &emc->manufacturer_id);
577 emc_read_lpddr_mode_register(emc, emem_dev, 6, &emc->revision_id1);
578 emc_read_lpddr_mode_register(emc, emem_dev, 7, &emc->revision_id2);
579 emc_read_lpddr_mode_register(emc, emem_dev, 8, &emc->basic_conf4.value);
584 dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u density: %uMbit iowidth: %ubit\n",
585 emem_dev, emc->manufacturer_id,
586 lpddr2_jedec_manufacturer(emc->manufacturer_id),
587 emc->revision_id1, emc->revision_id2,
588 4 >> emc->basic_conf4.arch_type,
589 64 << emc->basic_conf4.density,
590 32 >> emc->basic_conf4.io_width);
593 static int emc_setup_hw(struct tegra_emc *emc)
602 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
605 * Depending on a memory type, DRAM should enter either self-refresh
606 * or power-down state on EMC clock change.
610 dev_err(emc->dev,
611 "bootloader didn't specify DRAM auto-suspend mode\n");
612 return -EINVAL;
615 /* enable EMC and CAR to handshake on PLL divider/source changes */
617 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
620 writel_relaxed(intmask, emc->regs + EMC_INTMASK);
621 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
624 emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
629 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
631 emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
634 emc->dram_bus_width = 16;
636 emc->dram_bus_width = 32;
655 emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG_0);
658 dev_info_once(emc->dev, "%ubit DRAM bus, %u %s %s attached\n",
659 emc->dram_bus_width, emem_numdev, dram_type_str,
663 while (emem_numdev--)
664 emc_read_lpddr_sdram_info(emc, emem_numdev,
669 return 0;
678 struct tegra_emc *emc = arg;
681 if (!emc->num_timings)
682 return clk_get_rate(emc->clk);
684 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
686 for (i = 0; i < emc->num_timings; i++) {
687 if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
690 if (emc->timings[i].rate > max_rate) {
691 i = max(i, 1u) - 1;
693 if (emc->timings[i].rate < min_rate)
697 if (emc->timings[i].rate < min_rate)
700 timing = &emc->timings[i];
705 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
707 return -EINVAL;
710 return timing->rate;
713 static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
717 for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
718 emc->requested_rate[i].min_rate = 0;
719 emc->requested_rate[i].max_rate = ULONG_MAX;
723 static int emc_request_rate(struct tegra_emc *emc,
728 struct emc_rate_request *req = emc->requested_rate;
729 unsigned long min_rate = 0, max_rate = ULONG_MAX;
734 for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
739 min_rate = max(req->min_rate, min_rate);
740 max_rate = min(req->max_rate, max_rate);
745 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
747 return -ERANGE;
751 * EMC rate-changes should go via OPP API because it manages voltage
754 err = dev_pm_opp_set_rate(emc->dev, min_rate);
758 emc->requested_rate[type].min_rate = new_min_rate;
759 emc->requested_rate[type].max_rate = new_max_rate;
761 return 0;
764 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
767 struct emc_rate_request *req = &emc->requested_rate[type];
770 mutex_lock(&emc->rate_lock);
771 ret = emc_request_rate(emc, rate, req->max_rate, type);
772 mutex_unlock(&emc->rate_lock);
777 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
780 struct emc_rate_request *req = &emc->requested_rate[type];
783 mutex_lock(&emc->rate_lock);
784 ret = emc_request_rate(emc, req->min_rate, rate, type);
785 mutex_unlock(&emc->rate_lock);
794 * to control the EMC frequency. The top-level directory can be found here:
796 * /sys/kernel/debug/emc
800 * - available_rates: This file contains a list of valid, space-separated
801 * EMC frequencies.
803 * - min_rate: Writing a value to this file sets the given frequency as the
805 * configured EMC frequency, this will cause the frequency to be
808 * - max_rate: Similarily to the min_rate file, writing a value to this file
810 * the value is lower than the currently configured EMC frequency, this
815 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
819 for (i = 0; i < emc->num_timings; i++)
820 if (rate == emc->timings[i].rate)
828 struct tegra_emc *emc = s->private;
832 for (i = 0; i < emc->num_timings; i++) {
833 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
839 return 0;
845 struct tegra_emc *emc = data;
847 *rate = emc->debugfs.min_rate;
849 return 0;
854 struct tegra_emc *emc = data;
857 if (!tegra_emc_validate_rate(emc, rate))
858 return -EINVAL;
860 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
861 if (err < 0)
864 emc->debugfs.min_rate = rate;
866 return 0;
875 struct tegra_emc *emc = data;
877 *rate = emc->debugfs.max_rate;
879 return 0;
884 struct tegra_emc *emc = data;
887 if (!tegra_emc_validate_rate(emc, rate))
888 return -EINVAL;
890 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
891 if (err < 0)
894 emc->debugfs.max_rate = rate;
896 return 0;
903 static void tegra_emc_debugfs_init(struct tegra_emc *emc)
905 struct device *dev = emc->dev;
909 emc->debugfs.min_rate = ULONG_MAX;
910 emc->debugfs.max_rate = 0;
912 for (i = 0; i < emc->num_timings; i++) {
913 if (emc->timings[i].rate < emc->debugfs.min_rate)
914 emc->debugfs.min_rate = emc->timings[i].rate;
916 if (emc->timings[i].rate > emc->debugfs.max_rate)
917 emc->debugfs.max_rate = emc->timings[i].rate;
920 if (!emc->num_timings) {
921 emc->debugfs.min_rate = clk_get_rate(emc->clk);
922 emc->debugfs.max_rate = emc->debugfs.min_rate;
925 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
926 emc->debugfs.max_rate);
927 if (err < 0) {
928 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
929 emc->debugfs.min_rate, emc->debugfs.max_rate,
930 emc->clk);
933 emc->debugfs.root = debugfs_create_dir("emc", NULL);
935 debugfs_create_file("available_rates", 0444, emc->debugfs.root,
936 emc, &tegra_emc_debug_available_rates_fops);
937 debugfs_create_file("min_rate", 0644, emc->debugfs.root,
938 emc, &tegra_emc_debug_min_rate_fops);
939 debugfs_create_file("max_rate", 0644, emc->debugfs.root,
940 emc, &tegra_emc_debug_max_rate_fops);
957 list_for_each_entry(node, &provider->nodes, node_list) {
958 if (node->id != TEGRA_ICC_EMEM)
963 return ERR_PTR(-ENOMEM);
969 ndata->tag = TEGRA_MC_ICC_TAG_ISO;
970 ndata->node = node;
975 return ERR_PTR(-EPROBE_DEFER);
980 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
981 unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
982 unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
988 * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data
989 * is sampled on both clock edges. This means that EMC clock rate
990 * equals to the peak data-rate.
992 dram_data_bus_width_bytes = emc->dram_bus_width / 8;
996 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
1000 return 0;
1003 static int tegra_emc_interconnect_init(struct tegra_emc *emc)
1009 emc->mc = devm_tegra_memory_controller_get(emc->dev);
1010 if (IS_ERR(emc->mc))
1011 return PTR_ERR(emc->mc);
1013 soc = emc->mc->soc;
1015 emc->provider.dev = emc->dev;
1016 emc->provider.set = emc_icc_set;
1017 emc->provider.data = &emc->provider;
1018 emc->provider.aggregate = soc->icc_ops->aggregate;
1019 emc->provider.xlate_extended = emc_of_icc_xlate_extended;
1021 icc_provider_init(&emc->provider);
1030 node->name = "External Memory Controller";
1031 icc_node_add(node, &emc->provider);
1045 node->name = "External Memory (DRAM)";
1046 icc_node_add(node, &emc->provider);
1048 err = icc_provider_register(&emc->provider);
1052 return 0;
1055 icc_nodes_remove(&emc->provider);
1057 dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
1069 struct tegra_emc *emc = data;
1071 clk_notifier_unregister(emc->clk, &emc->clk_nb);
1074 static int tegra_emc_init_clk(struct tegra_emc *emc)
1078 tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
1080 err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback,
1085 emc->clk = devm_clk_get(emc->dev, NULL);
1086 if (IS_ERR(emc->clk)) {
1087 dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk);
1088 return PTR_ERR(emc->clk);
1091 err = clk_notifier_register(emc->clk, &emc->clk_nb);
1093 dev_err(emc->dev, "failed to register clk notifier: %d\n", err);
1097 err = devm_add_action_or_reset(emc->dev,
1098 devm_tegra_emc_unreg_clk_notifier, emc);
1102 return 0;
1108 struct tegra_emc *emc = dev_get_drvdata(dev);
1121 return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ);
1127 struct tegra_emc *emc = dev_get_drvdata(dev);
1130 writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL);
1133 * busy_time: number of clocks EMC request was accepted
1136 stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT);
1137 stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS);
1138 stat->current_frequency = clk_get_rate(emc->clk);
1141 writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL);
1142 writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL);
1144 return 0;
1153 static int tegra_emc_devfreq_init(struct tegra_emc *emc)
1158 * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold
1164 emc->ondemand_data.upthreshold = 20;
1171 writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL);
1172 writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL);
1173 writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT);
1175 devfreq = devm_devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile,
1177 &emc->ondemand_data);
1179 dev_err(emc->dev, "failed to initialize devfreq: %pe", devfreq);
1183 return 0;
1190 struct tegra_emc *emc;
1193 irq = platform_get_irq(pdev, 0);
1194 if (irq < 0) {
1195 dev_err(&pdev->dev, "please update your device tree\n");
1199 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1200 if (!emc)
1201 return -ENOMEM;
1203 mutex_init(&emc->rate_lock);
1204 emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
1205 emc->dev = &pdev->dev;
1207 emc->regs = devm_platform_ioremap_resource(pdev, 0);
1208 if (IS_ERR(emc->regs))
1209 return PTR_ERR(emc->regs);
1211 err = emc_setup_hw(emc);
1215 np = tegra_emc_find_node_by_ram_code(emc);
1217 err = tegra_emc_load_timings_from_dt(emc, np);
1223 err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0,
1224 dev_name(&pdev->dev), emc);
1226 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1230 err = tegra_emc_init_clk(emc);
1236 err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params);
1240 platform_set_drvdata(pdev, emc);
1241 tegra_emc_rate_requests_init(emc);
1242 tegra_emc_debugfs_init(emc);
1243 tegra_emc_interconnect_init(emc);
1244 tegra_emc_devfreq_init(emc);
1253 return 0;
1257 { .compatible = "nvidia,tegra20-emc", },
1265 .name = "tegra20-emc",
1274 MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver");