Lines Matching +full:0 +full:x3c8
16 .id = 0x00,
21 .reg = 0x34c,
22 .shift = 0,
23 .mask = 0xff,
24 .def = 0x0,
28 .id = 0x01,
33 .reg = 0x228,
37 .reg = 0x2e8,
38 .shift = 0,
39 .mask = 0xff,
40 .def = 0xc2,
44 .id = 0x02,
49 .reg = 0x228,
53 .reg = 0x2f4,
54 .shift = 0,
55 .mask = 0xff,
56 .def = 0xc6,
60 .id = 0x03,
65 .reg = 0x228,
69 .reg = 0x2e8,
71 .mask = 0xff,
72 .def = 0x50,
76 .id = 0x04,
81 .reg = 0x228,
85 .reg = 0x2f4,
87 .mask = 0xff,
88 .def = 0x50,
92 .id = 0x05,
97 .reg = 0x228,
101 .reg = 0x2ec,
102 .shift = 0,
103 .mask = 0xff,
104 .def = 0x50,
108 .id = 0x06,
113 .reg = 0x228,
117 .reg = 0x2f8,
118 .shift = 0,
119 .mask = 0xff,
120 .def = 0x50,
124 .id = 0x0e,
129 .reg = 0x228,
133 .reg = 0x2e0,
134 .shift = 0,
135 .mask = 0xff,
136 .def = 0x13,
140 .id = 0x0f,
145 .reg = 0x228,
149 .reg = 0x2e4,
150 .shift = 0,
151 .mask = 0xff,
152 .def = 0x04,
156 .id = 0x10,
161 .reg = 0x228,
165 .reg = 0x2f0,
166 .shift = 0,
167 .mask = 0xff,
168 .def = 0x50,
172 .id = 0x11,
177 .reg = 0x228,
181 .reg = 0x2fc,
182 .shift = 0,
183 .mask = 0xff,
184 .def = 0x50,
188 .id = 0x15,
193 .reg = 0x228,
197 .reg = 0x318,
198 .shift = 0,
199 .mask = 0xff,
200 .def = 0x24,
204 .id = 0x16,
209 .reg = 0x228,
213 .reg = 0x310,
214 .shift = 0,
215 .mask = 0xff,
216 .def = 0x1e,
220 .id = 0x17,
225 .reg = 0x228,
229 .reg = 0x310,
231 .mask = 0xff,
232 .def = 0x50,
236 .id = 0x1c,
241 .reg = 0x228,
245 .reg = 0x328,
246 .shift = 0,
247 .mask = 0xff,
248 .def = 0x23,
252 .id = 0x1d,
257 .reg = 0x228,
261 .reg = 0x344,
262 .shift = 0,
263 .mask = 0xff,
264 .def = 0x49,
268 .id = 0x1e,
273 .reg = 0x228,
277 .reg = 0x344,
279 .mask = 0xff,
280 .def = 0x1a,
284 .id = 0x1f,
289 .reg = 0x228,
293 .reg = 0x350,
294 .shift = 0,
295 .mask = 0xff,
296 .def = 0x65,
300 .id = 0x22,
305 .reg = 0x22c,
309 .reg = 0x354,
310 .shift = 0,
311 .mask = 0xff,
312 .def = 0x4f,
316 .id = 0x23,
321 .reg = 0x22c,
325 .reg = 0x354,
327 .mask = 0xff,
328 .def = 0x3d,
332 .id = 0x24,
337 .reg = 0x22c,
341 .reg = 0x358,
342 .shift = 0,
343 .mask = 0xff,
344 .def = 0x66,
348 .id = 0x25,
353 .reg = 0x22c,
357 .reg = 0x358,
359 .mask = 0xff,
360 .def = 0xa5,
364 .id = 0x26,
369 .reg = 0x324,
370 .shift = 0,
371 .mask = 0xff,
372 .def = 0x04,
376 .id = 0x27,
381 .reg = 0x320,
382 .shift = 0,
383 .mask = 0xff,
384 .def = 0x04,
388 .id = 0x2b,
393 .reg = 0x22c,
397 .reg = 0x328,
399 .mask = 0xff,
400 .def = 0x80,
404 .id = 0x31,
409 .reg = 0x22c,
413 .reg = 0x2e0,
415 .mask = 0xff,
416 .def = 0x80,
420 .id = 0x32,
425 .reg = 0x22c,
429 .reg = 0x2e4,
431 .mask = 0xff,
432 .def = 0x80,
436 .id = 0x35,
441 .reg = 0x22c,
445 .reg = 0x318,
447 .mask = 0xff,
448 .def = 0x80,
452 .id = 0x36,
457 .reg = 0x22c,
461 .reg = 0x314,
462 .shift = 0,
463 .mask = 0xff,
464 .def = 0x80,
468 .id = 0x38,
473 .reg = 0x324,
475 .mask = 0xff,
476 .def = 0x80,
480 .id = 0x39,
485 .reg = 0x320,
487 .mask = 0xff,
488 .def = 0x80,
492 .id = 0x3b,
497 .reg = 0x22c,
501 .reg = 0x348,
502 .shift = 0,
503 .mask = 0xff,
504 .def = 0x80,
508 .id = 0x3c,
513 .reg = 0x22c,
517 .reg = 0x348,
519 .mask = 0xff,
520 .def = 0x80,
524 .id = 0x3d,
529 .reg = 0x22c,
533 .reg = 0x350,
535 .mask = 0xff,
536 .def = 0x65,
540 .id = 0x3e,
545 .reg = 0x22c,
549 .reg = 0x35c,
550 .shift = 0,
551 .mask = 0xff,
552 .def = 0x80,
556 .id = 0x3f,
561 .reg = 0x22c,
565 .reg = 0x35c,
567 .mask = 0xff,
568 .def = 0x80,
572 .id = 0x40,
577 .reg = 0x230,
578 .bit = 0,
581 .reg = 0x360,
582 .shift = 0,
583 .mask = 0xff,
584 .def = 0x80,
588 .id = 0x41,
593 .reg = 0x230,
597 .reg = 0x360,
599 .mask = 0xff,
600 .def = 0x80,
604 .id = 0x44,
609 .reg = 0x230,
613 .reg = 0x370,
614 .shift = 0,
615 .mask = 0xff,
616 .def = 0x18,
620 .id = 0x46,
625 .reg = 0x230,
629 .reg = 0x374,
630 .shift = 0,
631 .mask = 0xff,
632 .def = 0x80,
636 .id = 0x47,
641 .reg = 0x230,
645 .reg = 0x374,
647 .mask = 0xff,
648 .def = 0x80,
652 .id = 0x4a,
657 .reg = 0x230,
661 .reg = 0x37c,
662 .shift = 0,
663 .mask = 0xff,
664 .def = 0x39,
668 .id = 0x4b,
673 .reg = 0x230,
677 .reg = 0x37c,
679 .mask = 0xff,
680 .def = 0x80,
684 .id = 0x4c,
689 .reg = 0x230,
693 .reg = 0x380,
694 .shift = 0,
695 .mask = 0xff,
696 .def = 0x39,
700 .id = 0x4d,
705 .reg = 0x230,
709 .reg = 0x380,
711 .mask = 0xff,
712 .def = 0x80,
716 .id = 0x4e,
721 .reg = 0x230,
725 .reg = 0x384,
726 .shift = 0,
727 .mask = 0xff,
728 .def = 0x18,
732 .id = 0x50,
737 .reg = 0x230,
741 .reg = 0x388,
742 .shift = 0,
743 .mask = 0xff,
744 .def = 0x80,
748 .id = 0x51,
753 .reg = 0x230,
757 .reg = 0x388,
759 .mask = 0xff,
760 .def = 0x80,
764 .id = 0x54,
769 .reg = 0x230,
773 .reg = 0x390,
774 .shift = 0,
775 .mask = 0xff,
776 .def = 0x9b,
780 .id = 0x55,
785 .reg = 0x230,
789 .reg = 0x390,
791 .mask = 0xff,
792 .def = 0x80,
796 .id = 0x56,
801 .reg = 0x230,
805 .reg = 0x3a4,
806 .shift = 0,
807 .mask = 0xff,
808 .def = 0x04,
812 .id = 0x57,
817 .reg = 0x230,
821 .reg = 0x3a4,
823 .mask = 0xff,
824 .def = 0x80,
828 .id = 0x58,
834 .reg = 0x230,
838 .reg = 0x3c8,
839 .shift = 0,
840 .mask = 0xff,
841 .def = 0x1a,
845 .id = 0x59,
851 .reg = 0x230,
855 .reg = 0x3c8,
857 .mask = 0xff,
858 .def = 0x80,
862 .id = 0x5a,
867 .reg = 0x230,
871 .reg = 0x2f0,
873 .mask = 0xff,
874 .def = 0x50,
878 .id = 0x60,
883 .reg = 0x234,
884 .bit = 0,
887 .reg = 0x3b8,
888 .shift = 0,
889 .mask = 0xff,
890 .def = 0x49,
894 .id = 0x61,
899 .reg = 0x234,
903 .reg = 0x3bc,
904 .shift = 0,
905 .mask = 0xff,
906 .def = 0x49,
910 .id = 0x62,
915 .reg = 0x234,
919 .reg = 0x3c0,
920 .shift = 0,
921 .mask = 0xff,
922 .def = 0x49,
926 .id = 0x63,
931 .reg = 0x234,
935 .reg = 0x3c4,
936 .shift = 0,
937 .mask = 0xff,
938 .def = 0x49,
942 .id = 0x64,
947 .reg = 0x234,
951 .reg = 0x3b8,
953 .mask = 0xff,
954 .def = 0x80,
958 .id = 0x65,
963 .reg = 0x234,
967 .reg = 0x3bc,
969 .mask = 0xff,
970 .def = 0x80,
974 .id = 0x66,
979 .reg = 0x234,
983 .reg = 0x3c0,
985 .mask = 0xff,
986 .def = 0x80,
990 .id = 0x67,
995 .reg = 0x234,
999 .reg = 0x3c4,
1001 .mask = 0xff,
1002 .def = 0x80,
1006 .id = 0x6c,
1011 .reg = 0x234,
1015 .reg = 0x394,
1016 .shift = 0,
1017 .mask = 0xff,
1018 .def = 0x1a,
1022 .id = 0x6d,
1027 .reg = 0x234,
1031 .reg = 0x394,
1033 .mask = 0xff,
1034 .def = 0x80,
1038 .id = 0x72,
1043 .reg = 0x234,
1047 .reg = 0x398,
1048 .shift = 0,
1049 .mask = 0xff,
1050 .def = 0x80,
1054 .id = 0x73,
1059 .reg = 0x234,
1063 .reg = 0x3c8,
1064 .shift = 0,
1065 .mask = 0xff,
1066 .def = 0x50,
1073 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1074 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1075 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1076 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1077 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1078 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1079 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
1080 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1081 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1082 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
1083 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1084 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1085 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1086 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1087 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1088 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1089 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1090 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1091 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1092 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1093 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1094 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1095 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1122 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
1123 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
1124 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
1125 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
1126 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
1127 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
1128 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
1129 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
1130 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1131 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
1132 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
1133 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
1134 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
1135 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
1136 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
1137 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1138 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1139 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1140 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1141 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1142 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1143 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1144 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1145 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1151 return 0; in tegra124_mc_icc_set()
1169 return 0; in tegra124_mc_icc_aggreate()
1177 unsigned int i, idx = spec->args[0]; in tegra124_mc_of_icc_xlate_extended()
1209 for (i = 0; i < mc->soc->num_clients; i++) { in tegra124_mc_of_icc_xlate_extended()
1266 .client_id_mask = 0x7f,
1300 .client_id_mask = 0x7f,