Lines Matching +full:cs +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
42 #define GPMC_REVISION 0x00
43 #define GPMC_SYSCONFIG 0x10
44 #define GPMC_SYSSTATUS 0x14
45 #define GPMC_IRQSTATUS 0x18
46 #define GPMC_IRQENABLE 0x1c
47 #define GPMC_TIMEOUT_CONTROL 0x40
48 #define GPMC_ERR_ADDRESS 0x44
49 #define GPMC_ERR_TYPE 0x48
50 #define GPMC_CONFIG 0x50
51 #define GPMC_STATUS 0x54
52 #define GPMC_PREFETCH_CONFIG1 0x1e0
53 #define GPMC_PREFETCH_CONFIG2 0x1e4
54 #define GPMC_PREFETCH_CONTROL 0x1ec
55 #define GPMC_PREFETCH_STATUS 0x1f0
56 #define GPMC_ECC_CONFIG 0x1f4
57 #define GPMC_ECC_CONTROL 0x1f8
58 #define GPMC_ECC_SIZE_CONFIG 0x1fc
59 #define GPMC_ECC1_RESULT 0x200
60 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
61 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
62 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
63 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
64 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
65 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
66 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
69 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
70 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
71 #define GPMC_ECC_CTRL_ECCREG1 0x001
72 #define GPMC_ECC_CTRL_ECCREG2 0x002
73 #define GPMC_ECC_CTRL_ECCREG3 0x003
74 #define GPMC_ECC_CTRL_ECCREG4 0x004
75 #define GPMC_ECC_CTRL_ECCREG5 0x005
76 #define GPMC_ECC_CTRL_ECCREG6 0x006
77 #define GPMC_ECC_CTRL_ECCREG7 0x007
78 #define GPMC_ECC_CTRL_ECCREG8 0x008
79 #define GPMC_ECC_CTRL_ECCREG9 0x009
83 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
92 #define GPMC_CS0_OFFSET 0x60
93 #define GPMC_CS_SIZE 0x30
94 #define GPMC_BCH_SIZE 0x10
103 #define GPMC_MEM_START 0x1000000
104 #define GPMC_MEM_END 0x3FFFFFFF
110 #define ENABLE_PREFETCH (0x1 << 7)
113 #define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
114 #define GPMC_REVISION_MINOR(l) ((l) & 0xf)
116 #define GPMC_HAS_WR_ACCESS 0x1
117 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
118 #define GPMC_HAS_MUX_AAD 0x4
122 #define GPMC_CS_CONFIG1 0x00
123 #define GPMC_CS_CONFIG2 0x04
124 #define GPMC_CS_CONFIG3 0x08
125 #define GPMC_CS_CONFIG4 0x0c
126 #define GPMC_CS_CONFIG5 0x10
127 #define GPMC_CS_CONFIG6 0x14
128 #define GPMC_CS_CONFIG7 0x18
129 #define GPMC_CS_NAND_COMMAND 0x1c
130 #define GPMC_CS_NAND_ADDRESS 0x20
131 #define GPMC_CS_NAND_DATA 0x24
134 #define GPMC_CONFIG_RDY_BSY 0x00000001
135 #define GPMC_CONFIG_DEV_SIZE 0x00000002
136 #define GPMC_CONFIG_DEV_TYPE 0x00000003
141 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
144 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
163 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
172 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
175 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
181 #define GPMC_DEVICETYPE_NOR 0
183 #define GPMC_CONFIG_WRITEPROTECT 0x00000010
184 #define WR_RD_PIN_MONITORING 0x00600000
187 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
201 #define GPMC_CS_RESERVED (1 << 0)
207 /* Structure to save gpmc cs context */
258 /* Define chip-selects as reserved by default until probe completes */
278 void gpmc_cs_write_reg(int cs, int idx, u32 val) in gpmc_cs_write_reg() argument
282 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_write_reg()
286 static u32 gpmc_cs_read_reg(int cs, int idx) in gpmc_cs_read_reg() argument
290 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_read_reg()
306 * gpmc_get_clk_period - get period of selected clock domain in ps
307 * @cs: Chip Select Region.
310 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
313 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) in gpmc_get_clk_period() argument
322 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); in gpmc_get_clk_period()
323 div = (l & 0x03) + 1; in gpmc_get_clk_period()
335 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, in gpmc_ns_to_clk_ticks() argument
341 tick_ps = gpmc_get_clk_period(cs, cd); in gpmc_ns_to_clk_ticks()
343 return (time_ns * 1000 + tick_ps - 1) / tick_ps; in gpmc_ns_to_clk_ticks()
348 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK); in gpmc_ns_to_ticks()
358 return (time_ps + tick_ps - 1) / tick_ps; in gpmc_ps_to_ticks()
373 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) in gpmc_cs_modify_reg() argument
377 l = gpmc_cs_read_reg(cs, reg); in gpmc_cs_modify_reg()
382 gpmc_cs_write_reg(cs, reg, l); in gpmc_cs_modify_reg()
385 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) in gpmc_cs_bool_timings() argument
387 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, in gpmc_cs_bool_timings()
389 p->time_para_granularity); in gpmc_cs_bool_timings()
390 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, in gpmc_cs_bool_timings()
391 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); in gpmc_cs_bool_timings()
392 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, in gpmc_cs_bool_timings()
393 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); in gpmc_cs_bool_timings()
394 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, in gpmc_cs_bool_timings()
395 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); in gpmc_cs_bool_timings()
396 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, in gpmc_cs_bool_timings()
397 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay); in gpmc_cs_bool_timings()
398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, in gpmc_cs_bool_timings()
400 p->cycle2cyclesamecsen); in gpmc_cs_bool_timings()
401 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, in gpmc_cs_bool_timings()
403 p->cycle2cyclediffcsen); in gpmc_cs_bool_timings()
408 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs, in gpmc_clk_ticks_to_ns() argument
411 return ticks * gpmc_get_clk_period(cs, cd) / 1000; in gpmc_clk_ticks_to_ns()
415 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
416 * @cs: Chip Select Region
421 * If 0, maximum is as high as @st_bit and @end_bit allow.
427 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
428 * Where x ns -- y ns result in the same tick value.
430 * @noval: Parameter values equal to 0 are not printed.
436 int cs, int reg, int st_bit, int end_bit, int max, in get_gpmc_timing_reg() argument
448 l = gpmc_cs_read_reg(cs, reg); in get_gpmc_timing_reg()
449 nr_bits = end_bit - st_bit + 1; in get_gpmc_timing_reg()
450 mask = (1 << nr_bits) - 1; in get_gpmc_timing_reg()
457 if (noval && (l == 0)) in get_gpmc_timing_reg()
458 return 0; in get_gpmc_timing_reg()
462 unsigned int time_ns_min = 0; in get_gpmc_timing_reg()
465 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1; in get_gpmc_timing_reg()
466 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd); in get_gpmc_timing_reg()
467 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", in get_gpmc_timing_reg()
479 #define GPMC_PRINT_CONFIG(cs, config) \ argument
480 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
481 gpmc_cs_read_reg(cs, config))
483 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
485 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
487 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
489 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
491 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
493 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
495 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
497 static void gpmc_show_regs(int cs, const char *desc) in gpmc_show_regs() argument
499 pr_info("gpmc cs%i %s:\n", cs, desc); in gpmc_show_regs()
500 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); in gpmc_show_regs()
501 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); in gpmc_show_regs()
502 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); in gpmc_show_regs()
503 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4); in gpmc_show_regs()
504 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5); in gpmc_show_regs()
505 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6); in gpmc_show_regs()
509 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
512 static void gpmc_cs_show_timings(int cs, const char *desc) in gpmc_cs_show_timings() argument
514 gpmc_show_regs(cs, desc); in gpmc_cs_show_timings()
516 pr_info("gpmc cs%i access configuration:\n", cs); in gpmc_cs_show_timings()
517 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); in gpmc_cs_show_timings()
518 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); in gpmc_cs_show_timings()
520 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width"); in gpmc_cs_show_timings()
521 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin"); in gpmc_cs_show_timings()
522 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write"); in gpmc_cs_show_timings()
523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read"); in gpmc_cs_show_timings()
526 "burst-length"); in gpmc_cs_show_timings()
527 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write"); in gpmc_cs_show_timings()
528 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write"); in gpmc_cs_show_timings()
529 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read"); in gpmc_cs_show_timings()
530 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read"); in gpmc_cs_show_timings()
531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap"); in gpmc_cs_show_timings()
533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay"); in gpmc_cs_show_timings()
535 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay"); in gpmc_cs_show_timings()
537 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay"); in gpmc_cs_show_timings()
538 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay"); in gpmc_cs_show_timings()
540 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen"); in gpmc_cs_show_timings()
541 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen"); in gpmc_cs_show_timings()
543 pr_info("gpmc cs%i timings configuration:\n", cs); in gpmc_cs_show_timings()
544 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); in gpmc_cs_show_timings()
545 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); in gpmc_cs_show_timings()
546 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); in gpmc_cs_show_timings()
548 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns"); in gpmc_cs_show_timings()
549 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns"); in gpmc_cs_show_timings()
550 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns"); in gpmc_cs_show_timings()
552 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns"); in gpmc_cs_show_timings()
554 "adv-aad-mux-rd-off-ns"); in gpmc_cs_show_timings()
556 "adv-aad-mux-wr-off-ns"); in gpmc_cs_show_timings()
559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns"); in gpmc_cs_show_timings()
560 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns"); in gpmc_cs_show_timings()
562 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns"); in gpmc_cs_show_timings()
563 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns"); in gpmc_cs_show_timings()
565 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns"); in gpmc_cs_show_timings()
566 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns"); in gpmc_cs_show_timings()
568 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns"); in gpmc_cs_show_timings()
569 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns"); in gpmc_cs_show_timings()
570 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns"); in gpmc_cs_show_timings()
572 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns"); in gpmc_cs_show_timings()
574 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns"); in gpmc_cs_show_timings()
575 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns"); in gpmc_cs_show_timings()
579 "wait-monitoring-ns", GPMC_CD_CLK); in gpmc_cs_show_timings()
582 "clk-activation-ns", GPMC_CD_FCLK); in gpmc_cs_show_timings()
584 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns"); in gpmc_cs_show_timings()
585 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns"); in gpmc_cs_show_timings()
588 static inline void gpmc_cs_show_timings(int cs, const char *desc) in gpmc_cs_show_timings() argument
594 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
598 * @cs: Chip Select Region.
603 * If 0, maximum is as high as @st_bit and @end_bit allow.
607 * @return: 0 on success, -1 on error.
609 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max, in set_gpmc_timing_reg() argument
615 if (time == 0) in set_gpmc_timing_reg()
616 ticks = 0; in set_gpmc_timing_reg()
618 ticks = gpmc_ns_to_clk_ticks(time, cs, cd); in set_gpmc_timing_reg()
619 nr_bits = end_bit - st_bit + 1; in set_gpmc_timing_reg()
620 mask = (1 << nr_bits) - 1; in set_gpmc_timing_reg()
626 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n", in set_gpmc_timing_reg()
627 __func__, cs, name, time, ticks, max); in set_gpmc_timing_reg()
629 return -1; in set_gpmc_timing_reg()
632 l = gpmc_cs_read_reg(cs, reg); in set_gpmc_timing_reg()
634 pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", in set_gpmc_timing_reg()
635 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, in set_gpmc_timing_reg()
640 gpmc_cs_write_reg(cs, reg, l); in set_gpmc_timing_reg()
642 return 0; in set_gpmc_timing_reg()
646 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
648 * read --> don't sample bus too early
649 * write --> data is longer on bus
654 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
655 * div <= 0 check.
658 * @return: -1 on failure to scale, else proper divider > 0.
664 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1; in gpmc_calc_waitmonitoring_divider()
668 return -1; in gpmc_calc_waitmonitoring_divider()
669 if (div <= 0) in gpmc_calc_waitmonitoring_divider()
676 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
679 * Else, returns -1.
686 return -1; in gpmc_calc_divider()
687 if (div <= 0) in gpmc_calc_divider()
694 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
695 * @cs: Chip Select Region.
698 * @return: 0 on success, -1 on error.
700 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, in gpmc_cs_set_timings() argument
706 div = gpmc_calc_divider(t->sync_clk); in gpmc_cs_set_timings()
707 if (div < 0) in gpmc_cs_set_timings()
708 return -EINVAL; in gpmc_cs_set_timings()
713 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for in gpmc_cs_set_timings()
723 if (!s->sync_read && !s->sync_write && in gpmc_cs_set_timings()
724 (s->wait_on_read || s->wait_on_write) in gpmc_cs_set_timings()
726 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring); in gpmc_cs_set_timings()
727 if (div < 0) { in gpmc_cs_set_timings()
730 t->wait_monitoring in gpmc_cs_set_timings()
732 return -ENXIO; in gpmc_cs_set_timings()
736 ret = 0; in gpmc_cs_set_timings()
737 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on, in gpmc_cs_set_timings()
739 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off, in gpmc_cs_set_timings()
741 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off, in gpmc_cs_set_timings()
744 return -ENXIO; in gpmc_cs_set_timings()
746 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on, in gpmc_cs_set_timings()
748 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off, in gpmc_cs_set_timings()
750 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off, in gpmc_cs_set_timings()
753 return -ENXIO; in gpmc_cs_set_timings()
756 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0, in gpmc_cs_set_timings()
757 t->adv_aad_mux_on, GPMC_CD_FCLK, in gpmc_cs_set_timings()
759 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0, in gpmc_cs_set_timings()
760 t->adv_aad_mux_rd_off, GPMC_CD_FCLK, in gpmc_cs_set_timings()
762 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0, in gpmc_cs_set_timings()
763 t->adv_aad_mux_wr_off, GPMC_CD_FCLK, in gpmc_cs_set_timings()
766 return -ENXIO; in gpmc_cs_set_timings()
769 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on, in gpmc_cs_set_timings()
771 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off, in gpmc_cs_set_timings()
774 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0, in gpmc_cs_set_timings()
775 t->oe_aad_mux_on, GPMC_CD_FCLK, in gpmc_cs_set_timings()
777 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0, in gpmc_cs_set_timings()
778 t->oe_aad_mux_off, GPMC_CD_FCLK, in gpmc_cs_set_timings()
781 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on, in gpmc_cs_set_timings()
783 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off, in gpmc_cs_set_timings()
786 return -ENXIO; in gpmc_cs_set_timings()
788 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle, in gpmc_cs_set_timings()
790 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle, in gpmc_cs_set_timings()
792 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access, in gpmc_cs_set_timings()
794 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0, in gpmc_cs_set_timings()
795 t->page_burst_access, GPMC_CD_FCLK, in gpmc_cs_set_timings()
798 return -ENXIO; in gpmc_cs_set_timings()
800 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0, in gpmc_cs_set_timings()
801 t->bus_turnaround, GPMC_CD_FCLK, in gpmc_cs_set_timings()
803 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0, in gpmc_cs_set_timings()
804 t->cycle2cycle_delay, GPMC_CD_FCLK, in gpmc_cs_set_timings()
807 return -ENXIO; in gpmc_cs_set_timings()
810 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0, in gpmc_cs_set_timings()
811 t->wr_data_mux_bus, GPMC_CD_FCLK, in gpmc_cs_set_timings()
814 return -ENXIO; in gpmc_cs_set_timings()
817 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0, in gpmc_cs_set_timings()
818 t->wr_access, GPMC_CD_FCLK, in gpmc_cs_set_timings()
821 return -ENXIO; in gpmc_cs_set_timings()
824 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); in gpmc_cs_set_timings()
825 l &= ~0x03; in gpmc_cs_set_timings()
826 l |= (div - 1); in gpmc_cs_set_timings()
827 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); in gpmc_cs_set_timings()
829 ret = 0; in gpmc_cs_set_timings()
830 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19, in gpmc_cs_set_timings()
832 t->wait_monitoring, GPMC_CD_CLK, in gpmc_cs_set_timings()
834 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26, in gpmc_cs_set_timings()
836 t->clk_activation, GPMC_CD_FCLK, in gpmc_cs_set_timings()
839 return -ENXIO; in gpmc_cs_set_timings()
842 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", in gpmc_cs_set_timings()
843 cs, (div * gpmc_get_fclk_period()) / 1000, div); in gpmc_cs_set_timings()
846 gpmc_cs_bool_timings(cs, &t->bool_timings); in gpmc_cs_set_timings()
847 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings"); in gpmc_cs_set_timings()
849 return 0; in gpmc_cs_set_timings()
852 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size) in gpmc_cs_set_memconf() argument
861 if (base & (size - 1)) in gpmc_cs_set_memconf()
862 return -EINVAL; in gpmc_cs_set_memconf()
865 mask = (1 << GPMC_SECTION_SHIFT) - size; in gpmc_cs_set_memconf()
869 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); in gpmc_cs_set_memconf()
874 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); in gpmc_cs_set_memconf()
876 return 0; in gpmc_cs_set_memconf()
879 static void gpmc_cs_enable_mem(int cs) in gpmc_cs_enable_mem() argument
883 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); in gpmc_cs_enable_mem()
885 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); in gpmc_cs_enable_mem()
888 static void gpmc_cs_disable_mem(int cs) in gpmc_cs_disable_mem() argument
892 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); in gpmc_cs_disable_mem()
894 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); in gpmc_cs_disable_mem()
897 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) in gpmc_cs_get_memconf() argument
902 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); in gpmc_cs_get_memconf()
903 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; in gpmc_cs_get_memconf()
904 mask = (l >> 8) & 0x0f; in gpmc_cs_get_memconf()
905 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); in gpmc_cs_get_memconf()
908 static int gpmc_cs_mem_enabled(int cs) in gpmc_cs_mem_enabled() argument
912 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); in gpmc_cs_mem_enabled()
916 static void gpmc_cs_set_reserved(int cs, int reserved) in gpmc_cs_set_reserved() argument
918 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; in gpmc_cs_set_reserved()
920 gpmc->flags |= GPMC_CS_RESERVED; in gpmc_cs_set_reserved()
923 static bool gpmc_cs_reserved(int cs) in gpmc_cs_reserved() argument
925 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; in gpmc_cs_reserved()
927 return gpmc->flags & GPMC_CS_RESERVED; in gpmc_cs_reserved()
934 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); in gpmc_mem_align()
935 order = GPMC_CHUNK_SHIFT - 1; in gpmc_mem_align()
944 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) in gpmc_cs_insert_mem() argument
946 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; in gpmc_cs_insert_mem()
947 struct resource *res = &gpmc->mem; in gpmc_cs_insert_mem()
952 res->start = base; in gpmc_cs_insert_mem()
953 res->end = base + size - 1; in gpmc_cs_insert_mem()
960 static int gpmc_cs_delete_mem(int cs) in gpmc_cs_delete_mem() argument
962 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; in gpmc_cs_delete_mem()
963 struct resource *res = &gpmc->mem; in gpmc_cs_delete_mem()
968 res->start = 0; in gpmc_cs_delete_mem()
969 res->end = 0; in gpmc_cs_delete_mem()
975 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) in gpmc_cs_request() argument
977 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; in gpmc_cs_request()
978 struct resource *res = &gpmc->mem; in gpmc_cs_request()
979 int r = -1; in gpmc_cs_request()
981 if (cs >= gpmc_cs_num) { in gpmc_cs_request()
982 pr_err("%s: requested chip-select is disabled\n", __func__); in gpmc_cs_request()
983 return -ENODEV; in gpmc_cs_request()
987 return -ENOMEM; in gpmc_cs_request()
991 if (gpmc_cs_reserved(cs)) in gpmc_cs_request()
992 return -EBUSY; in gpmc_cs_request()
994 if (gpmc_cs_mem_enabled(cs)) in gpmc_cs_request()
995 r = adjust_resource(res, res->start & ~(size - 1), size); in gpmc_cs_request()
996 if (r < 0) in gpmc_cs_request()
997 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, in gpmc_cs_request()
999 if (r < 0) in gpmc_cs_request()
1002 /* Disable CS while changing base address and size mask */ in gpmc_cs_request()
1003 gpmc_cs_disable_mem(cs); in gpmc_cs_request()
1005 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res)); in gpmc_cs_request()
1006 if (r < 0) { in gpmc_cs_request()
1011 /* Enable CS */ in gpmc_cs_request()
1012 gpmc_cs_enable_mem(cs); in gpmc_cs_request()
1013 *base = res->start; in gpmc_cs_request()
1014 gpmc_cs_set_reserved(cs, 1); in gpmc_cs_request()
1016 return 0; in gpmc_cs_request()
1020 void gpmc_cs_free(int cs) in gpmc_cs_free() argument
1026 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { in gpmc_cs_free()
1027 WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs); in gpmc_cs_free()
1030 gpmc = &gpmc_cs[cs]; in gpmc_cs_free()
1031 res = &gpmc->mem; in gpmc_cs_free()
1033 gpmc_cs_disable_mem(cs); in gpmc_cs_free()
1034 if (res->flags) in gpmc_cs_free()
1036 gpmc_cs_set_reserved(cs, 0); in gpmc_cs_free()
1052 if (!gpmc_is_valid_waitpin(p->wait_pin)) in gpmc_alloc_waitpin()
1053 return -EINVAL; in gpmc_alloc_waitpin()
1055 waitpin = &gpmc->waitpins[p->wait_pin]; in gpmc_alloc_waitpin()
1057 if (!waitpin->desc) { in gpmc_alloc_waitpin()
1062 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip, in gpmc_alloc_waitpin()
1063 p->wait_pin, "WAITPIN", in gpmc_alloc_waitpin()
1068 if (IS_ERR(waitpin_desc) && ret != -EBUSY) in gpmc_alloc_waitpin()
1072 waitpin->desc = waitpin_desc; in gpmc_alloc_waitpin()
1073 waitpin->pin = p->wait_pin; in gpmc_alloc_waitpin()
1074 waitpin->polarity = p->wait_pin_polarity; in gpmc_alloc_waitpin()
1077 if (p->wait_pin_polarity != waitpin->polarity || in gpmc_alloc_waitpin()
1078 p->wait_pin != waitpin->pin) { in gpmc_alloc_waitpin()
1079 dev_err(gpmc->dev, in gpmc_alloc_waitpin()
1080 "shared-wait-pin: invalid configuration\n"); in gpmc_alloc_waitpin()
1081 return -EINVAL; in gpmc_alloc_waitpin()
1083 dev_info(gpmc->dev, "shared wait-pin: %d\n", waitpin->pin); in gpmc_alloc_waitpin()
1086 return 0; in gpmc_alloc_waitpin()
1093 gpiochip_free_own_desc(gpmc->waitpins[wait_pin].desc); in gpmc_free_waitpin()
1097 * gpmc_configure - write request to configure gpmc
1118 return -EINVAL; in gpmc_configure()
1121 return 0; in gpmc_configure()
1138 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1140 * @cs: GPMC chip select number on which the NAND sits. The
1143 * Returns NULL on error e.g. invalid cs.
1145 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs) in gpmc_omap_get_nand_ops() argument
1149 if (cs >= gpmc_cs_num) in gpmc_omap_get_nand_ops()
1152 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + in gpmc_omap_get_nand_ops()
1153 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; in gpmc_omap_get_nand_ops()
1154 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + in gpmc_omap_get_nand_ops()
1155 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; in gpmc_omap_get_nand_ops()
1156 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + in gpmc_omap_get_nand_ops()
1157 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; in gpmc_omap_get_nand_ops()
1158 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; in gpmc_omap_get_nand_ops()
1159 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; in gpmc_omap_get_nand_ops()
1160 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; in gpmc_omap_get_nand_ops()
1161 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; in gpmc_omap_get_nand_ops()
1162 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; in gpmc_omap_get_nand_ops()
1163 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; in gpmc_omap_get_nand_ops()
1164 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; in gpmc_omap_get_nand_ops()
1165 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; in gpmc_omap_get_nand_ops()
1167 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { in gpmc_omap_get_nand_ops()
1168 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + in gpmc_omap_get_nand_ops()
1170 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + in gpmc_omap_get_nand_ops()
1172 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + in gpmc_omap_get_nand_ops()
1174 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + in gpmc_omap_get_nand_ops()
1176 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 + in gpmc_omap_get_nand_ops()
1178 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 + in gpmc_omap_get_nand_ops()
1180 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 + in gpmc_omap_get_nand_ops()
1240 memset(&dev_t, 0, sizeof(dev_t)); in gpmc_omap_onenand_calc_sync_timings()
1242 if (!s->sync_write) { in gpmc_omap_onenand_calc_sync_timings()
1267 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq, in gpmc_omap_onenand_set_timings() argument
1275 gpmc_read_settings_dt(dev->of_node, &gpmc_s); in gpmc_omap_onenand_set_timings()
1277 info->sync_read = gpmc_s.sync_read; in gpmc_omap_onenand_set_timings()
1278 info->sync_write = gpmc_s.sync_write; in gpmc_omap_onenand_set_timings()
1279 info->burst_len = gpmc_s.burst_len; in gpmc_omap_onenand_set_timings()
1282 return 0; in gpmc_omap_onenand_set_timings()
1286 ret = gpmc_cs_program_settings(cs, &gpmc_s); in gpmc_omap_onenand_set_timings()
1287 if (ret < 0) in gpmc_omap_onenand_set_timings()
1290 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); in gpmc_omap_onenand_set_timings()
1300 hwirq += 8 - GPMC_NR_NAND_IRQS; in gpmc_irq_endis()
1309 return 0; in gpmc_irq_endis()
1314 gpmc_irq_endis(p->hwirq, false); in gpmc_irq_disable()
1319 gpmc_irq_endis(p->hwirq, true); in gpmc_irq_enable()
1324 gpmc_irq_endis(d->hwirq, false); in gpmc_irq_mask()
1329 gpmc_irq_endis(d->hwirq, true); in gpmc_irq_unmask()
1341 hwirq += 8 - GPMC_NR_NAND_IRQS; in gpmc_irq_edge_config()
1354 unsigned int hwirq = d->hwirq; in gpmc_irq_ack()
1358 hwirq += 8 - GPMC_NR_NAND_IRQS; in gpmc_irq_ack()
1367 if (d->hwirq < GPMC_NR_NAND_IRQS) in gpmc_irq_set_type()
1368 return -EINVAL; in gpmc_irq_set_type()
1372 gpmc_irq_edge_config(d->hwirq, false); in gpmc_irq_set_type()
1374 gpmc_irq_edge_config(d->hwirq, true); in gpmc_irq_set_type()
1376 return -EINVAL; in gpmc_irq_set_type()
1378 return 0; in gpmc_irq_set_type()
1384 struct gpmc_device *gpmc = d->host_data; in gpmc_irq_map()
1389 irq_set_chip_and_handler(virq, &gpmc->irq_chip, in gpmc_irq_map()
1392 irq_set_chip_and_handler(virq, &gpmc->irq_chip, in gpmc_irq_map()
1396 return 0; in gpmc_irq_map()
1416 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) { in gpmc_handle_irq()
1419 regvalx >>= 8 - GPMC_NR_NAND_IRQS; in gpmc_handle_irq()
1424 dev_warn(gpmc->dev, in gpmc_handle_irq()
1444 gpmc_write_reg(GPMC_IRQENABLE, 0); in gpmc_setup_irq()
1450 gpmc->irq_chip.name = "gpmc"; in gpmc_setup_irq()
1451 gpmc->irq_chip.irq_enable = gpmc_irq_enable; in gpmc_setup_irq()
1452 gpmc->irq_chip.irq_disable = gpmc_irq_disable; in gpmc_setup_irq()
1453 gpmc->irq_chip.irq_ack = gpmc_irq_ack; in gpmc_setup_irq()
1454 gpmc->irq_chip.irq_mask = gpmc_irq_mask; in gpmc_setup_irq()
1455 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask; in gpmc_setup_irq()
1456 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type; in gpmc_setup_irq()
1458 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node, in gpmc_setup_irq()
1459 gpmc->nirqs, in gpmc_setup_irq()
1463 dev_err(gpmc->dev, "IRQ domain add failed\n"); in gpmc_setup_irq()
1464 return -ENODEV; in gpmc_setup_irq()
1467 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc); in gpmc_setup_irq()
1469 dev_err(gpmc->dev, "failed to request irq %d: %d\n", in gpmc_setup_irq()
1470 gpmc->irq, rc); in gpmc_setup_irq()
1482 free_irq(gpmc->irq, gpmc); in gpmc_free_irq()
1484 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) in gpmc_free_irq()
1490 return 0; in gpmc_free_irq()
1495 int cs; in gpmc_mem_exit() local
1497 for (cs = 0; cs < gpmc_cs_num; cs++) { in gpmc_mem_exit()
1498 if (!gpmc_cs_mem_enabled(cs)) in gpmc_mem_exit()
1500 gpmc_cs_delete_mem(cs); in gpmc_mem_exit()
1506 int cs; in gpmc_mem_init() local
1508 if (!gpmc->data) { in gpmc_mem_init()
1513 gpmc_mem_root.start = gpmc->data->start; in gpmc_mem_init()
1514 gpmc_mem_root.end = gpmc->data->end; in gpmc_mem_init()
1518 for (cs = 0; cs < gpmc_cs_num; cs++) { in gpmc_mem_init()
1521 if (!gpmc_cs_mem_enabled(cs)) in gpmc_mem_init()
1523 gpmc_cs_get_memconf(cs, &base, &size); in gpmc_mem_init()
1524 if (gpmc_cs_insert_mem(cs, base, size)) { in gpmc_mem_init()
1525 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", in gpmc_mem_init()
1526 __func__, cs, base, base + size); in gpmc_mem_init()
1527 gpmc_cs_disable_mem(cs); in gpmc_mem_init()
1539 temp = (temp + div - 1) / div; in gpmc_round_ps_to_sync_clk()
1551 temp = dev_t->t_avdp_r; in gpmc_calc_sync_read_timings()
1558 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh); in gpmc_calc_sync_read_timings()
1559 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); in gpmc_calc_sync_read_timings()
1561 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); in gpmc_calc_sync_read_timings()
1564 temp = dev_t->t_oeasu; /* XXX: remove this ? */ in gpmc_calc_sync_read_timings()
1566 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach); in gpmc_calc_sync_read_timings()
1567 temp = max_t(u32, temp, gpmc_t->adv_rd_off + in gpmc_calc_sync_read_timings()
1568 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe)); in gpmc_calc_sync_read_timings()
1570 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); in gpmc_calc_sync_read_timings()
1577 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk); in gpmc_calc_sync_read_timings()
1578 temp += gpmc_t->clk_activation; in gpmc_calc_sync_read_timings()
1579 if (dev_t->cyc_oe) in gpmc_calc_sync_read_timings()
1580 temp = max_t(u32, temp, gpmc_t->oe_on + in gpmc_calc_sync_read_timings()
1581 gpmc_ticks_to_ps(dev_t->cyc_oe)); in gpmc_calc_sync_read_timings()
1582 gpmc_t->access = gpmc_round_ps_to_ticks(temp); in gpmc_calc_sync_read_timings()
1584 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); in gpmc_calc_sync_read_timings()
1585 gpmc_t->cs_rd_off = gpmc_t->oe_off; in gpmc_calc_sync_read_timings()
1588 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez); in gpmc_calc_sync_read_timings()
1589 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) + in gpmc_calc_sync_read_timings()
1590 gpmc_t->access; in gpmc_calc_sync_read_timings()
1592 if (dev_t->t_ce_rdyz) in gpmc_calc_sync_read_timings()
1593 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz); in gpmc_calc_sync_read_timings()
1594 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); in gpmc_calc_sync_read_timings()
1596 return 0; in gpmc_calc_sync_read_timings()
1606 temp = dev_t->t_avdp_w; in gpmc_calc_sync_write_timings()
1609 gpmc_t->clk_activation + dev_t->t_avdh); in gpmc_calc_sync_write_timings()
1610 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); in gpmc_calc_sync_write_timings()
1612 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); in gpmc_calc_sync_write_timings()
1615 temp = max_t(u32, dev_t->t_weasu, in gpmc_calc_sync_write_timings()
1616 gpmc_t->clk_activation + dev_t->t_rdyo); in gpmc_calc_sync_write_timings()
1622 gpmc_t->adv_wr_off + dev_t->t_aavdh); in gpmc_calc_sync_write_timings()
1623 temp = max_t(u32, temp, gpmc_t->adv_wr_off + in gpmc_calc_sync_write_timings()
1624 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); in gpmc_calc_sync_write_timings()
1626 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); in gpmc_calc_sync_write_timings()
1630 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); in gpmc_calc_sync_write_timings()
1632 gpmc_t->we_on = gpmc_t->wr_data_mux_bus; in gpmc_calc_sync_write_timings()
1636 gpmc_t->wr_access = gpmc_t->access; in gpmc_calc_sync_write_timings()
1639 temp = gpmc_t->we_on + dev_t->t_wpl; in gpmc_calc_sync_write_timings()
1641 gpmc_t->wr_access + gpmc_ticks_to_ps(1)); in gpmc_calc_sync_write_timings()
1643 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl)); in gpmc_calc_sync_write_timings()
1644 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); in gpmc_calc_sync_write_timings()
1646 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + in gpmc_calc_sync_write_timings()
1647 dev_t->t_wph); in gpmc_calc_sync_write_timings()
1650 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk); in gpmc_calc_sync_write_timings()
1651 temp += gpmc_t->wr_access; in gpmc_calc_sync_write_timings()
1653 if (dev_t->t_ce_rdyz) in gpmc_calc_sync_write_timings()
1655 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz); in gpmc_calc_sync_write_timings()
1656 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); in gpmc_calc_sync_write_timings()
1658 return 0; in gpmc_calc_sync_write_timings()
1668 temp = dev_t->t_avdp_r; in gpmc_calc_async_read_timings()
1670 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); in gpmc_calc_async_read_timings()
1671 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); in gpmc_calc_async_read_timings()
1674 temp = dev_t->t_oeasu; in gpmc_calc_async_read_timings()
1676 temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh); in gpmc_calc_async_read_timings()
1677 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); in gpmc_calc_async_read_timings()
1680 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ in gpmc_calc_async_read_timings()
1681 gpmc_t->oe_on + dev_t->t_oe); in gpmc_calc_async_read_timings()
1682 temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce); in gpmc_calc_async_read_timings()
1683 temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa); in gpmc_calc_async_read_timings()
1684 gpmc_t->access = gpmc_round_ps_to_ticks(temp); in gpmc_calc_async_read_timings()
1686 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); in gpmc_calc_async_read_timings()
1687 gpmc_t->cs_rd_off = gpmc_t->oe_off; in gpmc_calc_async_read_timings()
1690 temp = max_t(u32, dev_t->t_rd_cycle, in gpmc_calc_async_read_timings()
1691 gpmc_t->cs_rd_off + dev_t->t_cez_r); in gpmc_calc_async_read_timings()
1692 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez); in gpmc_calc_async_read_timings()
1693 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); in gpmc_calc_async_read_timings()
1695 return 0; in gpmc_calc_async_read_timings()
1705 temp = dev_t->t_avdp_w; in gpmc_calc_async_write_timings()
1707 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); in gpmc_calc_async_write_timings()
1708 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); in gpmc_calc_async_write_timings()
1711 temp = dev_t->t_weasu; in gpmc_calc_async_write_timings()
1713 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh); in gpmc_calc_async_write_timings()
1714 temp = max_t(u32, temp, gpmc_t->adv_wr_off + in gpmc_calc_async_write_timings()
1715 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); in gpmc_calc_async_write_timings()
1717 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); in gpmc_calc_async_write_timings()
1721 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); in gpmc_calc_async_write_timings()
1723 gpmc_t->we_on = gpmc_t->wr_data_mux_bus; in gpmc_calc_async_write_timings()
1726 temp = gpmc_t->we_on + dev_t->t_wpl; in gpmc_calc_async_write_timings()
1727 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); in gpmc_calc_async_write_timings()
1729 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + in gpmc_calc_async_write_timings()
1730 dev_t->t_wph); in gpmc_calc_async_write_timings()
1733 temp = max_t(u32, dev_t->t_wr_cycle, in gpmc_calc_async_write_timings()
1734 gpmc_t->cs_wr_off + dev_t->t_cez_w); in gpmc_calc_async_write_timings()
1735 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); in gpmc_calc_async_write_timings()
1737 return 0; in gpmc_calc_async_write_timings()
1745 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) * in gpmc_calc_sync_common_timings()
1748 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk( in gpmc_calc_sync_common_timings()
1749 dev_t->t_bacc, in gpmc_calc_sync_common_timings()
1750 gpmc_t->sync_clk); in gpmc_calc_sync_common_timings()
1752 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds); in gpmc_calc_sync_common_timings()
1753 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp); in gpmc_calc_sync_common_timings()
1755 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1) in gpmc_calc_sync_common_timings()
1756 return 0; in gpmc_calc_sync_common_timings()
1758 if (dev_t->ce_xdelay) in gpmc_calc_sync_common_timings()
1759 gpmc_t->bool_timings.cs_extra_delay = true; in gpmc_calc_sync_common_timings()
1760 if (dev_t->avd_xdelay) in gpmc_calc_sync_common_timings()
1761 gpmc_t->bool_timings.adv_extra_delay = true; in gpmc_calc_sync_common_timings()
1762 if (dev_t->oe_xdelay) in gpmc_calc_sync_common_timings()
1763 gpmc_t->bool_timings.oe_extra_delay = true; in gpmc_calc_sync_common_timings()
1764 if (dev_t->we_xdelay) in gpmc_calc_sync_common_timings()
1765 gpmc_t->bool_timings.we_extra_delay = true; in gpmc_calc_sync_common_timings()
1767 return 0; in gpmc_calc_sync_common_timings()
1777 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu); in gpmc_calc_common_timings()
1780 temp = dev_t->t_avdasu; in gpmc_calc_common_timings()
1781 if (dev_t->t_ce_avd) in gpmc_calc_common_timings()
1783 gpmc_t->cs_on + dev_t->t_ce_avd); in gpmc_calc_common_timings()
1784 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); in gpmc_calc_common_timings()
1789 return 0; in gpmc_calc_common_timings()
1799 t->cs_on /= 1000; in gpmc_convert_ps_to_ns()
1800 t->cs_rd_off /= 1000; in gpmc_convert_ps_to_ns()
1801 t->cs_wr_off /= 1000; in gpmc_convert_ps_to_ns()
1802 t->adv_on /= 1000; in gpmc_convert_ps_to_ns()
1803 t->adv_rd_off /= 1000; in gpmc_convert_ps_to_ns()
1804 t->adv_wr_off /= 1000; in gpmc_convert_ps_to_ns()
1805 t->we_on /= 1000; in gpmc_convert_ps_to_ns()
1806 t->we_off /= 1000; in gpmc_convert_ps_to_ns()
1807 t->oe_on /= 1000; in gpmc_convert_ps_to_ns()
1808 t->oe_off /= 1000; in gpmc_convert_ps_to_ns()
1809 t->page_burst_access /= 1000; in gpmc_convert_ps_to_ns()
1810 t->access /= 1000; in gpmc_convert_ps_to_ns()
1811 t->rd_cycle /= 1000; in gpmc_convert_ps_to_ns()
1812 t->wr_cycle /= 1000; in gpmc_convert_ps_to_ns()
1813 t->bus_turnaround /= 1000; in gpmc_convert_ps_to_ns()
1814 t->cycle2cycle_delay /= 1000; in gpmc_convert_ps_to_ns()
1815 t->wait_monitoring /= 1000; in gpmc_convert_ps_to_ns()
1816 t->clk_activation /= 1000; in gpmc_convert_ps_to_ns()
1817 t->wr_access /= 1000; in gpmc_convert_ps_to_ns()
1818 t->wr_data_mux_bus /= 1000; in gpmc_convert_ps_to_ns()
1828 mux = gpmc_s->mux_add_data ? true : false; in gpmc_calc_timings()
1829 sync = (gpmc_s->sync_read || gpmc_s->sync_write); in gpmc_calc_timings()
1832 memset(gpmc_t, 0, sizeof(*gpmc_t)); in gpmc_calc_timings()
1836 if (gpmc_s && gpmc_s->sync_read) in gpmc_calc_timings()
1841 if (gpmc_s && gpmc_s->sync_write) in gpmc_calc_timings()
1849 return 0; in gpmc_calc_timings()
1853 * gpmc_cs_program_settings - programs non-timing related settings
1854 * @cs: GPMC chip-select to program
1857 * Programs non-timing related settings for a GPMC chip-select, such as
1858 * bus-width, burst configuration, etc. Function should be called once
1859 * for each chip-select that is being used and must be called before
1861 * register will be initialised to zero by this function. Returns 0 on
1864 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) in gpmc_cs_program_settings() argument
1868 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { in gpmc_cs_program_settings()
1869 pr_err("%s: invalid width %d!", __func__, p->device_width); in gpmc_cs_program_settings()
1870 return -EINVAL; in gpmc_cs_program_settings()
1873 /* Address-data multiplexing not supported for NAND devices */ in gpmc_cs_program_settings()
1874 if (p->device_nand && p->mux_add_data) { in gpmc_cs_program_settings()
1876 return -EINVAL; in gpmc_cs_program_settings()
1879 if ((p->mux_add_data > GPMC_MUX_AD) || in gpmc_cs_program_settings()
1880 ((p->mux_add_data == GPMC_MUX_AAD) && in gpmc_cs_program_settings()
1883 return -EINVAL; in gpmc_cs_program_settings()
1887 if (p->burst_read || p->burst_write) { in gpmc_cs_program_settings()
1888 switch (p->burst_len) { in gpmc_cs_program_settings()
1894 pr_err("%s: invalid page/burst-length (%d)\n", in gpmc_cs_program_settings()
1895 __func__, p->burst_len); in gpmc_cs_program_settings()
1896 return -EINVAL; in gpmc_cs_program_settings()
1900 if (p->wait_pin != GPMC_WAITPIN_INVALID && in gpmc_cs_program_settings()
1901 p->wait_pin > gpmc_nr_waitpins) { in gpmc_cs_program_settings()
1902 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); in gpmc_cs_program_settings()
1903 return -EINVAL; in gpmc_cs_program_settings()
1906 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); in gpmc_cs_program_settings()
1908 if (p->sync_read) in gpmc_cs_program_settings()
1910 if (p->sync_write) in gpmc_cs_program_settings()
1912 if (p->wait_on_read) in gpmc_cs_program_settings()
1914 if (p->wait_on_write) in gpmc_cs_program_settings()
1916 if (p->wait_on_read || p->wait_on_write) in gpmc_cs_program_settings()
1917 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); in gpmc_cs_program_settings()
1918 if (p->device_nand) in gpmc_cs_program_settings()
1920 if (p->mux_add_data) in gpmc_cs_program_settings()
1921 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); in gpmc_cs_program_settings()
1922 if (p->burst_read) in gpmc_cs_program_settings()
1924 if (p->burst_write) in gpmc_cs_program_settings()
1926 if (p->burst_read || p->burst_write) { in gpmc_cs_program_settings()
1927 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); in gpmc_cs_program_settings()
1928 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; in gpmc_cs_program_settings()
1931 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); in gpmc_cs_program_settings()
1933 if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_INVALID) { in gpmc_cs_program_settings()
1936 if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_LOW) in gpmc_cs_program_settings()
1937 config1 &= ~GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin); in gpmc_cs_program_settings()
1938 else if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_HIGH) in gpmc_cs_program_settings()
1939 config1 |= GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin); in gpmc_cs_program_settings()
1944 return 0; in gpmc_cs_program_settings()
1948 static void gpmc_cs_set_name(int cs, const char *name) in gpmc_cs_set_name() argument
1950 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; in gpmc_cs_set_name()
1952 gpmc->name = name; in gpmc_cs_set_name()
1955 static const char *gpmc_cs_get_name(int cs) in gpmc_cs_get_name() argument
1957 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; in gpmc_cs_get_name()
1959 return gpmc->name; in gpmc_cs_get_name()
1963 * gpmc_cs_remap - remaps a chip-select physical base address
1964 * @cs: chip-select to remap
1965 * @base: physical base address to re-map chip-select to
1967 * Re-maps a chip-select to a new physical base address specified by
1968 * "base". Returns 0 on success and appropriate negative error code
1971 static int gpmc_cs_remap(int cs, u32 base) in gpmc_cs_remap() argument
1976 if (cs >= gpmc_cs_num) { in gpmc_cs_remap()
1977 pr_err("%s: requested chip-select is disabled\n", __func__); in gpmc_cs_remap()
1978 return -ENODEV; in gpmc_cs_remap()
1986 base &= ~(SZ_16M - 1); in gpmc_cs_remap()
1988 gpmc_cs_get_memconf(cs, &old_base, &size); in gpmc_cs_remap()
1990 return 0; in gpmc_cs_remap()
1992 ret = gpmc_cs_delete_mem(cs); in gpmc_cs_remap()
1993 if (ret < 0) in gpmc_cs_remap()
1996 ret = gpmc_cs_insert_mem(cs, base, size); in gpmc_cs_remap()
1997 if (ret < 0) in gpmc_cs_remap()
2000 ret = gpmc_cs_set_memconf(cs, base, size); in gpmc_cs_remap()
2006 * gpmc_read_settings_dt - read gpmc settings from device-tree
2007 * @np: pointer to device-tree node for a gpmc child device
2010 * Reads the GPMC settings for a GPMC child device from device-tree and
2017 memset(p, 0, sizeof(struct gpmc_settings)); in gpmc_read_settings_dt()
2019 p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); in gpmc_read_settings_dt()
2020 p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); in gpmc_read_settings_dt()
2021 of_property_read_u32(np, "gpmc,device-width", &p->device_width); in gpmc_read_settings_dt()
2022 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); in gpmc_read_settings_dt()
2024 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { in gpmc_read_settings_dt()
2025 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); in gpmc_read_settings_dt()
2026 p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); in gpmc_read_settings_dt()
2027 p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); in gpmc_read_settings_dt()
2028 if (!p->burst_read && !p->burst_write) in gpmc_read_settings_dt()
2029 pr_warn("%s: page/burst-length set but not used!\n", in gpmc_read_settings_dt()
2033 p->wait_pin = GPMC_WAITPIN_INVALID; in gpmc_read_settings_dt()
2034 p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID; in gpmc_read_settings_dt()
2036 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { in gpmc_read_settings_dt()
2037 if (!gpmc_is_valid_waitpin(p->wait_pin)) { in gpmc_read_settings_dt()
2038 pr_err("%s: Invalid wait-pin (%d)\n", __func__, p->wait_pin); in gpmc_read_settings_dt()
2039 p->wait_pin = GPMC_WAITPIN_INVALID; in gpmc_read_settings_dt()
2042 if (!of_property_read_u32(np, "ti,wait-pin-polarity", in gpmc_read_settings_dt()
2043 &p->wait_pin_polarity)) { in gpmc_read_settings_dt()
2044 if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_HIGH && in gpmc_read_settings_dt()
2045 p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_LOW) { in gpmc_read_settings_dt()
2046 pr_err("%s: Invalid wait-pin-polarity (%d)\n", in gpmc_read_settings_dt()
2047 __func__, p->wait_pin_polarity); in gpmc_read_settings_dt()
2048 p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID; in gpmc_read_settings_dt()
2052 p->wait_on_read = of_property_read_bool(np, in gpmc_read_settings_dt()
2053 "gpmc,wait-on-read"); in gpmc_read_settings_dt()
2054 p->wait_on_write = of_property_read_bool(np, in gpmc_read_settings_dt()
2055 "gpmc,wait-on-write"); in gpmc_read_settings_dt()
2056 if (!p->wait_on_read && !p->wait_on_write) in gpmc_read_settings_dt()
2070 memset(gpmc_t, 0, sizeof(*gpmc_t)); in gpmc_read_timings_dt()
2073 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); in gpmc_read_timings_dt()
2076 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); in gpmc_read_timings_dt()
2077 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); in gpmc_read_timings_dt()
2078 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); in gpmc_read_timings_dt()
2081 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); in gpmc_read_timings_dt()
2082 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); in gpmc_read_timings_dt()
2083 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); in gpmc_read_timings_dt()
2084 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns", in gpmc_read_timings_dt()
2085 &gpmc_t->adv_aad_mux_on); in gpmc_read_timings_dt()
2086 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns", in gpmc_read_timings_dt()
2087 &gpmc_t->adv_aad_mux_rd_off); in gpmc_read_timings_dt()
2088 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns", in gpmc_read_timings_dt()
2089 &gpmc_t->adv_aad_mux_wr_off); in gpmc_read_timings_dt()
2092 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); in gpmc_read_timings_dt()
2093 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); in gpmc_read_timings_dt()
2096 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); in gpmc_read_timings_dt()
2097 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); in gpmc_read_timings_dt()
2098 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns", in gpmc_read_timings_dt()
2099 &gpmc_t->oe_aad_mux_on); in gpmc_read_timings_dt()
2100 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns", in gpmc_read_timings_dt()
2101 &gpmc_t->oe_aad_mux_off); in gpmc_read_timings_dt()
2104 of_property_read_u32(np, "gpmc,page-burst-access-ns", in gpmc_read_timings_dt()
2105 &gpmc_t->page_burst_access); in gpmc_read_timings_dt()
2106 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); in gpmc_read_timings_dt()
2107 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); in gpmc_read_timings_dt()
2108 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); in gpmc_read_timings_dt()
2109 of_property_read_u32(np, "gpmc,bus-turnaround-ns", in gpmc_read_timings_dt()
2110 &gpmc_t->bus_turnaround); in gpmc_read_timings_dt()
2111 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", in gpmc_read_timings_dt()
2112 &gpmc_t->cycle2cycle_delay); in gpmc_read_timings_dt()
2113 of_property_read_u32(np, "gpmc,wait-monitoring-ns", in gpmc_read_timings_dt()
2114 &gpmc_t->wait_monitoring); in gpmc_read_timings_dt()
2115 of_property_read_u32(np, "gpmc,clk-activation-ns", in gpmc_read_timings_dt()
2116 &gpmc_t->clk_activation); in gpmc_read_timings_dt()
2119 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); in gpmc_read_timings_dt()
2120 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", in gpmc_read_timings_dt()
2121 &gpmc_t->wr_data_mux_bus); in gpmc_read_timings_dt()
2124 p = &gpmc_t->bool_timings; in gpmc_read_timings_dt()
2126 p->cycle2cyclediffcsen = in gpmc_read_timings_dt()
2127 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); in gpmc_read_timings_dt()
2128 p->cycle2cyclesamecsen = in gpmc_read_timings_dt()
2129 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); in gpmc_read_timings_dt()
2130 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); in gpmc_read_timings_dt()
2131 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); in gpmc_read_timings_dt()
2132 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); in gpmc_read_timings_dt()
2133 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); in gpmc_read_timings_dt()
2134 p->time_para_granularity = in gpmc_read_timings_dt()
2135 of_property_read_bool(np, "gpmc,time-para-granularity"); in gpmc_read_timings_dt()
2139 * gpmc_probe_generic_child - configures the gpmc for a child device
2141 * @child: pointer to device-tree node for child device
2143 * Allocates and configures a GPMC chip-select for a child device.
2144 * Returns 0 on success and appropriate negative error code on failure.
2154 int ret, cs; in gpmc_probe_generic_child() local
2158 if (of_property_read_u32(child, "reg", &cs) < 0) { in gpmc_probe_generic_child()
2159 dev_err(&pdev->dev, "%pOF has no 'reg' property\n", in gpmc_probe_generic_child()
2161 return -ENODEV; in gpmc_probe_generic_child()
2164 if (of_address_to_resource(child, 0, &res) < 0) { in gpmc_probe_generic_child()
2165 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n", in gpmc_probe_generic_child()
2167 return -ENODEV; in gpmc_probe_generic_child()
2175 name = gpmc_cs_get_name(cs); in gpmc_probe_generic_child()
2179 ret = gpmc_cs_request(cs, resource_size(&res), &base); in gpmc_probe_generic_child()
2180 if (ret < 0) { in gpmc_probe_generic_child()
2181 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); in gpmc_probe_generic_child()
2184 gpmc_cs_set_name(cs, child->full_name); in gpmc_probe_generic_child()
2195 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n", in gpmc_probe_generic_child()
2196 cs); in gpmc_probe_generic_child()
2197 gpmc_cs_show_timings(cs, in gpmc_probe_generic_child()
2202 /* CS must be disabled while making changes to gpmc configuration */ in gpmc_probe_generic_child()
2203 gpmc_cs_disable_mem(cs); in gpmc_probe_generic_child()
2206 * FIXME: gpmc_cs_request() will map the CS to an arbitrary in gpmc_probe_generic_child()
2208 * device-tree we want the NOR flash to be mapped to the in gpmc_probe_generic_child()
2209 * location specified in the device-tree blob. So remap the in gpmc_probe_generic_child()
2210 * CS to this location. Once DT migration is complete should in gpmc_probe_generic_child()
2213 ret = gpmc_cs_remap(cs, res.start); in gpmc_probe_generic_child()
2214 if (ret < 0) { in gpmc_probe_generic_child()
2215 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", in gpmc_probe_generic_child()
2216 cs, &res.start); in gpmc_probe_generic_child()
2218 dev_info(&pdev->dev, in gpmc_probe_generic_child()
2219 "GPMC CS %d start cannot be lesser than 0x%x\n", in gpmc_probe_generic_child()
2220 cs, GPMC_MEM_START); in gpmc_probe_generic_child()
2222 dev_info(&pdev->dev, in gpmc_probe_generic_child()
2223 "GPMC CS %d end cannot be greater than 0x%x\n", in gpmc_probe_generic_child()
2224 cs, GPMC_MEM_END); in gpmc_probe_generic_child()
2232 of_property_read_u32(child, "nand-bus-width", &val); in gpmc_probe_generic_child()
2241 dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n", in gpmc_probe_generic_child()
2243 ret = -EINVAL; in gpmc_probe_generic_child()
2248 gpmc_configure(GPMC_CONFIG_WP, 0); in gpmc_probe_generic_child()
2251 ret = of_property_read_u32(child, "bank-width", in gpmc_probe_generic_child()
2253 if (ret < 0 && !gpmc_s.device_width) { in gpmc_probe_generic_child()
2254 dev_err(&pdev->dev, in gpmc_probe_generic_child()
2255 "%pOF has no 'gpmc,device-width' property\n", in gpmc_probe_generic_child()
2264 if (ret < 0) in gpmc_probe_generic_child()
2268 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings"); in gpmc_probe_generic_child()
2270 ret = gpmc_cs_program_settings(cs, &gpmc_s); in gpmc_probe_generic_child()
2271 if (ret < 0) in gpmc_probe_generic_child()
2274 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); in gpmc_probe_generic_child()
2276 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n", in gpmc_probe_generic_child()
2281 /* Clear limited address i.e. enable A26-A11 */ in gpmc_probe_generic_child()
2286 /* Enable CS region */ in gpmc_probe_generic_child()
2287 gpmc_cs_enable_mem(cs); in gpmc_probe_generic_child()
2292 if (!of_platform_device_create(child, NULL, &pdev->dev)) in gpmc_probe_generic_child()
2296 if (of_platform_default_populate(child, NULL, &pdev->dev)) in gpmc_probe_generic_child()
2299 return 0; in gpmc_probe_generic_child()
2303 dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child); in gpmc_probe_generic_child()
2304 ret = -ENODEV; in gpmc_probe_generic_child()
2309 gpmc_cs_free(cs); in gpmc_probe_generic_child()
2320 of_match_device(gpmc_dt_ids, &pdev->dev); in gpmc_probe_dt()
2323 return 0; in gpmc_probe_dt()
2325 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", in gpmc_probe_dt()
2327 if (ret < 0) { in gpmc_probe_dt()
2328 pr_err("%s: number of chip-selects not defined\n", __func__); in gpmc_probe_dt()
2331 pr_err("%s: all chip-selects are disabled\n", __func__); in gpmc_probe_dt()
2332 return -EINVAL; in gpmc_probe_dt()
2334 pr_err("%s: number of supported chip-selects cannot be > %d\n", in gpmc_probe_dt()
2336 return -EINVAL; in gpmc_probe_dt()
2339 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", in gpmc_probe_dt()
2341 if (ret < 0) { in gpmc_probe_dt()
2346 return 0; in gpmc_probe_dt()
2354 for_each_available_child_of_node(pdev->dev.of_node, child) { in gpmc_probe_dt_children()
2357 dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n", in gpmc_probe_dt_children()
2365 memset(p, 0, sizeof(*p)); in gpmc_read_settings_dt()
2369 return 0; in gpmc_probe_dt()
2385 return 0; /* we're input only */ in gpmc_gpio_direction_input()
2391 return -EINVAL; /* we're input only */ in gpmc_gpio_direction_output()
2414 gpmc->gpio_chip.parent = gpmc->dev; in gpmc_gpio_init()
2415 gpmc->gpio_chip.owner = THIS_MODULE; in gpmc_gpio_init()
2416 gpmc->gpio_chip.label = DEVICE_NAME; in gpmc_gpio_init()
2417 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins; in gpmc_gpio_init()
2418 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction; in gpmc_gpio_init()
2419 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input; in gpmc_gpio_init()
2420 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output; in gpmc_gpio_init()
2421 gpmc->gpio_chip.set = gpmc_gpio_set; in gpmc_gpio_init()
2422 gpmc->gpio_chip.get = gpmc_gpio_get; in gpmc_gpio_init()
2423 gpmc->gpio_chip.base = -1; in gpmc_gpio_init()
2425 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL); in gpmc_gpio_init()
2426 if (ret < 0) { in gpmc_gpio_init()
2427 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret); in gpmc_gpio_init()
2431 return 0; in gpmc_gpio_init()
2442 gpmc_context = &gpmc->context; in omap3_gpmc_save_context()
2444 gpmc_context->sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); in omap3_gpmc_save_context()
2445 gpmc_context->irqenable = gpmc_read_reg(GPMC_IRQENABLE); in omap3_gpmc_save_context()
2446 gpmc_context->timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); in omap3_gpmc_save_context()
2447 gpmc_context->config = gpmc_read_reg(GPMC_CONFIG); in omap3_gpmc_save_context()
2448 gpmc_context->prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); in omap3_gpmc_save_context()
2449 gpmc_context->prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); in omap3_gpmc_save_context()
2450 gpmc_context->prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); in omap3_gpmc_save_context()
2451 for (i = 0; i < gpmc_cs_num; i++) { in omap3_gpmc_save_context()
2452 gpmc_context->cs_context[i].is_valid = gpmc_cs_mem_enabled(i); in omap3_gpmc_save_context()
2453 if (gpmc_context->cs_context[i].is_valid) { in omap3_gpmc_save_context()
2454 gpmc_context->cs_context[i].config1 = in omap3_gpmc_save_context()
2456 gpmc_context->cs_context[i].config2 = in omap3_gpmc_save_context()
2458 gpmc_context->cs_context[i].config3 = in omap3_gpmc_save_context()
2460 gpmc_context->cs_context[i].config4 = in omap3_gpmc_save_context()
2462 gpmc_context->cs_context[i].config5 = in omap3_gpmc_save_context()
2464 gpmc_context->cs_context[i].config6 = in omap3_gpmc_save_context()
2466 gpmc_context->cs_context[i].config7 = in omap3_gpmc_save_context()
2480 gpmc_context = &gpmc->context; in omap3_gpmc_restore_context()
2482 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context->sysconfig); in omap3_gpmc_restore_context()
2483 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context->irqenable); in omap3_gpmc_restore_context()
2484 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context->timeout_ctrl); in omap3_gpmc_restore_context()
2485 gpmc_write_reg(GPMC_CONFIG, gpmc_context->config); in omap3_gpmc_restore_context()
2486 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context->prefetch_config1); in omap3_gpmc_restore_context()
2487 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context->prefetch_config2); in omap3_gpmc_restore_context()
2488 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context->prefetch_control); in omap3_gpmc_restore_context()
2489 for (i = 0; i < gpmc_cs_num; i++) { in omap3_gpmc_restore_context()
2490 if (gpmc_context->cs_context[i].is_valid) { in omap3_gpmc_restore_context()
2492 gpmc_context->cs_context[i].config1); in omap3_gpmc_restore_context()
2494 gpmc_context->cs_context[i].config2); in omap3_gpmc_restore_context()
2496 gpmc_context->cs_context[i].config3); in omap3_gpmc_restore_context()
2498 gpmc_context->cs_context[i].config4); in omap3_gpmc_restore_context()
2500 gpmc_context->cs_context[i].config5); in omap3_gpmc_restore_context()
2502 gpmc_context->cs_context[i].config6); in omap3_gpmc_restore_context()
2504 gpmc_context->cs_context[i].config7); in omap3_gpmc_restore_context()
2506 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 0); in omap3_gpmc_restore_context()
2517 if (gpmc->is_suspended || pm_runtime_suspended(gpmc->dev)) in omap_gpmc_context_notifier()
2541 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL); in gpmc_probe()
2543 return -ENOMEM; in gpmc_probe()
2545 gpmc->dev = &pdev->dev; in gpmc_probe()
2551 gpmc_base = devm_platform_ioremap_resource(pdev, 0); in gpmc_probe()
2555 gpmc_base = devm_ioremap_resource(&pdev->dev, res); in gpmc_probe()
2561 dev_err(&pdev->dev, "couldn't get data reg resource\n"); in gpmc_probe()
2562 return -ENOENT; in gpmc_probe()
2565 gpmc->data = res; in gpmc_probe()
2568 gpmc->irq = platform_get_irq(pdev, 0); in gpmc_probe()
2569 if (gpmc->irq < 0) in gpmc_probe()
2570 return gpmc->irq; in gpmc_probe()
2572 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck"); in gpmc_probe()
2574 dev_err(&pdev->dev, "Failed to get GPMC fck\n"); in gpmc_probe()
2579 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n"); in gpmc_probe()
2580 return -EINVAL; in gpmc_probe()
2583 if (pdev->dev.of_node) { in gpmc_probe()
2592 gpmc->waitpins = devm_kzalloc(&pdev->dev, in gpmc_probe()
2595 if (!gpmc->waitpins) in gpmc_probe()
2596 return -ENOMEM; in gpmc_probe()
2598 for (i = 0; i < gpmc_nr_waitpins; i++) in gpmc_probe()
2599 gpmc->waitpins[i].pin = GPMC_WAITPIN_INVALID; in gpmc_probe()
2601 pm_runtime_enable(&pdev->dev); in gpmc_probe()
2602 pm_runtime_get_sync(&pdev->dev); in gpmc_probe()
2607 * FIXME: Once device-tree migration is complete the below flags in gpmc_probe()
2608 * should be populated based upon the device-tree compatible in gpmc_probe()
2611 * devices support the addr-addr-data multiplex protocol. in gpmc_probe()
2614 * - OMAP24xx = 2.0 in gpmc_probe()
2615 * - OMAP3xxx = 5.0 in gpmc_probe()
2616 * - OMAP44xx/54xx/AM335x = 6.0 in gpmc_probe()
2618 if (GPMC_REVISION_MAJOR(l) > 0x4) in gpmc_probe()
2620 if (GPMC_REVISION_MAJOR(l) > 0x5) in gpmc_probe()
2622 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), in gpmc_probe()
2630 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins; in gpmc_probe()
2633 dev_err(gpmc->dev, "gpmc_setup_irq failed\n"); in gpmc_probe()
2639 gpmc->nb.notifier_call = omap_gpmc_context_notifier; in gpmc_probe()
2640 cpu_pm_register_notifier(&gpmc->nb); in gpmc_probe()
2642 return 0; in gpmc_probe()
2646 pm_runtime_put_sync(&pdev->dev); in gpmc_probe()
2647 pm_runtime_disable(&pdev->dev); in gpmc_probe()
2657 cpu_pm_unregister_notifier(&gpmc->nb); in gpmc_remove()
2658 for (i = 0; i < gpmc_nr_waitpins; i++) in gpmc_remove()
2662 pm_runtime_put_sync(&pdev->dev); in gpmc_remove()
2663 pm_runtime_disable(&pdev->dev); in gpmc_remove()
2673 gpmc->is_suspended = 1; in gpmc_suspend()
2675 return 0; in gpmc_suspend()
2684 gpmc->is_suspended = 0; in gpmc_resume()
2686 return 0; in gpmc_resume()
2694 { .compatible = "ti,omap2420-gpmc" },
2695 { .compatible = "ti,omap2430-gpmc" },
2696 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
2697 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
2698 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
2699 { .compatible = "ti,am64-gpmc" },