Lines Matching +full:4 +full:x12

45 #define SMI_LARB_THRT_RD_NU_LMT_MSK	GENMASK(7, 4)
46 #define SMI_LARB_THRT_RD_NU_LMT		(5 << 4)
64  * every port have 4 bit to control, bit[port + 3] control virtual or physical,
81 #define SMI_LARB_NONSEC_CON(id)		(0x380 + ((id) * 4))
288 	[1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
289 	[2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},
290 	[3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
291 	[4] = {0x06, 0x01, 0x17, 0x06, 0x0a, 0x07, 0x07,},
294 	[7] = {0x0c, 0x0c, 0x12,},
319 	[17] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
320 		0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
321 	[18] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
322 		0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
331 	[24] = {0x12, 0x06, 0x12, 0x06,},
338 	[2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},      /* ... */
339 	[3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
340 	[4] = {0x06, 0x01, 0x17, 0x06, 0x0a,},
343 	[7] = {0x0c, 0x0c, 0x12,},
344 	[8] = {0x0c, 0x0c, 0x12,},
347 	[10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10,
352 	[13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,},
353 	[14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01,
356 	[16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
357 		0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,},
359 	[18] = {0x12, 0x06, 0x12, 0x06,},
371 	[25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
373 	[26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
375 	[27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
396 		BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
654 	.bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
674 	.bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7),
718 	.bus_sel  = F_MMU1_LARB(2) | F_MMU1_LARB(4),