24 #define SMI_L1LEN			0x100
26 #define SMI_L1_ARB			0x200
27 #define SMI_BUS_SEL			0x220
30 #define F_MMU1_LARB(larbid)		(0x1 << SMI_BUS_LARB_SHIFT(larbid))
32 #define SMI_READ_FIFO_TH		0x230
33 #define SMI_M4U_TH			0x234
34 #define SMI_FIFO_TH1			0x238
35 #define SMI_FIFO_TH2			0x23c
36 #define SMI_DCM				0x300
37 #define SMI_DUMMY			0x444
40 #define SMI_LARB_SLP_CON                0xc
41 #define SLP_PROT_EN                     BIT(0)
44 #define SMI_LARB_CMD_THRT_CON		0x24
48 #define SMI_LARB_SW_FLAG		0x40
49 #define SMI_LARB_SW_FLAG_1		0x1
51 #define SMI_LARB_OSTDL_PORT		0x200
52 #define SMI_LARB_OSTDL_PORTx(id)	(SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2))
56 #define REG_SMI_SECUR_CON_BASE		0x5c0
58 /* every register control 8 port, register offset 0x4 */
68 #define SMI_SECUR_CON_VAL_MSK(id)	(~(0xf << (((id) & 0x7) << 2)))
69 #define SMI_SECUR_CON_VAL_VIRT(id)	BIT((((id) & 0x7) << 2) + 3)
71 #define SMI_SECUR_CON_VAL_DOMAIN(id)	(0x3 << ((((id) & 0x7) << 2) + 1))
75 #define MT8167_SMI_LARB_MMU_EN		0xfc0
78 #define MT8173_SMI_LARB_MMU_EN		0xf00
81 #define SMI_LARB_NONSEC_CON(id)		(0x380 + ((id) * 4))
82 #define F_MMU_EN			BIT(0)
84 	u32 _id = (id) & 0x3;				\
91 #define MTK_SMI_FLAG_THRT_UPDATE	BIT(0)
169 	for (i = 0; i < MTK_LARB_NR_MAX; i++) {  in mtk_smi_larb_bind()
174 			return 0;  in mtk_smi_larb_bind()
203 	for (i = 0; i < larb_port_num; i++, m4u_port_id++) {  in mtk_smi_larb_config_port_gen1()
220 	return 0;  in mtk_smi_larb_config_port_gen1()
228 	return 0;  in mtk_smi_larb_config_port_mt8167()
236 	return 0;  in mtk_smi_larb_config_port_mt8173()
248 		return 0;  in mtk_smi_larb_config_port_gen2_general()
260 	for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++)  in mtk_smi_larb_config_port_gen2_general()
270 			      larb->larbid, *larb->mmu, 0, 0, 0, 0, &res);  in mtk_smi_larb_config_port_gen2_general()
271 		if (res.a0 != 0) {  in mtk_smi_larb_config_port_gen2_general()
283 	return 0;  in mtk_smi_larb_config_port_gen2_general()
287 	[0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
288 	[1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
289 	[2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},
290 	[3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
291 	[4] = {0x06, 0x01, 0x17, 0x06, 0x0a, 0x07, 0x07,},
292 	[5] = {0x02, 0x01, 0x04, 0x02, 0x06, 0x01, 0x06, 0x0a,},
293 	[6] = {0x06, 0x01, 0x06, 0x0a,},
294 	[7] = {0x0c, 0x0c, 0x12,},
295 	[8] = {0x0c, 0x01, 0x0a, 0x05, 0x02, 0x03, 0x01, 0x01, 0x14, 0x14,
296 	       0x0a, 0x14, 0x1e, 0x01, 0x0c, 0x0a, 0x05, 0x02, 0x02, 0x05,
297 	       0x03, 0x01, 0x1e, 0x01, 0x05,},
298 	[9] = {0x1e, 0x01, 0x0a, 0x0a, 0x01, 0x01, 0x03, 0x1e, 0x1e, 0x10,
299 	       0x07, 0x01, 0x0a, 0x06, 0x03, 0x03, 0x0e, 0x01, 0x04, 0x28,},
300 	[10] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
301 		0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
302 		0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
303 	[11] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
304 		0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
305 		0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
306 	[12] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
307 		0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
308 		0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
309 	[13] = {0x07, 0x02, 0x04, 0x02, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
310 		0x07, 0x02, 0x04, 0x02, 0x05, 0x05,},
311 	[14] = {0x02, 0x02, 0x0c, 0x0c, 0x0c, 0x0c, 0x01, 0x01, 0x02, 0x02,
312 		0x02, 0x02, 0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
313 		0x02, 0x02, 0x01, 0x01,},
314 	[15] = {0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x0c, 0x0c,
315 		0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02,
316 		0x0c, 0x01, 0x01,},
317 	[16] = {0x28, 0x28, 0x03, 0x01, 0x01, 0x03, 0x14, 0x14, 0x0a, 0x0d,
318 		0x03, 0x05, 0x0e, 0x01, 0x01, 0x05, 0x06, 0x0d, 0x01,},
319 	[17] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
320 		0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
321 	[18] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
322 		0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
323 	[19] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
324 	[20] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
325 	[21] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
326 		0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
327 		0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
328 	[22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,
329 		0x01,},
330 	[23] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x18, 0x01, 0x01,},
331 	[24] = {0x12, 0x06, 0x12, 0x06,},
332 	[25] = {0x01},
336 	[0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */
337 	[1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */
338 	[2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},      /* ... */
339 	[3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
340 	[4] = {0x06, 0x01, 0x17, 0x06, 0x0a,},
341 	[5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,},
342 	[6] = {0x06, 0x01, 0x06, 0x0a,},
343 	[7] = {0x0c, 0x0c, 0x12,},
344 	[8] = {0x0c, 0x0c, 0x12,},
345 	[9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a,
346 		0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,},
347 	[10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10,
348 		0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d,
349 		0x0d, 0x06, 0x10, 0x10,},
350 	[11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,},
351 	[12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,},
352 	[13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,},
353 	[14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01,
354 		0x01, 0x02, 0x02, 0x08, 0x02,},
356 	[16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
357 		0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,},
358 	[17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
359 	[18] = {0x12, 0x06, 0x12, 0x06,},
360 	[19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
361 		0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
362 		0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
363 	[20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
364 		0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
365 		0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
366 	[21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
367 	[22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
368 	[23] = {0x18, 0x01,},
369 	[24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01,
370 		0x01, 0x01,},
371 	[25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
372 		0x02, 0x01,},
373 	[26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
374 		0x02, 0x01,},
375 	[27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
376 		0x02, 0x01,},
377 	[28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
465 		dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp);  in mtk_smi_larb_sleep_ctrl_enable()
472 	writel_relaxed(0, larb->base + SMI_LARB_SLP_CON);  in mtk_smi_larb_sleep_ctrl_disable()
482 	smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);  in mtk_smi_device_link_common()
507 	return 0;  in mtk_smi_device_link_common()
517 	for (i = 0; i < clk_nr_required; i++)  in mtk_smi_dts_clk_init()
542 	larb->base = devm_platform_ioremap_resource(pdev, 0);  in mtk_smi_larb_probe()
554 	if (ret < 0)  in mtk_smi_larb_probe()
562 	return 0;  in mtk_smi_larb_probe()
608 	return 0;  in mtk_smi_larb_suspend()
628 	{SMI_L1_ARB, 0x1b},
629 	{SMI_M4U_TH, 0xce810c85},
630 	{SMI_FIFO_TH1, 0x43214c8},
631 	{SMI_READ_FIFO_TH, 0x191f},
635 	{SMI_L1LEN, 0xb},
636 	{SMI_M4U_TH, 0xe100e10},
637 	{SMI_FIFO_TH1, 0x506090a},
638 	{SMI_FIFO_TH2, 0x506090a},
639 	{SMI_DCM, 0x4f1},
640 	{SMI_DUMMY, 0x1},
660 	.bus_sel  = F_MMU1_LARB(0),
759 	ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0);  in mtk_smi_common_probe()
770 		common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0);  in mtk_smi_common_probe()
778 		common->base = devm_platform_ioremap_resource(pdev, 0);  in mtk_smi_common_probe()
786 		if (ret < 0)  in mtk_smi_common_probe()
792 	return 0;  in mtk_smi_common_probe()
808 	u32 bus_sel = common->plat->bus_sel; /* default is 0 */  in mtk_smi_common_resume()
816 		return 0;  in mtk_smi_common_resume()
818 	for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++)  in mtk_smi_common_resume()
822 	return 0;  in mtk_smi_common_resume()
830 	return 0;  in mtk_smi_common_suspend()