63 /* DRAM MR4 Offsets & Masks */
742 	u32 mr4;  in show_refresh()  local
754 	mr4 = (readl_relaxed(info + DRAM_INFO_MR4) >> DRAM_INFO_MR4_SHIFT) &  in show_refresh()
757 	refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK;  in show_refresh()
758 	sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK;  in show_refresh()
759 	ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK;  in show_refresh()
760 	thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK;  in show_refresh()
761 	tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK;  in show_refresh()
832 	u32 mr4, mr5, mr6, mr7, mr8, err;  in show_dram()  local
839 	mr4 = response[MSG_ARG0 + 0] & DRAM_INFO_MR4_MASK;  in show_dram()
846 	return sprintf(buf, "%#x %#x %#x %#x %#x %#x\n", mr4, mr5, mr6, mr7,  in show_dram()