47 #define IR_DEC_REG1				0x1c  macro
226 		regmap_read(ir->reg, IR_DEC_REG1, &duration);  in meson_ir_irq()
273 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);  in meson_ir_hw_decoder_init()
274 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,  in meson_ir_hw_decoder_init()
290 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_HOLD_CODE,  in meson_ir_hw_decoder_init()
329 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_FRAME_LEN, regval);  in meson_ir_hw_decoder_init()
393 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,  in meson_ir_hw_decoder_init()
395 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);  in meson_ir_hw_decoder_init()
396 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,  in meson_ir_hw_decoder_init()
414 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,  in meson_ir_sw_decoder_init()
416 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);  in meson_ir_sw_decoder_init()
420 		regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,  in meson_ir_sw_decoder_init()
433 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,  in meson_ir_sw_decoder_init()
436 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,  in meson_ir_sw_decoder_init()
538 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);  in meson_ir_remove()
556 		regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,  in meson_ir_shutdown()
588 	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);  in meson_ir_suspend()
598 	.max_register = IR_DEC_REG1,