Lines Matching +full:byte +full:- +full:order
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
34 /* hw-specific operation function pointers; most of these must be
62 /* put a byte to the TX FIFO */
98 /* duty cycle, 0-100 */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
130 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
135 * frequency A = (H - L) / (H + L). We can use this in order to honor the
136 * s_rx_carrier_range() call in ir-core. We'll suppose that any request
170 * Environment Control - Low Pin Count Input / Output
171 * (EC - LPC I/O)
183 #define IT87_BDLR 0x05 /* baud rate divisor low byte register */
184 #define IT87_BDHR 0x06 /* baud rate divisor high byte register */
202 #define IT87_HCFS 0x40 /* high-speed carrier frequency select */
212 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
213 * 0x30 -> 25 */
224 #define IT87_TXFBC 0x3f /* transmitter FIFO byte count mask */
227 #define IT87_RXFBC 0x3f /* receiver FIFO byte count mask */
228 #define IT87_RXFTO 0x80 /* receiver FIFO time-out */
248 * they only are accessible to the integrated microcontroller. Thus, in order
250 * the controller firmware in use, we are going to use the PNP ID in order to
265 #define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */
266 #define IT85_C0BDHR 0x09 /* baud rate divisor high byte register */
280 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
281 * 0x0c -> 25 */
329 #define IT85_RXFTO 0x80 /* receiver FIFO time-out */
349 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
350 * selectable by a single bank-select bit that's mapped onto both banks. The
351 * IT8512 registers are mapped in a different order, so that the first bank
353 * reserved high-order bit are placed at the same offset in both banks in
354 * order to reuse the reserved bit as the bank select bit.
374 #define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */
375 #define IT8708_C0BDHR 0x02 /* baud rate divisor high byte register */
408 * a specific firmware running on the IT8512's embedded micro-controller.
409 * In addition of the embedded micro-controller, the IT8512 chip contains a
412 * micro-controller. The CIR module is only accessible by the
413 * micro-controller.
415 * The battery-backed SRAM module is accessible by the host CPU and the
416 * micro-controller. So one of the MC's firmware role is to act as a bridge
420 * communication protocol is not, so it was reverse-engineered.
425 #define IT8709_RAM_VAL 0x01 /* read/write data to the indexed byte */
430 #define IT8709_MODE 0x1a /* request/ack byte */