Lines Matching full:pipe
34 static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
37 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
65 struct vsp1_pipeline *pipe,
117 struct vsp1_pipeline *pipe,
191 ret = vsp1_du_insert_uif(vsp1, pipe, uif, &rpf->entity, RWPF_PAD_SOURCE,
192 pipe->brx, brx_input);
199 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL,
206 format.format.code, BRX_NAME(pipe->brx), format.pad);
212 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_selection, NULL,
219 BRX_NAME(pipe->brx), sel.pad);
226 struct vsp1_pipeline *pipe);
227 static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe);
230 struct vsp1_pipeline *pipe)
232 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
245 if (pipe->num_inputs > 2)
247 else if (pipe->brx && !drm_pipe->force_brx_release)
248 brx = pipe->brx;
249 else if (vsp1_feature(vsp1, VSP1_HAS_BRU) && !vsp1->bru->entity.pipe)
255 if (brx != pipe->brx) {
259 if (pipe->brx) {
260 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
261 __func__, pipe->lif->index,
262 BRX_NAME(pipe->brx));
278 released_brx = pipe->brx;
280 list_del(&pipe->brx->list_pipe);
281 pipe->brx->sink = NULL;
282 pipe->brx->pipe = NULL;
283 pipe->brx = NULL;
290 if (brx->pipe) {
293 dev_dbg(vsp1->dev, "%s: pipe %u: waiting for %s\n",
294 __func__, pipe->lif->index, BRX_NAME(brx));
296 owner_pipe = to_vsp1_drm_pipeline(brx->pipe);
299 vsp1_du_pipeline_setup_inputs(vsp1, &owner_pipe->pipe);
300 vsp1_du_pipeline_configure(&owner_pipe->pipe);
308 owner_pipe->pipe.lif->index);
314 * the pipe pointer NULL) to let vsp1_du_pipeline_configure()
317 if (released_brx && !released_brx->pipe)
319 &pipe->entities);
325 dev_dbg(vsp1->dev, "%s: pipe %u: acquired %s\n",
326 __func__, pipe->lif->index, BRX_NAME(brx));
328 pipe->brx = brx;
329 pipe->brx->pipe = pipe;
330 pipe->brx->sink = &pipe->output->entity;
331 pipe->brx->sink_pad = 0;
333 list_add_tail(&pipe->brx->list_pipe,
334 &pipe->output->entity.list_pipe);
373 struct vsp1_pipeline *pipe)
375 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
384 pipe->num_inputs = 0;
390 if (!pipe->inputs[i])
394 for (j = pipe->num_inputs++; j > 0; --j) {
408 ret = vsp1_du_pipeline_setup_brx(vsp1, pipe);
411 BRX_NAME(pipe->brx));
415 brx = to_brx(&pipe->brx->subdev);
418 for (i = 0; i < pipe->brx->source_pad; ++i) {
426 if (!rpf->entity.pipe) {
427 rpf->entity.pipe = pipe;
428 list_add(&rpf->entity.list_pipe, &pipe->entities);
433 rpf->entity.sink = pipe->brx;
437 __func__, rpf->entity.index, BRX_NAME(pipe->brx), i);
443 ret = vsp1_du_pipeline_setup_rpf(vsp1, pipe, rpf, uif, i);
456 ret = vsp1_du_insert_uif(vsp1, pipe, uif,
457 pipe->brx, pipe->brx->source_pad,
458 &pipe->output->entity, 0);
461 __func__, BRX_NAME(pipe->brx));
463 /* If the DRM pipe does not have a UIF there is nothing we can update. */
468 * If the UIF is not in use schedule it for removal by setting its pipe
475 drm_pipe->uif->pipe = NULL;
476 } else if (!drm_pipe->uif->pipe) {
477 drm_pipe->uif->pipe = pipe;
478 list_add_tail(&drm_pipe->uif->list_pipe, &pipe->entities);
486 struct vsp1_pipeline *pipe)
488 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
500 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
507 format.format.code, pipe->output->entity.index);
510 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL,
517 format.format.code, pipe->output->entity.index);
520 ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL,
527 format.format.code, pipe->lif->index);
537 pipe->lif->index);
545 static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
547 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
554 vsp1_pipeline_calculate_partition(pipe, &pipe->part_table[0],
559 if (pipe->output->writeback)
562 dl = vsp1_dl_list_get(pipe->output->dlm);
565 list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
567 if (!entity->pipe) {
577 vsp1_entity_route_setup(entity, pipe, dlb);
578 vsp1_entity_configure_stream(entity, entity->state, pipe,
580 vsp1_entity_configure_frame(entity, pipe, dl, dlb);
581 vsp1_entity_configure_partition(entity, pipe,
582 &pipe->part_table[0], dl, dlb);
659 struct vsp1_pipeline *pipe;
667 drm_pipe = &vsp1->drm->pipe[pipe_index];
668 pipe = &drm_pipe->pipe;
675 brx = to_brx(&pipe->brx->subdev);
681 ret = vsp1_pipeline_stop(pipe);
685 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
686 struct vsp1_rwpf *rpf = pipe->inputs[i];
692 * Remove the RPF from the pipe and the list of BRx
695 WARN_ON(!rpf->entity.pipe);
696 rpf->entity.pipe = NULL;
698 pipe->inputs[i] = NULL;
704 pipe->num_inputs = 0;
706 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
707 __func__, pipe->lif->index,
708 BRX_NAME(pipe->brx));
710 list_del(&pipe->brx->list_pipe);
711 pipe->brx->pipe = NULL;
712 pipe->brx = NULL;
716 vsp1_dlm_reset(pipe->output->dlm);
725 pipe->underrun_count = 0;
729 pipe->interlaced = cfg->interlaced;
733 pipe->interlaced ? "i" : "");
738 ret = vsp1_du_pipeline_setup_inputs(vsp1, pipe);
742 ret = vsp1_du_pipeline_setup_output(vsp1, pipe);
746 vsp1_pipeline_dump(pipe, "LIF setup");
765 vsp1_du_pipeline_configure(pipe);
774 spin_lock_irqsave(&pipe->irqlock, flags);
775 vsp1_pipeline_run(pipe);
776 spin_unlock_irqrestore(&pipe->irqlock, flags);
829 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
849 rpf->entity.pipe = NULL;
850 drm_pipe->pipe.inputs[rpf_index] = NULL;
885 drm_pipe->pipe.inputs[rpf_index] = rpf;
895 * @cfg: atomic pipe configuration
901 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
902 struct vsp1_pipeline *pipe = &drm_pipe->pipe;
912 ret = vsp1_du_pipeline_set_rwpf_format(vsp1, pipe->output,
918 pipe->output->mem.addr[0] = wb_cfg->mem[0];
919 pipe->output->mem.addr[1] = wb_cfg->mem[1];
920 pipe->output->mem.addr[2] = wb_cfg->mem[2];
921 pipe->output->writeback = true;
924 vsp1_du_pipeline_setup_inputs(vsp1, pipe);
926 vsp1_pipeline_dump(pipe, "atomic update");
928 vsp1_du_pipeline_configure(pipe);
974 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i];
975 struct vsp1_pipeline *pipe = &drm_pipe->pipe;
979 vsp1_pipeline_init(pipe);
981 pipe->partitions = 1;
982 pipe->part_table = &drm_pipe->partition;
984 pipe->frame_end = vsp1_du_pipeline_frame_end;
990 pipe->output = vsp1->wpf[i];
991 pipe->lif = &vsp1->lif[i]->entity;
993 pipe->output->entity.pipe = pipe;
994 pipe->output->entity.sink = pipe->lif;
995 pipe->output->entity.sink_pad = 0;
996 list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities);
998 pipe->lif->pipe = pipe;
999 list_add_tail(&pipe->lif->list_pipe, &pipe->entities);