Lines Matching +full:output +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
3 * camss-vfe-4-1.c
5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.1
7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2015-2018 Linaro Ltd.
16 #include "camss-vfe.h"
17 #include "camss-vfe-gen1.h"
215 u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); in vfe_hw_version()
217 dev_dbg(vfe->camss->dev, "VFE HW Version = 0x%08x\n", hw_version); in vfe_hw_version()
232 u32 bits = readl_relaxed(vfe->base + reg); in vfe_reg_clr()
234 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
239 u32 bits = readl_relaxed(vfe->base + reg); in vfe_reg_set()
241 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
256 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); in vfe_global_reset()
262 vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_request()
267 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_clear()
270 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_enable() argument
272 if (enable) in vfe_wm_enable()
280 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_frame_based() argument
282 if (enable) in vfe_wm_frame_based()
293 *width = pix->width; in vfe_get_wm_sizes()
294 *height = pix->height; in vfe_get_wm_sizes()
295 *bytesperline = pix->plane_fmt[0].bytesperline; in vfe_get_wm_sizes()
297 if (pix->pixelformat == V4L2_PIX_FMT_NV12 || in vfe_get_wm_sizes()
298 pix->pixelformat == V4L2_PIX_FMT_NV21) in vfe_get_wm_sizes()
305 u8 plane, u32 enable) in vfe_wm_line_based() argument
309 if (enable) { in vfe_wm_line_based()
314 wpl = vfe_word_per_line(pix->pixelformat, width); in vfe_wm_line_based()
316 reg = height - 1; in vfe_wm_line_based()
317 reg |= ((wpl + 1) / 2 - 1) << 16; in vfe_wm_line_based()
319 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
322 wpl = vfe_word_per_line(pix->pixelformat, bytesperline); in vfe_wm_line_based()
325 reg |= (height - 1) << 4; in vfe_wm_line_based()
328 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
331 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
333 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
342 reg = readl_relaxed(vfe->base + in vfe_wm_set_framedrop_period()
351 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); in vfe_wm_set_framedrop_period()
358 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); in vfe_wm_set_framedrop_pattern()
368 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); in vfe_wm_set_ub_cfg()
374 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); in vfe_bus_reload_wm()
381 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); in vfe_wm_set_ping_addr()
387 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); in vfe_wm_set_pong_addr()
394 reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); in vfe_wm_get_ping_pong_status()
399 static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) in vfe_bus_enable_wr_if() argument
401 if (enable) in vfe_bus_enable_wr_if()
402 writel_relaxed(0x10000009, vfe->base + VFE_0_BUS_CFG); in vfe_bus_enable_wr_if()
404 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); in vfe_bus_enable_wr_if()
446 vfe->base + in vfe_wm_set_subsample()
483 static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, in vfe_set_xbar_cfg() argument
484 u8 enable) in vfe_set_xbar_cfg() argument
486 struct vfe_line *line = container_of(output, struct vfe_line, output); in vfe_set_xbar_cfg()
487 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_xbar_cfg()
491 for (i = 0; i < output->wm_num; i++) { in vfe_set_xbar_cfg()
500 /* On current devices output->wm_num is always <= 2 */ in vfe_set_xbar_cfg()
504 if (output->wm_idx[i] % 2 == 1) in vfe_set_xbar_cfg()
507 if (enable) in vfe_set_xbar_cfg()
509 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), in vfe_set_xbar_cfg()
513 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), in vfe_set_xbar_cfg()
519 u8 enable) in vfe_set_realign_cfg() argument
534 vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); in vfe_reg_update()
536 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); in vfe_reg_update()
543 vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); in vfe_reg_update_clear()
547 enum vfe_line_id line_id, u8 enable) in vfe_enable_irq_wm_line() argument
554 if (enable) { in vfe_enable_irq_wm_line()
564 enum vfe_line_id line_id, u8 enable) in vfe_enable_irq_pix_line() argument
566 struct vfe_output *output = &vfe->line[line_id].output; in vfe_enable_irq_pix_line() local
577 for (i = 0; i < output->wm_num; i++) { in vfe_enable_irq_pix_line()
579 output->wm_idx[i]); in vfe_enable_irq_pix_line()
580 comp_mask |= (1 << output->wm_idx[i]) << comp * 8; in vfe_enable_irq_pix_line()
583 if (enable) { in vfe_enable_irq_pix_line()
608 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); in vfe_set_demux_cfg()
611 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); in vfe_set_demux_cfg()
614 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); in vfe_set_demux_cfg()
616 switch (line->fmt[MSM_VFE_PAD_SINK].code) { in vfe_set_demux_cfg()
636 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); in vfe_set_demux_cfg()
637 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); in vfe_set_demux_cfg()
642 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_scale_cfg()
644 u16 input, output; in vfe_set_scale_cfg() local
648 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); in vfe_set_scale_cfg()
650 input = line->fmt[MSM_VFE_PAD_SINK].width; in vfe_set_scale_cfg()
651 output = line->compose.width; in vfe_set_scale_cfg()
652 reg = (output << 16) | input; in vfe_set_scale_cfg()
653 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); in vfe_set_scale_cfg()
655 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
656 phase_mult = input * (1 << (13 + interp_reso)) / output; in vfe_set_scale_cfg()
658 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); in vfe_set_scale_cfg()
660 input = line->fmt[MSM_VFE_PAD_SINK].height; in vfe_set_scale_cfg()
661 output = line->compose.height; in vfe_set_scale_cfg()
662 reg = (output << 16) | input; in vfe_set_scale_cfg()
663 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); in vfe_set_scale_cfg()
665 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
666 phase_mult = input * (1 << (13 + interp_reso)) / output; in vfe_set_scale_cfg()
668 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); in vfe_set_scale_cfg()
670 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); in vfe_set_scale_cfg()
672 input = line->fmt[MSM_VFE_PAD_SINK].width; in vfe_set_scale_cfg()
673 output = line->compose.width / 2; in vfe_set_scale_cfg()
674 reg = (output << 16) | input; in vfe_set_scale_cfg()
675 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); in vfe_set_scale_cfg()
677 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
678 phase_mult = input * (1 << (13 + interp_reso)) / output; in vfe_set_scale_cfg()
680 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); in vfe_set_scale_cfg()
682 input = line->fmt[MSM_VFE_PAD_SINK].height; in vfe_set_scale_cfg()
683 output = line->compose.height; in vfe_set_scale_cfg()
685 output = line->compose.height / 2; in vfe_set_scale_cfg()
686 reg = (output << 16) | input; in vfe_set_scale_cfg()
687 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); in vfe_set_scale_cfg()
689 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
690 phase_mult = input * (1 << (13 + interp_reso)) / output; in vfe_set_scale_cfg()
692 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); in vfe_set_scale_cfg()
697 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_crop_cfg()
701 first = line->crop.left; in vfe_set_crop_cfg()
702 last = line->crop.left + line->crop.width - 1; in vfe_set_crop_cfg()
704 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); in vfe_set_crop_cfg()
706 first = line->crop.top; in vfe_set_crop_cfg()
707 last = line->crop.top + line->crop.height - 1; in vfe_set_crop_cfg()
709 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); in vfe_set_crop_cfg()
711 first = line->crop.left / 2; in vfe_set_crop_cfg()
712 last = line->crop.left / 2 + line->crop.width / 2 - 1; in vfe_set_crop_cfg()
714 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); in vfe_set_crop_cfg()
716 first = line->crop.top; in vfe_set_crop_cfg()
717 last = line->crop.top + line->crop.height - 1; in vfe_set_crop_cfg()
719 first = line->crop.top / 2; in vfe_set_crop_cfg()
720 last = line->crop.top / 2 + line->crop.height / 2 - 1; in vfe_set_crop_cfg()
723 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); in vfe_set_crop_cfg()
732 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); in vfe_set_clamp_cfg()
738 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); in vfe_set_clamp_cfg()
746 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); in vfe_set_qos()
747 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); in vfe_set_qos()
748 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); in vfe_set_qos()
749 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); in vfe_set_qos()
750 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); in vfe_set_qos()
751 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); in vfe_set_qos()
752 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); in vfe_set_qos()
753 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); in vfe_set_qos()
761 static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_set_cgc_override() argument
765 if (enable) in vfe_set_cgc_override()
777 switch (line->fmt[MSM_VFE_PAD_SINK].code) { in vfe_set_camif_cfg()
793 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); in vfe_set_camif_cfg()
795 val = line->fmt[MSM_VFE_PAD_SINK].width * 2; in vfe_set_camif_cfg()
796 val |= line->fmt[MSM_VFE_PAD_SINK].height << 16; in vfe_set_camif_cfg()
797 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); in vfe_set_camif_cfg()
799 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; in vfe_set_camif_cfg()
800 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); in vfe_set_camif_cfg()
802 val = line->fmt[MSM_VFE_PAD_SINK].height - 1; in vfe_set_camif_cfg()
803 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); in vfe_set_camif_cfg()
806 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG_0); in vfe_set_camif_cfg()
809 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); in vfe_set_camif_cfg()
815 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); in vfe_set_camif_cfg()
818 static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) in vfe_set_camif_cmd() argument
823 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); in vfe_set_camif_cmd()
826 if (enable) in vfe_set_camif_cmd()
831 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); in vfe_set_camif_cmd()
834 static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) in vfe_set_module_cfg() argument
841 if (enable) in vfe_set_module_cfg()
842 writel_relaxed(val, vfe->base + VFE_0_MODULE_CFG); in vfe_set_module_cfg()
844 writel_relaxed(0x0, vfe->base + VFE_0_MODULE_CFG); in vfe_set_module_cfg()
852 ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, in vfe_camif_wait_for_stop()
865 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); in vfe_isr_read()
866 *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); in vfe_isr_read()
868 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); in vfe_isr_read()
869 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); in vfe_isr_read()
872 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); in vfe_isr_read()
877 u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); in vfe_violation_read()
883 * vfe_isr - VFE module interrupt handler
895 vfe->res->hw_ops->isr_read(vfe, &value0, &value1); in vfe_isr()
897 dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n", in vfe_isr()
901 vfe->isr_ops.reset_ack(vfe); in vfe_isr()
904 vfe->res->hw_ops->violation_read(vfe); in vfe_isr()
907 vfe->isr_ops.halt_ack(vfe); in vfe_isr()
911 vfe->isr_ops.reg_update(vfe, i); in vfe_isr()
914 vfe->isr_ops.sof(vfe, VFE_LINE_PIX); in vfe_isr()
918 vfe->isr_ops.sof(vfe, i); in vfe_isr()
922 vfe->isr_ops.comp_done(vfe, i); in vfe_isr()
923 for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) in vfe_isr()
924 if (vfe->wm_output_map[j] == VFE_LINE_PIX) in vfe_isr()
930 vfe->isr_ops.wm_done(vfe, i); in vfe_isr()
936 * vfe_pm_domain_off - Disable power domains specific to this VFE.
945 * vfe_pm_domain_on - Enable power domains specific to this VFE.
992 vfe->isr_ops = vfe_isr_ops_gen1; in vfe_subdev_init()
993 vfe->ops_gen1 = &vfe_ops_gen1_4_1; in vfe_subdev_init()
994 vfe->video_ops = vfe_video_ops_gen1; in vfe_subdev_init()