Lines Matching refs:val
178 int val;
183 val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
184 val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
185 val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL;
186 writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0);
188 val = 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN;
190 val |= 1 << CSI2_RX_CFG1_VC_MODE;
191 val |= 1 << CSI2_RX_CFG1_MISR_EN;
192 writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1);
197 int val;
200 val = HALT_CMD_RESUME_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD;
202 val = HALT_CMD_HALT_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD;
203 writel_relaxed(val, csid->base + CSID_RDI_CTRL(rdi));
214 u32 val;
220 val = vc << TPG_VC_CFG0_VC_NUM;
221 val |= INTELEAVING_MODE_ONE_SHOT << TPG_VC_CFG0_LINE_INTERLEAVING_MODE;
222 val |= 0 << TPG_VC_CFG0_NUM_FRAMES;
223 writel_relaxed(val, csid->base + CSID_TPG_VC_CFG0);
225 val = 0x740 << TPG_VC_CFG1_H_BLANKING_COUNT;
226 val |= 0x3ff << TPG_VC_CFG1_V_BLANKING_COUNT;
227 writel_relaxed(val, csid->base + CSID_TPG_VC_CFG1);
231 val = (input_format->height & 0x1fff) << TPG_DT_n_CFG_0_FRAME_HEIGHT;
232 val |= (input_format->width & 0x1fff) << TPG_DT_n_CFG_0_FRAME_WIDTH;
233 writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0));
235 val = format->data_type << TPG_DT_n_CFG_1_DATA_TYPE;
236 writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0));
238 val = (tg->mode - 1) << TPG_DT_n_CFG_2_PAYLOAD_MODE;
239 val |= 0xBE << TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD;
240 val |= format->decode_format << TPG_DT_n_CFG_2_ENCODE_FORMAT;
241 writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0));
247 val = enable << TPG_CTRL_TEST_EN;
248 val |= 1 << TPG_CTRL_FS_PKT_EN;
249 val |= 1 << TPG_CTRL_FE_PKT_EN;
250 val |= (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES;
251 val |= 0x64 << TPG_CTRL_CYCLES_BETWEEN_PKTS;
252 val |= 0xA << TPG_CTRL_NUM_TRAIL_BYTES;
253 writel_relaxed(val, csid->base + CSID_TPG_CTRL);
263 u32 val;
279 val = 1 << RDI_CFG0_BYTE_CNTR_EN;
280 val |= 1 << RDI_CFG0_FORMAT_MEASURE_EN;
281 val |= 1 << RDI_CFG0_TIMESTAMP_EN;
283 val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
284 val |= format->data_type << RDI_CFG0_DATA_TYPE;
285 val |= vc << RDI_CFG0_VIRTUAL_CHANNEL;
286 val |= dt_id << RDI_CFG0_DT_ID;
287 writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
290 val = 2 << RDI_CFG1_TIMESTAMP_STB_SEL;
291 writel_relaxed(val, csid->base + CSID_RDI_CFG1(vc));
293 val = 1;
294 writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(vc));
296 val = 0;
297 writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PATTERN(vc));
299 val = 1;
300 writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc));
302 val = 0;
303 writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc));
305 val = 1;
306 writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PERIOD(vc));
308 val = 0;
309 writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PATTERN(vc));
311 val = 1;
312 writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PERIOD(vc));
314 val = 0;
315 writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PATTERN(vc));
317 val = 0;
318 writel_relaxed(val, csid->base + CSID_RDI_CTRL(vc));
320 val = readl_relaxed(csid->base + CSID_RDI_CFG0(vc));
321 val |= enable << RDI_CFG0_ENABLE;
322 writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
341 static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
343 if (val > 0 && val <= csid->testgen.nmodes)
344 csid->testgen.mode = val;
359 u32 val;
363 val = readl_relaxed(csid->base + CSID_TOP_IRQ_STATUS);
364 writel_relaxed(val, csid->base + CSID_TOP_IRQ_CLEAR);
365 reset_done = val & BIT(TOP_IRQ_STATUS_RESET_DONE);
367 val = readl_relaxed(csid->base + CSID_CSI2_RX_IRQ_STATUS);
368 writel_relaxed(val, csid->base + CSID_CSI2_RX_IRQ_CLEAR);
373 val = readl_relaxed(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
374 writel_relaxed(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
377 val = 1 << IRQ_CMD_CLEAR;
378 writel_relaxed(val, csid->base + CSID_IRQ_CMD);
395 u32 val;
405 val = 0x1e << RST_STROBES;
406 writel_relaxed(val, csid->base + CSID_RST_STROBES);