183 	int val;  in __csid_configure_rx()  local
188 	val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;  in __csid_configure_rx()
189 	val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;  in __csid_configure_rx()
190 	val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL;  in __csid_configure_rx()
191 	writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0);  in __csid_configure_rx()
193 	val = 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN;  in __csid_configure_rx()
195 		val |= 1 << CSI2_RX_CFG1_VC_MODE;  in __csid_configure_rx()
196 	val |= 1 << CSI2_RX_CFG1_MISR_EN;  in __csid_configure_rx()
197 	writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1);  in __csid_configure_rx()
202 	int val;  in __csid_ctrl_rdi()  local
205 		val = HALT_CMD_RESUME_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD;  in __csid_ctrl_rdi()
207 		val = HALT_CMD_HALT_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD;  in __csid_ctrl_rdi()
208 	writel_relaxed(val, csid->base + CSID_RDI_CTRL(rdi));  in __csid_ctrl_rdi()
219 	u32 val;  in __csid_configure_testgen()  local
225 	val = vc << TPG_VC_CFG0_VC_NUM;  in __csid_configure_testgen()
226 	val |= INTELEAVING_MODE_ONE_SHOT << TPG_VC_CFG0_LINE_INTERLEAVING_MODE;  in __csid_configure_testgen()
227 	val |= 0 << TPG_VC_CFG0_NUM_FRAMES;  in __csid_configure_testgen()
228 	writel_relaxed(val, csid->base + CSID_TPG_VC_CFG0);  in __csid_configure_testgen()
230 	val = 0x740 << TPG_VC_CFG1_H_BLANKING_COUNT;  in __csid_configure_testgen()
231 	val |= 0x3ff << TPG_VC_CFG1_V_BLANKING_COUNT;  in __csid_configure_testgen()
232 	writel_relaxed(val, csid->base + CSID_TPG_VC_CFG1);  in __csid_configure_testgen()
236 	val = (input_format->height & 0x1fff) << TPG_DT_n_CFG_0_FRAME_HEIGHT;  in __csid_configure_testgen()
237 	val |= (input_format->width & 0x1fff) << TPG_DT_n_CFG_0_FRAME_WIDTH;  in __csid_configure_testgen()
238 	writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0));  in __csid_configure_testgen()
240 	val = format->data_type << TPG_DT_n_CFG_1_DATA_TYPE;  in __csid_configure_testgen()
241 	writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0));  in __csid_configure_testgen()
243 	val = (tg->mode - 1) << TPG_DT_n_CFG_2_PAYLOAD_MODE;  in __csid_configure_testgen()
244 	val |= 0xBE << TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD;  in __csid_configure_testgen()
245 	val |= format->decode_format << TPG_DT_n_CFG_2_ENCODE_FORMAT;  in __csid_configure_testgen()
246 	writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0));  in __csid_configure_testgen()
252 	val = enable << TPG_CTRL_TEST_EN;  in __csid_configure_testgen()
253 	val |= 1 << TPG_CTRL_FS_PKT_EN;  in __csid_configure_testgen()
254 	val |= 1 << TPG_CTRL_FE_PKT_EN;  in __csid_configure_testgen()
255 	val |= (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES;  in __csid_configure_testgen()
256 	val |= 0x64 << TPG_CTRL_CYCLES_BETWEEN_PKTS;  in __csid_configure_testgen()
257 	val |= 0xA << TPG_CTRL_NUM_TRAIL_BYTES;  in __csid_configure_testgen()
258 	writel_relaxed(val, csid->base + CSID_TPG_CTRL);  in __csid_configure_testgen()
268 	u32 val;  in __csid_configure_rdi_stream()  local
284 	val = 1 << RDI_CFG0_BYTE_CNTR_EN;  in __csid_configure_rdi_stream()
285 	val |= 1 << RDI_CFG0_FORMAT_MEASURE_EN;  in __csid_configure_rdi_stream()
286 	val |= 1 << RDI_CFG0_TIMESTAMP_EN;  in __csid_configure_rdi_stream()
288 	val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;  in __csid_configure_rdi_stream()
289 	val |= format->data_type << RDI_CFG0_DATA_TYPE;  in __csid_configure_rdi_stream()
290 	val |= vc << RDI_CFG0_VIRTUAL_CHANNEL;  in __csid_configure_rdi_stream()
291 	val |= dt_id << RDI_CFG0_DT_ID;  in __csid_configure_rdi_stream()
292 	writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));  in __csid_configure_rdi_stream()
295 	val = 2 << RDI_CFG1_TIMESTAMP_STB_SEL;  in __csid_configure_rdi_stream()
296 	writel_relaxed(val, csid->base + CSID_RDI_CFG1(vc));  in __csid_configure_rdi_stream()
298 	val = 1;  in __csid_configure_rdi_stream()
299 	writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(vc));  in __csid_configure_rdi_stream()
301 	val = 0;  in __csid_configure_rdi_stream()
302 	writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PATTERN(vc));  in __csid_configure_rdi_stream()
304 	val = 1;  in __csid_configure_rdi_stream()
305 	writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc));  in __csid_configure_rdi_stream()
307 	val = 0;  in __csid_configure_rdi_stream()
308 	writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc));  in __csid_configure_rdi_stream()
310 	val = 1;  in __csid_configure_rdi_stream()
311 	writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PERIOD(vc));  in __csid_configure_rdi_stream()
313 	val = 0;  in __csid_configure_rdi_stream()
314 	writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PATTERN(vc));  in __csid_configure_rdi_stream()
316 	val = 1;  in __csid_configure_rdi_stream()
317 	writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PERIOD(vc));  in __csid_configure_rdi_stream()
319 	val = 0;  in __csid_configure_rdi_stream()
320 	writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PATTERN(vc));  in __csid_configure_rdi_stream()
322 	val = 0;  in __csid_configure_rdi_stream()
323 	writel_relaxed(val, csid->base + CSID_RDI_CTRL(vc));  in __csid_configure_rdi_stream()
325 	val = readl_relaxed(csid->base + CSID_RDI_CFG0(vc));  in __csid_configure_rdi_stream()
326 	val |=  enable << RDI_CFG0_ENABLE;  in __csid_configure_rdi_stream()
327 	writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));  in __csid_configure_rdi_stream()
346 static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)  in csid_configure_testgen_pattern()  argument
348 	if (val > 0 && val <= csid->testgen.nmodes)  in csid_configure_testgen_pattern()
349 		csid->testgen.mode = val;  in csid_configure_testgen_pattern()
387 	u32 val;  in csid_isr()  local
391 	val = readl_relaxed(csid->base + CSID_TOP_IRQ_STATUS);  in csid_isr()
392 	writel_relaxed(val, csid->base + CSID_TOP_IRQ_CLEAR);  in csid_isr()
393 	reset_done = val & BIT(TOP_IRQ_STATUS_RESET_DONE);  in csid_isr()
395 	val = readl_relaxed(csid->base + CSID_CSI2_RX_IRQ_STATUS);  in csid_isr()
396 	writel_relaxed(val, csid->base + CSID_CSI2_RX_IRQ_CLEAR);  in csid_isr()
401 			val = readl_relaxed(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));  in csid_isr()
402 			writel_relaxed(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));  in csid_isr()
405 	val = 1 << IRQ_CMD_CLEAR;  in csid_isr()
406 	writel_relaxed(val, csid->base + CSID_IRQ_CMD);  in csid_isr()
423 	u32 val;  in csid_reset()  local
433 	val = 0x1e << RST_STROBES;  in csid_reset()
434 	writel_relaxed(val, csid->base + CSID_RST_STROBES);  in csid_reset()