Lines Matching full:sxe
277 tegra_vde_set_bits(vde, 0x000A, vde->sxe, 0xF0); in tegra_vde_setup_hw_context()
293 tegra_vde_writel(vde, 0x00000010, vde->sxe, 0x08); in tegra_vde_setup_hw_context()
294 tegra_vde_writel(vde, 0x00000150, vde->sxe, 0x54); in tegra_vde_setup_hw_context()
295 tegra_vde_writel(vde, 0x0000054C, vde->sxe, 0x58); in tegra_vde_setup_hw_context()
296 tegra_vde_writel(vde, 0x00000E34, vde->sxe, 0x5C); in tegra_vde_setup_hw_context()
362 tegra_vde_writel(vde, value, vde->sxe, 0x10); in tegra_vde_setup_hw_context()
370 tegra_vde_writel(vde, value, vde->sxe, 0x40); in tegra_vde_setup_hw_context()
376 tegra_vde_writel(vde, value, vde->sxe, 0x44); in tegra_vde_setup_hw_context()
383 tegra_vde_writel(vde, value, vde->sxe, 0x48); in tegra_vde_setup_hw_context()
388 tegra_vde_writel(vde, value, vde->sxe, 0x4C); in tegra_vde_setup_hw_context()
393 tegra_vde_writel(vde, value, vde->sxe, 0x68); in tegra_vde_setup_hw_context()
395 tegra_vde_writel(vde, bitstream_data_addr, vde->sxe, 0x6C); in tegra_vde_setup_hw_context()
398 tegra_vde_writel(vde, vde->secure_bo->dma_addr, vde->sxe, 0x7c); in tegra_vde_setup_hw_context()
460 vde->sxe, 0x00); in tegra_vde_decode_frame()
635 macroblocks_nb = tegra_vde_readl(vde, vde->sxe, 0xC8) & 0x1FFF; in tegra_vde_decode_end()