19 #define FLAG_B_FRAME		0x1
20 #define FLAG_REFERENCE		0x2
52 	return readl_relaxed_poll_timeout(vde->mbe + 0x8C, tmp,  in tegra_vde_wait_mbe()
53 					  tmp >= 0x10, 1, 100);  in tegra_vde_wait_mbe()
60 	u32 value, frame_idx_enb_mask = 0;  in tegra_vde_setup_mbe_frame_idx()
65 	tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80);  in tegra_vde_setup_mbe_frame_idx()
66 	tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80);  in tegra_vde_setup_mbe_frame_idx()
73 		return 0;  in tegra_vde_setup_mbe_frame_idx()
75 	for (idx = 0, frame_idx = 1; idx < refs_nb; idx++, frame_idx++) {  in tegra_vde_setup_mbe_frame_idx()
76 		tegra_vde_writel(vde, 0xD0000000 | (frame_idx << 23),  in tegra_vde_setup_mbe_frame_idx()
77 				 vde->mbe, 0x80);  in tegra_vde_setup_mbe_frame_idx()
78 		tegra_vde_writel(vde, 0xD0200000 | (frame_idx << 23),  in tegra_vde_setup_mbe_frame_idx()
79 				 vde->mbe, 0x80);  in tegra_vde_setup_mbe_frame_idx()
84 			value = 0xC0000000;  in tegra_vde_setup_mbe_frame_idx()
88 			tegra_vde_writel(vde, value, vde->mbe, 0x80);  in tegra_vde_setup_mbe_frame_idx()
94 			frame_idx_enb_mask = 0;  in tegra_vde_setup_mbe_frame_idx()
98 	return 0;  in tegra_vde_setup_mbe_frame_idx()
103 	tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF),  in tegra_vde_mbe_set_0xa_reg()
104 			 vde->mbe, 0x80);  in tegra_vde_mbe_set_0xa_reg()
105 	tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16),  in tegra_vde_mbe_set_0xa_reg()
106 			 vde->mbe, 0x80);  in tegra_vde_mbe_set_0xa_reg()
130 		return 0;  in tegra_vde_wait_bsev()
139 	return 0;  in tegra_vde_wait_bsev()
155 	u32 y_addr  = frame ? frame->y_addr  : 0x6CDEAD00;  in tegra_vde_setup_frameid()
156 	u32 cb_addr = frame ? frame->cb_addr : 0x6CDEAD00;  in tegra_vde_setup_frameid()
157 	u32 cr_addr = frame ? frame->cr_addr : 0x6CDEAD00;  in tegra_vde_setup_frameid()
158 	u32 value1 = frame ? ((frame->luma_atoms_pitch << 16) | mbs_height) : 0;  in tegra_vde_setup_frameid()
159 	u32 value2 = frame ? ((frame->chroma_atoms_pitch << 6) | 1) : 0;  in tegra_vde_setup_frameid()
161 	tegra_vde_writel(vde, y_addr  >> 8, vde->frameid, 0x000 + frameid * 4);  in tegra_vde_setup_frameid()
162 	tegra_vde_writel(vde, cb_addr >> 8, vde->frameid, 0x100 + frameid * 4);  in tegra_vde_setup_frameid()
163 	tegra_vde_writel(vde, cr_addr >> 8, vde->frameid, 0x180 + frameid * 4);  in tegra_vde_setup_frameid()
164 	tegra_vde_writel(vde, value1,       vde->frameid, 0x080 + frameid * 4);  in tegra_vde_setup_frameid()
165 	tegra_vde_writel(vde, value2,       vde->frameid, 0x280 + frameid * 4);  in tegra_vde_setup_frameid()
175 	for (idx = 0; idx < frames_nb; idx++)  in tegra_setup_frameidx()
180 		tegra_vde_setup_frameid(vde, NULL, idx, 0, 0);  in tegra_setup_frameidx()
192 	iram_tables[0x20 * table + row * 2 + 0] = value1;  in tegra_vde_setup_iram_entry()
193 	iram_tables[0x20 * table + row * 2 + 1] = value2;  in tegra_vde_setup_iram_entry()
206 	trace_vde_ref_l0(dpb_frames[0].frame_num);  in tegra_vde_setup_iram_tables()
208 	for (i = 0; i < 16; i++) {  in tegra_vde_setup_iram_tables()
219 			aux_addr = 0x6ADEAD00;  in tegra_vde_setup_iram_tables()
220 			value = 0x3f;  in tegra_vde_setup_iram_tables()
223 		tegra_vde_setup_iram_entry(vde, 0, i, value, aux_addr);  in tegra_vde_setup_iram_tables()
229 	if (!(dpb_frames[0].flags & FLAG_B_FRAME))  in tegra_vde_setup_iram_tables()
239 	for (i = 0, k = with_earlier_poc_nb; i < with_later_poc_nb; i++, k++) {  in tegra_vde_setup_iram_tables()
252 	for (k = 0; i < ref_frames_nb; i++, k++) {  in tegra_vde_setup_iram_tables()
277 	tegra_vde_set_bits(vde, 0x000A, vde->sxe, 0xF0);  in tegra_vde_setup_hw_context()
278 	tegra_vde_set_bits(vde, 0x000B, vde->bsev, CMDQUE_CONTROL);  in tegra_vde_setup_hw_context()
279 	tegra_vde_set_bits(vde, 0x8002, vde->mbe, 0x50);  in tegra_vde_setup_hw_context()
280 	tegra_vde_set_bits(vde, 0x000A, vde->mbe, 0xA0);  in tegra_vde_setup_hw_context()
281 	tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x14);  in tegra_vde_setup_hw_context()
282 	tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x28);  in tegra_vde_setup_hw_context()
283 	tegra_vde_set_bits(vde, 0x0A00, vde->mce, 0x08);  in tegra_vde_setup_hw_context()
284 	tegra_vde_set_bits(vde, 0x000A, vde->tfe, 0x00);  in tegra_vde_setup_hw_context()
285 	tegra_vde_set_bits(vde, 0x0005, vde->vdma, 0x04);  in tegra_vde_setup_hw_context()
287 	tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x1C);  in tegra_vde_setup_hw_context()
288 	tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x00);  in tegra_vde_setup_hw_context()
289 	tegra_vde_writel(vde, 0x00000007, vde->vdma, 0x04);  in tegra_vde_setup_hw_context()
290 	tegra_vde_writel(vde, 0x00000007, vde->frameid, 0x200);  in tegra_vde_setup_hw_context()
291 	tegra_vde_writel(vde, 0x00000005, vde->tfe, 0x04);  in tegra_vde_setup_hw_context()
292 	tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84);  in tegra_vde_setup_hw_context()
293 	tegra_vde_writel(vde, 0x00000010, vde->sxe, 0x08);  in tegra_vde_setup_hw_context()
294 	tegra_vde_writel(vde, 0x00000150, vde->sxe, 0x54);  in tegra_vde_setup_hw_context()
295 	tegra_vde_writel(vde, 0x0000054C, vde->sxe, 0x58);  in tegra_vde_setup_hw_context()
296 	tegra_vde_writel(vde, 0x00000E34, vde->sxe, 0x5C);  in tegra_vde_setup_hw_context()
297 	tegra_vde_writel(vde, 0x063C063C, vde->mce, 0x10);  in tegra_vde_setup_hw_context()
298 	tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS);  in tegra_vde_setup_hw_context()
299 	tegra_vde_writel(vde, 0x0000150D, vde->bsev, BSE_CONFIG);  in tegra_vde_setup_hw_context()
300 	tegra_vde_writel(vde, 0x00000100, vde->bsev, BSE_INT_ENB);  in tegra_vde_setup_hw_context()
301 	tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x98);  in tegra_vde_setup_hw_context()
302 	tegra_vde_writel(vde, 0x00000060, vde->bsev, 0x9C);  in tegra_vde_setup_hw_context()
304 	memset(vde->iram + 128, 0, macroblocks_nb / 2);  in tegra_vde_setup_hw_context()
319 	tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x8C);  in tegra_vde_setup_hw_context()
321 			 vde->bsev, 0x54);  in tegra_vde_setup_hw_context()
327 	tegra_vde_writel(vde, value, vde->bsev, 0x88);  in tegra_vde_setup_hw_context()
333 	err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x800003FC, false);  in tegra_vde_setup_hw_context()
337 	value = 0x01500000;  in tegra_vde_setup_hw_context()
338 	value |= ((vde->iram_lists_addr + 512) >> 2) & 0xFFFF;  in tegra_vde_setup_hw_context()
344 	err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x840F054C, false);  in tegra_vde_setup_hw_context()
348 	err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x80000080, false);  in tegra_vde_setup_hw_context()
352 	value = 0x0E340000 | ((vde->iram_lists_addr >> 2) & 0xFFFF);  in tegra_vde_setup_hw_context()
358 	value = 0x00800005;  in tegra_vde_setup_hw_context()
362 	tegra_vde_writel(vde, value, vde->sxe, 0x10);  in tegra_vde_setup_hw_context()
370 	tegra_vde_writel(vde, value, vde->sxe, 0x40);  in tegra_vde_setup_hw_context()
376 	tegra_vde_writel(vde, value, vde->sxe, 0x44);  in tegra_vde_setup_hw_context()
383 	tegra_vde_writel(vde, value, vde->sxe, 0x48);  in tegra_vde_setup_hw_context()
385 	value = 0x0C000000;  in tegra_vde_setup_hw_context()
386 	value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 24;  in tegra_vde_setup_hw_context()
388 	tegra_vde_writel(vde, value, vde->sxe, 0x4C);  in tegra_vde_setup_hw_context()
390 	value = 0x03800000;  in tegra_vde_setup_hw_context()
393 	tegra_vde_writel(vde, value, vde->sxe, 0x68);  in tegra_vde_setup_hw_context()
395 	tegra_vde_writel(vde, bitstream_data_addr, vde->sxe, 0x6C);  in tegra_vde_setup_hw_context()
398 		tegra_vde_writel(vde, vde->secure_bo->dma_addr, vde->sxe, 0x7c);  in tegra_vde_setup_hw_context()
400 	value = 0x10000005;  in tegra_vde_setup_hw_context()
404 	tegra_vde_writel(vde, value, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
406 	value = 0x26800000;  in tegra_vde_setup_hw_context()
411 	tegra_vde_writel(vde, value, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
413 	tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
414 	tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
415 	tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
417 	value = 0x20000000;  in tegra_vde_setup_hw_context()
420 	tegra_vde_writel(vde, value, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
424 					    ctx->pic_order_cnt_type == 0);  in tegra_vde_setup_hw_context()
430 	tegra_vde_mbe_set_0xa_reg(vde, 0, 0x000009FC);  in tegra_vde_setup_hw_context()
431 	tegra_vde_mbe_set_0xa_reg(vde, 2, 0x61DEAD00);  in tegra_vde_setup_hw_context()
432 	tegra_vde_mbe_set_0xa_reg(vde, 4, 0x62DEAD00);  in tegra_vde_setup_hw_context()
433 	tegra_vde_mbe_set_0xa_reg(vde, 6, 0x63DEAD00);  in tegra_vde_setup_hw_context()
434 	tegra_vde_mbe_set_0xa_reg(vde, 8, dpb_frames[0].aux_addr);  in tegra_vde_setup_hw_context()
436 	value = 0xFC000000;  in tegra_vde_setup_hw_context()
437 	value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 2;  in tegra_vde_setup_hw_context()
440 		value |= !!(dpb_frames[0].flags & FLAG_REFERENCE) << 1;  in tegra_vde_setup_hw_context()
442 	tegra_vde_writel(vde, value, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
450 	return 0;  in tegra_vde_setup_hw_context()
458 	tegra_vde_writel(vde, 0x00000001, vde->bsev, 0x8C);  in tegra_vde_decode_frame()
459 	tegra_vde_writel(vde, 0x20000000 | (macroblocks_nb - 1),  in tegra_vde_decode_frame()
460 			 vde->sxe, 0x00);  in tegra_vde_decode_frame()
466 	if (ctx->dpb_frames_nb == 0 || ctx->dpb_frames_nb > 17) {  in tegra_vde_validate_h264_ctx()
529 	return 0;  in tegra_vde_validate_h264_ctx()
547 	if (err < 0)  in tegra_vde_decode_begin()
585 	return 0;  in tegra_vde_decode_begin()
631 	if (time_left < 0) {  in tegra_vde_decode_end()
633 	} else if (time_left == 0) {  in tegra_vde_decode_end()
634 		bsev_ptr = tegra_vde_readl(vde, vde->bsev, 0x10);  in tegra_vde_decode_end()
635 		macroblocks_nb = tegra_vde_readl(vde, vde->sxe, 0xC8) & 0x1FFF;  in tegra_vde_decode_end()
636 		read_bytes = bsev_ptr ? bsev_ptr - vde->bitstream_data_addr : 0;  in tegra_vde_decode_end()
638 		dev_err(dev, "Decoding failed: read 0x%X bytes, %u macroblocks parsed\n",  in tegra_vde_decode_end()
643 		ret = 0;  in tegra_vde_decode_end()
681 		dev_err(dev, "Too small plane[%u] size %lu @0x%llX, should be at least %zu\n",  in tegra_vde_validate_vb_size()
686 	return 0;  in tegra_vde_validate_vb_size()
702 	unsigned int flags = 0;  in tegra_vde_h264_setup_frame()
708 	lstride = pixfmt->plane_fmt[0].bytesperline;  in tegra_vde_h264_setup_frame()
711 	err = tegra_vde_validate_vb_size(ctx, vb, 0, lsize);  in tegra_vde_h264_setup_frame()
729 	if (id == 0) {  in tegra_vde_h264_setup_frame()
742 	vde->frames[id].y_addr = tb->dma_addr[0];  in tegra_vde_h264_setup_frame()
746 	vde->frames[id].frame_num = frame_num & 0x7fffff;  in tegra_vde_h264_setup_frame()
750 	return 0;  in tegra_vde_h264_setup_frame()
788 	err = tegra_vde_h264_setup_frame(ctx, h264, NULL, &dst->vb2_buf, 0,  in tegra_vde_h264_setup_frames()
795 		return 0;  in tegra_vde_h264_setup_frames()
807 	for (i = 0; i < b.num_valid; i++) {  in tegra_vde_h264_setup_frames()
821 	return 0;  in tegra_vde_h264_setup_frames()
868 	memset(h264, 0, sizeof(*h264));  in tegra_vde_h264_setup_context()
869 	memset(vde->frames, 0, sizeof(vde->frames));  in tegra_vde_h264_setup_context()
906 	h264->chroma_qp_index_offset		= h->pps->chroma_qp_index_offset & 0x1f;  in tegra_vde_h264_setup_context()
917 	return 0;  in tegra_vde_h264_setup_context()
924 	size_t bitstream_size = vb2_get_plane_payload(&src->vb2_buf, 0);  in tegra_vde_h264_decode_run()
934 				     bitstream->dma_addr[0],  in tegra_vde_h264_decode_run()
939 	return 0;  in tegra_vde_h264_decode_run()