Lines Matching +full:comp +full:- +full:disable
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
11 #include "mtk-mdp3-cfg.h"
12 #include "mtk-mdp3-comp.h"
13 #include "mtk-mdp3-core.h"
14 #include "mtk-mdp3-regs.h"
39 return ctx->comp->mdp_dev->mdp_data->mdp_cfg; in __get_plat_cfg()
47 rdma0 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RDMA0); in get_comp_flag()
48 rsz1 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RSZ1); in get_comp_flag()
52 if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing) in get_comp_flag()
53 if (ctx->comp->inner_id == rdma0) in get_comp_flag()
56 return BIT(ctx->comp->inner_id); in get_comp_flag()
62 phys_addr_t base = ctx->comp->reg_base; in init_rdma()
63 u8 subsys_id = ctx->comp->subsys_id; in init_rdma()
66 rdma0 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RDMA0); in init_rdma()
68 return -EINVAL; in init_rdma()
70 if (mdp_cfg && mdp_cfg->rdma_support_10bit) { in init_rdma()
71 struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_COMP_RSZ1]; in init_rdma()
73 /* Disable RSZ1 */ in init_rdma()
74 if (ctx->comp->inner_id == rdma0 && prz1) in init_rdma()
75 MM_REG_WRITE(cmd, subsys_id, prz1->reg_base, PRZ_ENABLE, in init_rdma()
91 u32 colorformat = ctx->input->buffer.format.colorformat; in config_rdma_frame()
94 phys_addr_t base = ctx->comp->reg_base; in config_rdma_frame()
95 u8 subsys_id = ctx->comp->subsys_id; in config_rdma_frame()
99 if (mdp_cfg && mdp_cfg->rdma_support_10bit) { in config_rdma_frame()
111 (1 << 16), //enable pre-ultra in config_rdma_frame()
116 reg = CFG_COMP(MT8183, ctx->param, rdma.src_ctrl); in config_rdma_frame()
118 reg = CFG_COMP(MT8195, ctx->param, rdma.src_ctrl); in config_rdma_frame()
123 if (mdp_cfg->rdma_support_10bit && en_ufo) { in config_rdma_frame()
126 reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_y); in config_rdma_frame()
128 reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_y); in config_rdma_frame()
134 reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_c); in config_rdma_frame()
136 reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_c); in config_rdma_frame()
144 reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd_in_pxl); in config_rdma_frame()
146 reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd_in_pxl); in config_rdma_frame()
154 reg = CFG_COMP(MT8183, ctx->param, rdma.control); in config_rdma_frame()
157 reg = CFG_COMP(MT8195, ctx->param, rdma.control); in config_rdma_frame()
165 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]); in config_rdma_frame()
167 reg = CFG_COMP(MT8195, ctx->param, rdma.iova[0]); in config_rdma_frame()
172 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[1]); in config_rdma_frame()
174 reg = CFG_COMP(MT8195, ctx->param, rdma.iova[1]); in config_rdma_frame()
179 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[2]); in config_rdma_frame()
181 reg = CFG_COMP(MT8195, ctx->param, rdma.iova[2]); in config_rdma_frame()
187 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]); in config_rdma_frame()
189 reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[0]); in config_rdma_frame()
194 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[1]); in config_rdma_frame()
196 reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[1]); in config_rdma_frame()
201 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[2]); in config_rdma_frame()
203 reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[2]); in config_rdma_frame()
209 reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd); in config_rdma_frame()
211 reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd); in config_rdma_frame()
216 reg = CFG_COMP(MT8183, ctx->param, rdma.sf_bkgd); in config_rdma_frame()
218 reg = CFG_COMP(MT8195, ctx->param, rdma.sf_bkgd); in config_rdma_frame()
224 reg = CFG_COMP(MT8183, ctx->param, rdma.transform); in config_rdma_frame()
226 reg = CFG_COMP(MT8195, ctx->param, rdma.transform); in config_rdma_frame()
230 if (!mdp_cfg || !mdp_cfg->rdma_esl_setting) in config_rdma_frame()
234 reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con0); in config_rdma_frame()
239 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con0); in config_rdma_frame()
244 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con0); in config_rdma_frame()
249 reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con1); in config_rdma_frame()
254 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con1); in config_rdma_frame()
259 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con1); in config_rdma_frame()
264 reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con2); in config_rdma_frame()
269 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con2); in config_rdma_frame()
274 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con2); in config_rdma_frame()
279 reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con3); in config_rdma_frame()
291 u32 colorformat = ctx->input->buffer.format.colorformat; in config_rdma_subfrm()
294 phys_addr_t base = ctx->comp->reg_base; in config_rdma_subfrm()
295 u8 subsys_id = ctx->comp->subsys_id; in config_rdma_subfrm()
304 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]); in config_rdma_subfrm()
306 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[0]); in config_rdma_subfrm()
312 if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) { in config_rdma_subfrm()
314 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset_0_p); in config_rdma_subfrm()
316 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset_0_p); in config_rdma_subfrm()
325 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[1]); in config_rdma_subfrm()
327 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[1]); in config_rdma_subfrm()
333 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[2]); in config_rdma_subfrm()
335 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[2]); in config_rdma_subfrm()
341 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].src); in config_rdma_subfrm()
343 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].src); in config_rdma_subfrm()
349 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip); in config_rdma_subfrm()
351 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip); in config_rdma_subfrm()
357 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip_ofst); in config_rdma_subfrm()
359 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip_ofst); in config_rdma_subfrm()
364 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); in config_rdma_subfrm()
365 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); in config_rdma_subfrm()
367 csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); in config_rdma_subfrm()
368 csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); in config_rdma_subfrm()
370 if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only) in config_rdma_subfrm()
371 if ((csf_r - csf_l + 1) > 320) in config_rdma_subfrm()
381 struct device *dev = &ctx->comp->mdp_dev->pdev->dev; in wait_rdma_event()
382 phys_addr_t base = ctx->comp->reg_base; in wait_rdma_event()
383 u8 subsys_id = ctx->comp->subsys_id; in wait_rdma_event()
386 return -EINVAL; in wait_rdma_event()
388 if (ctx->comp->alias_id >= mdp_cfg->rdma_event_num) { in wait_rdma_event()
389 dev_err(dev, "Invalid RDMA event %d\n", ctx->comp->alias_id); in wait_rdma_event()
390 return -EINVAL; in wait_rdma_event()
393 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); in wait_rdma_event()
395 /* Disable RDMA */ in wait_rdma_event()
410 phys_addr_t base = ctx->comp->reg_base; in init_rsz()
411 u8 subsys_id = ctx->comp->subsys_id; in init_rsz()
422 dev = ctx->comp->mdp_dev->mm_subsys[MDP_MM_SUBSYS_1].mmsys; in init_rsz()
434 phys_addr_t base = ctx->comp->reg_base; in config_rsz_frame()
435 u8 subsys_id = ctx->comp->subsys_id; in config_rsz_frame()
439 if (mdp_cfg && mdp_cfg->rsz_etc_control) in config_rsz_frame()
443 bypass = CFG_COMP(MT8183, ctx->param, frame.bypass); in config_rsz_frame()
445 bypass = CFG_COMP(MT8195, ctx->param, frame.bypass); in config_rsz_frame()
448 /* Disable RSZ */ in config_rsz_frame()
454 reg = CFG_COMP(MT8183, ctx->param, rsz.control1); in config_rsz_frame()
456 reg = CFG_COMP(MT8195, ctx->param, rsz.control1); in config_rsz_frame()
461 reg = CFG_COMP(MT8183, ctx->param, rsz.control2); in config_rsz_frame()
463 reg = CFG_COMP(MT8195, ctx->param, rsz.control2); in config_rsz_frame()
468 reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_x); in config_rsz_frame()
470 reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_x); in config_rsz_frame()
475 reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_y); in config_rsz_frame()
477 reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_y); in config_rsz_frame()
488 phys_addr_t base = ctx->comp->reg_base; in config_rsz_subfrm()
489 u8 subsys_id = ctx->comp->subsys_id; in config_rsz_subfrm()
495 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].control2); in config_rsz_subfrm()
497 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].control2); in config_rsz_subfrm()
502 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].src); in config_rsz_subfrm()
504 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].src); in config_rsz_subfrm()
509 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); in config_rsz_subfrm()
510 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); in config_rsz_subfrm()
512 csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); in config_rsz_subfrm()
513 csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); in config_rsz_subfrm()
515 if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) in config_rsz_subfrm()
516 if ((csf_r - csf_l + 1) <= 16) in config_rsz_subfrm()
521 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left); in config_rsz_subfrm()
523 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left); in config_rsz_subfrm()
528 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left_subpix); in config_rsz_subfrm()
530 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left_subpix); in config_rsz_subfrm()
536 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top); in config_rsz_subfrm()
538 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top); in config_rsz_subfrm()
543 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top_subpix); in config_rsz_subfrm()
545 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top_subpix); in config_rsz_subfrm()
550 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left); in config_rsz_subfrm()
552 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left); in config_rsz_subfrm()
558 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left_subpix); in config_rsz_subfrm()
560 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left_subpix); in config_rsz_subfrm()
566 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].clip); in config_rsz_subfrm()
568 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].clip); in config_rsz_subfrm()
575 const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data; in config_rsz_subfrm()
576 enum mtk_mdp_comp_id public_id = ctx->comp->public_id; in config_rsz_subfrm()
580 merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE2]; in config_rsz_subfrm()
583 merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE3]; in config_rsz_subfrm()
590 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].rsz_switch); in config_rsz_subfrm()
592 id = data->comp_data[public_id].match.alias_id; in config_rsz_subfrm()
593 dev = ctx->comp->mdp_dev->mm_subsys[MDP_MM_SUBSYS_1].mmsys; in config_rsz_subfrm()
597 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].merge_cfg); in config_rsz_subfrm()
598 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
600 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
602 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
604 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
608 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
610 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
623 if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) { in advance_rsz_subfrm()
624 phys_addr_t base = ctx->comp->reg_base; in advance_rsz_subfrm()
625 u8 subsys_id = ctx->comp->subsys_id; in advance_rsz_subfrm()
629 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); in advance_rsz_subfrm()
630 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); in advance_rsz_subfrm()
632 csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); in advance_rsz_subfrm()
633 csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); in advance_rsz_subfrm()
636 if ((csf_r - csf_l + 1) <= 16) in advance_rsz_subfrm()
654 phys_addr_t base = ctx->comp->reg_base; in init_wrot()
655 u8 subsys_id = ctx->comp->subsys_id; in init_wrot()
675 phys_addr_t base = ctx->comp->reg_base; in config_wrot_frame()
676 u8 subsys_id = ctx->comp->subsys_id; in config_wrot_frame()
681 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]); in config_wrot_frame()
683 reg = CFG_COMP(MT8195, ctx->param, wrot.iova[0]); in config_wrot_frame()
688 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[1]); in config_wrot_frame()
690 reg = CFG_COMP(MT8195, ctx->param, wrot.iova[1]); in config_wrot_frame()
695 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[2]); in config_wrot_frame()
697 reg = CFG_COMP(MT8195, ctx->param, wrot.iova[2]); in config_wrot_frame()
701 if (mdp_cfg && mdp_cfg->wrot_support_10bit) { in config_wrot_frame()
703 reg = CFG_COMP(MT8195, ctx->param, wrot.scan_10bit); in config_wrot_frame()
708 reg = CFG_COMP(MT8195, ctx->param, wrot.pending_zero); in config_wrot_frame()
714 reg = CFG_COMP(MT8195, ctx->param, wrot.bit_number); in config_wrot_frame()
721 reg = CFG_COMP(MT8183, ctx->param, wrot.control); in config_wrot_frame()
723 reg = CFG_COMP(MT8195, ctx->param, wrot.control); in config_wrot_frame()
727 /* Write pre-ultra threshold */ in config_wrot_frame()
729 reg = CFG_COMP(MT8195, ctx->param, wrot.pre_ultra); in config_wrot_frame()
736 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]); in config_wrot_frame()
738 reg = CFG_COMP(MT8195, ctx->param, wrot.stride[0]); in config_wrot_frame()
744 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[1]); in config_wrot_frame()
746 reg = CFG_COMP(MT8195, ctx->param, wrot.stride[1]); in config_wrot_frame()
751 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[2]); in config_wrot_frame()
753 reg = CFG_COMP(MT8195, ctx->param, wrot.stride[2]); in config_wrot_frame()
759 reg = CFG_COMP(MT8183, ctx->param, wrot.mat_ctrl); in config_wrot_frame()
761 reg = CFG_COMP(MT8195, ctx->param, wrot.mat_ctrl); in config_wrot_frame()
773 reg = CFG_COMP(MT8183, ctx->param, wrot.fifo_test); in config_wrot_frame()
775 reg = CFG_COMP(MT8195, ctx->param, wrot.fifo_test); in config_wrot_frame()
782 if (mdp_cfg && mdp_cfg->wrot_filter_constraint) { in config_wrot_frame()
784 reg = CFG_COMP(MT8183, ctx->param, wrot.filter); in config_wrot_frame()
786 reg = CFG_COMP(MT8195, ctx->param, wrot.filter); in config_wrot_frame()
802 phys_addr_t base = ctx->comp->reg_base; in config_wrot_subfrm()
803 u8 subsys_id = ctx->comp->subsys_id; in config_wrot_subfrm()
808 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]); in config_wrot_subfrm()
810 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[0]); in config_wrot_subfrm()
816 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[1]); in config_wrot_subfrm()
818 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[1]); in config_wrot_subfrm()
824 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[2]); in config_wrot_subfrm()
826 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[2]); in config_wrot_subfrm()
832 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].src); in config_wrot_subfrm()
834 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].src); in config_wrot_subfrm()
840 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip); in config_wrot_subfrm()
842 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip); in config_wrot_subfrm()
847 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip_ofst); in config_wrot_subfrm()
849 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip_ofst); in config_wrot_subfrm()
854 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].main_buf); in config_wrot_subfrm()
856 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].main_buf); in config_wrot_subfrm()
869 struct device *dev = &ctx->comp->mdp_dev->pdev->dev; in wait_wrot_event()
870 phys_addr_t base = ctx->comp->reg_base; in wait_wrot_event()
871 u8 subsys_id = ctx->comp->subsys_id; in wait_wrot_event()
874 return -EINVAL; in wait_wrot_event()
876 if (ctx->comp->alias_id >= mdp_cfg->wrot_event_num) { in wait_wrot_event()
877 dev_err(dev, "Invalid WROT event %d!\n", ctx->comp->alias_id); in wait_wrot_event()
878 return -EINVAL; in wait_wrot_event()
881 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); in wait_wrot_event()
883 if (mdp_cfg && mdp_cfg->wrot_filter_constraint) in wait_wrot_event()
887 /* Disable WROT */ in wait_wrot_event()
903 phys_addr_t base = ctx->comp->reg_base; in init_wdma()
904 u8 subsys_id = ctx->comp->subsys_id; in init_wdma()
917 phys_addr_t base = ctx->comp->reg_base; in config_wdma_frame()
918 u8 subsys_id = ctx->comp->subsys_id; in config_wdma_frame()
926 reg = CFG_COMP(MT8183, ctx->param, wdma.wdma_cfg); in config_wdma_frame()
931 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[0]); in config_wdma_frame()
935 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[1]); in config_wdma_frame()
939 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[2]); in config_wdma_frame()
944 reg = CFG_COMP(MT8183, ctx->param, wdma.w_in_byte); in config_wdma_frame()
949 reg = CFG_COMP(MT8183, ctx->param, wdma.uv_stride); in config_wdma_frame()
962 phys_addr_t base = ctx->comp->reg_base; in config_wdma_subfrm()
963 u8 subsys_id = ctx->comp->subsys_id; in config_wdma_subfrm()
968 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[0]); in config_wdma_subfrm()
973 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[1]); in config_wdma_subfrm()
978 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[2]); in config_wdma_subfrm()
983 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].src); in config_wdma_subfrm()
988 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip); in config_wdma_subfrm()
993 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip_ofst); in config_wdma_subfrm()
1005 phys_addr_t base = ctx->comp->reg_base; in wait_wdma_event()
1006 u8 subsys_id = ctx->comp->subsys_id; in wait_wdma_event()
1008 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); in wait_wdma_event()
1009 /* Disable WDMA */ in wait_wdma_event()
1025 phys_addr_t base = ctx->comp->reg_base; in reset_luma_hist()
1026 u16 subsys_id = ctx->comp->subsys_id; in reset_luma_hist()
1030 return -EINVAL; in reset_luma_hist()
1032 hist_num = mdp_cfg->tdshp_hist_num; in reset_luma_hist()
1040 if (mdp_cfg->tdshp_constrain) in reset_luma_hist()
1044 if (mdp_cfg->tdshp_contour) in reset_luma_hist()
1055 phys_addr_t base = ctx->comp->reg_base; in init_tdshp()
1056 u16 subsys_id = ctx->comp->subsys_id; in init_tdshp()
1069 phys_addr_t base = ctx->comp->reg_base; in config_tdshp_frame()
1070 u16 subsys_id = ctx->comp->subsys_id; in config_tdshp_frame()
1074 reg = CFG_COMP(MT8195, ctx->param, tdshp.cfg); in config_tdshp_frame()
1083 phys_addr_t base = ctx->comp->reg_base; in config_tdshp_subfrm()
1084 u16 subsys_id = ctx->comp->subsys_id; in config_tdshp_subfrm()
1088 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].src); in config_tdshp_subfrm()
1093 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip_ofst); in config_tdshp_subfrm()
1098 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip); in config_tdshp_subfrm()
1103 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_0); in config_tdshp_subfrm()
1107 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_1); in config_tdshp_subfrm()
1122 phys_addr_t base = ctx->comp->reg_base; in init_color()
1123 u16 subsys_id = ctx->comp->subsys_id; in init_color()
1148 phys_addr_t base = ctx->comp->reg_base; in config_color_frame()
1149 u16 subsys_id = ctx->comp->subsys_id; in config_color_frame()
1153 reg = CFG_COMP(MT8195, ctx->param, color.start); in config_color_frame()
1163 phys_addr_t base = ctx->comp->reg_base; in config_color_subfrm()
1164 u16 subsys_id = ctx->comp->subsys_id; in config_color_subfrm()
1168 reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_hsize); in config_color_subfrm()
1173 reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_vsize); in config_color_subfrm()
1189 phys_addr_t base = ctx->comp->reg_base; in init_ccorr()
1190 u8 subsys_id = ctx->comp->subsys_id; in init_ccorr()
1202 phys_addr_t base = ctx->comp->reg_base; in config_ccorr_subfrm()
1203 u8 subsys_id = ctx->comp->subsys_id; in config_ccorr_subfrm()
1209 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); in config_ccorr_subfrm()
1210 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); in config_ccorr_subfrm()
1211 csf_t = CFG_COMP(MT8183, ctx->param, subfrms[index].in.top); in config_ccorr_subfrm()
1212 csf_b = CFG_COMP(MT8183, ctx->param, subfrms[index].in.bottom); in config_ccorr_subfrm()
1215 hsize = csf_r - csf_l + 1; in config_ccorr_subfrm()
1216 vsize = csf_b - csf_t + 1; in config_ccorr_subfrm()
1230 phys_addr_t base = ctx->comp->reg_base; in init_aal()
1231 u16 subsys_id = ctx->comp->subsys_id; in init_aal()
1243 phys_addr_t base = ctx->comp->reg_base; in config_aal_frame()
1244 u16 subsys_id = ctx->comp->subsys_id; in config_aal_frame()
1248 reg = CFG_COMP(MT8195, ctx->param, aal.cfg_main); in config_aal_frame()
1252 reg = CFG_COMP(MT8195, ctx->param, aal.cfg); in config_aal_frame()
1261 phys_addr_t base = ctx->comp->reg_base; in config_aal_subfrm()
1262 u16 subsys_id = ctx->comp->subsys_id; in config_aal_subfrm()
1266 reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].src); in config_aal_subfrm()
1271 reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip_ofst); in config_aal_subfrm()
1276 reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip); in config_aal_subfrm()
1292 phys_addr_t base = ctx->comp->reg_base; in init_hdr()
1293 u16 subsys_id = ctx->comp->subsys_id; in init_hdr()
1305 phys_addr_t base = ctx->comp->reg_base; in config_hdr_frame()
1306 u16 subsys_id = ctx->comp->subsys_id; in config_hdr_frame()
1310 reg = CFG_COMP(MT8195, ctx->param, hdr.top); in config_hdr_frame()
1314 reg = CFG_COMP(MT8195, ctx->param, hdr.relay); in config_hdr_frame()
1323 phys_addr_t base = ctx->comp->reg_base; in config_hdr_subfrm()
1324 u16 subsys_id = ctx->comp->subsys_id; in config_hdr_subfrm()
1328 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].win_size); in config_hdr_subfrm()
1333 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].src); in config_hdr_subfrm()
1337 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst0); in config_hdr_subfrm()
1341 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst1); in config_hdr_subfrm()
1345 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_0); in config_hdr_subfrm()
1349 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_1); in config_hdr_subfrm()
1353 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hdr_top); in config_hdr_subfrm()
1358 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_addr); in config_hdr_subfrm()
1373 phys_addr_t base = ctx->comp->reg_base; in init_fg()
1374 u16 subsys_id = ctx->comp->subsys_id; in init_fg()
1386 phys_addr_t base = ctx->comp->reg_base; in config_fg_frame()
1387 u16 subsys_id = ctx->comp->subsys_id; in config_fg_frame()
1391 reg = CFG_COMP(MT8195, ctx->param, fg.ctrl_0); in config_fg_frame()
1395 reg = CFG_COMP(MT8195, ctx->param, fg.ck_en); in config_fg_frame()
1404 phys_addr_t base = ctx->comp->reg_base; in config_fg_subfrm()
1405 u16 subsys_id = ctx->comp->subsys_id; in config_fg_subfrm()
1409 reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_0); in config_fg_subfrm()
1413 reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_1); in config_fg_subfrm()
1428 phys_addr_t base = ctx->comp->reg_base; in init_ovl()
1429 u16 subsys_id = ctx->comp->subsys_id; in init_ovl()
1447 phys_addr_t base = ctx->comp->reg_base; in config_ovl_frame()
1448 u16 subsys_id = ctx->comp->subsys_id; in config_ovl_frame()
1452 reg = CFG_COMP(MT8195, ctx->param, ovl.L0_con); in config_ovl_frame()
1456 reg = CFG_COMP(MT8195, ctx->param, ovl.src_con); in config_ovl_frame()
1465 phys_addr_t base = ctx->comp->reg_base; in config_ovl_subfrm()
1466 u16 subsys_id = ctx->comp->subsys_id; in config_ovl_subfrm()
1470 reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].L0_src_size); in config_ovl_subfrm()
1476 reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].roi_size); in config_ovl_subfrm()
1492 phys_addr_t base = ctx->comp->reg_base; in init_pad()
1493 u16 subsys_id = ctx->comp->subsys_id; in init_pad()
1509 phys_addr_t base = ctx->comp->reg_base; in config_pad_subfrm()
1510 u16 subsys_id = ctx->comp->subsys_id; in config_pad_subfrm()
1514 reg = CFG_COMP(MT8195, ctx->param, pad.subfrms[index].pic_size); in config_pad_subfrm()
1544 .compatible = "mediatek,mt8183-mdp3-rdma",
1547 .compatible = "mediatek,mt8183-mdp3-ccorr",
1550 .compatible = "mediatek,mt8183-mdp3-rsz",
1553 .compatible = "mediatek,mt8183-mdp3-wrot",
1556 .compatible = "mediatek,mt8183-mdp3-wdma",
1559 .compatible = "mediatek,mt8195-mdp3-rdma",
1562 .compatible = "mediatek,mt8195-mdp3-split",
1565 .compatible = "mediatek,mt8195-mdp3-stitch",
1568 .compatible = "mediatek,mt8195-mdp3-fg",
1571 .compatible = "mediatek,mt8195-mdp3-hdr",
1574 .compatible = "mediatek,mt8195-mdp3-aal",
1577 .compatible = "mediatek,mt8195-mdp3-merge",
1580 .compatible = "mediatek,mt8195-mdp3-tdshp",
1583 .compatible = "mediatek,mt8195-mdp3-color",
1586 .compatible = "mediatek,mt8195-mdp3-ovl",
1589 .compatible = "mediatek,mt8195-mdp3-padding",
1592 .compatible = "mediatek,mt8195-mdp3-tcc",
1618 for (i = 0; i < mdp->mdp_data->comp_data_len; i++) in mdp_comp_get_id()
1619 if (mdp->mdp_data->comp_data[i].match.type == type && in mdp_comp_get_id()
1620 mdp->mdp_data->comp_data[i].match.alias_id == alias_id) in mdp_comp_get_id()
1622 return -ENODEV; in mdp_comp_get_id()
1625 int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp) in mdp_comp_clock_on() argument
1630 if (comp->comp_dev && is_dma_capable(comp->type)) { in mdp_comp_clock_on()
1631 ret = pm_runtime_resume_and_get(comp->comp_dev); in mdp_comp_clock_on()
1635 ret, comp->type, comp->inner_id); in mdp_comp_clock_on()
1640 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_clock_on()
1641 if (IS_ERR_OR_NULL(comp->clks[i])) in mdp_comp_clock_on()
1643 ret = clk_prepare_enable(comp->clks[i]); in mdp_comp_clock_on()
1647 i, comp->type, comp->inner_id); in mdp_comp_clock_on()
1655 while (--i >= 0) { in mdp_comp_clock_on()
1656 if (IS_ERR_OR_NULL(comp->clks[i])) in mdp_comp_clock_on()
1658 clk_disable_unprepare(comp->clks[i]); in mdp_comp_clock_on()
1660 if (comp->comp_dev && is_dma_capable(comp->type)) in mdp_comp_clock_on()
1661 pm_runtime_put_sync(comp->comp_dev); in mdp_comp_clock_on()
1666 void mdp_comp_clock_off(struct device *dev, struct mdp_comp *comp) in mdp_comp_clock_off() argument
1670 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_clock_off()
1671 if (IS_ERR_OR_NULL(comp->clks[i])) in mdp_comp_clock_off()
1673 clk_disable_unprepare(comp->clks[i]); in mdp_comp_clock_off()
1676 if (comp->comp_dev && is_dma_capable(comp->type)) in mdp_comp_clock_off()
1677 pm_runtime_put(comp->comp_dev); in mdp_comp_clock_off()
1698 b = &m->mdp_data->comp_data[id].blend; in mdp_comp_clocks_on()
1700 if (b && b->aid_clk) { in mdp_comp_clocks_on()
1701 ret = mdp_comp_clock_on(dev, m->comp[b->b_id]); in mdp_comp_clocks_on()
1726 b = &m->mdp_data->comp_data[id].blend; in mdp_comp_clocks_off()
1728 if (b && b->aid_clk) in mdp_comp_clocks_off()
1729 mdp_comp_clock_off(dev, m->comp[b->b_id]); in mdp_comp_clocks_off()
1734 struct device_node *node, struct mdp_comp *comp) in mdp_get_subsys_id() argument
1741 if (!dev || !node || !comp) in mdp_get_subsys_id()
1742 return -EINVAL; in mdp_get_subsys_id()
1747 dev_err(dev, "get comp_pdev fail! comp public id=%d, inner id=%d, type=%d\n", in mdp_get_subsys_id()
1748 comp->public_id, comp->inner_id, comp->type); in mdp_get_subsys_id()
1749 return -ENODEV; in mdp_get_subsys_id()
1752 index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst; in mdp_get_subsys_id()
1753 ret = cmdq_dev_get_client_reg(&comp_pdev->dev, &cmdq_reg, index); in mdp_get_subsys_id()
1755 dev_err(&comp_pdev->dev, "cmdq_dev_get_subsys fail!\n"); in mdp_get_subsys_id()
1756 put_device(&comp_pdev->dev); in mdp_get_subsys_id()
1757 return -EINVAL; in mdp_get_subsys_id()
1760 comp->subsys_id = cmdq_reg.subsys; in mdp_get_subsys_id()
1761 dev_dbg(&comp_pdev->dev, "subsys id=%d\n", cmdq_reg.subsys); in mdp_get_subsys_id()
1762 put_device(&comp_pdev->dev); in mdp_get_subsys_id()
1768 struct mdp_comp *comp) in __mdp_comp_init() argument
1774 index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst; in __mdp_comp_init()
1780 comp->mdp_dev = mdp; in __mdp_comp_init()
1781 comp->regs = of_iomap(node, 0); in __mdp_comp_init()
1782 comp->reg_base = base; in __mdp_comp_init()
1786 struct mdp_comp *comp, enum mtk_mdp_comp_id id) in mdp_comp_init() argument
1788 struct device *dev = &mdp->pdev->dev; in mdp_comp_init()
1796 return -EINVAL; in mdp_comp_init()
1802 node->name); in mdp_comp_init()
1803 return -ENODEV; in mdp_comp_init()
1806 comp->comp_dev = &pdev_c->dev; in mdp_comp_init()
1807 comp->public_id = id; in mdp_comp_init()
1808 comp->type = mdp->mdp_data->comp_data[id].match.type; in mdp_comp_init()
1809 comp->inner_id = mdp->mdp_data->comp_data[id].match.inner_id; in mdp_comp_init()
1810 comp->alias_id = mdp->mdp_data->comp_data[id].match.alias_id; in mdp_comp_init()
1811 comp->ops = mdp_comp_ops[comp->type]; in mdp_comp_init()
1812 __mdp_comp_init(mdp, node, comp); in mdp_comp_init()
1814 comp->clk_num = mdp->mdp_data->comp_data[id].info.clk_num; in mdp_comp_init()
1815 comp->clks = devm_kzalloc(dev, sizeof(struct clk *) * comp->clk_num, in mdp_comp_init()
1817 if (!comp->clks) in mdp_comp_init()
1818 return -ENOMEM; in mdp_comp_init()
1820 clk_ofst = mdp->mdp_data->comp_data[id].info.clk_ofst; in mdp_comp_init()
1822 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_init()
1823 comp->clks[i] = of_clk_get(node, i + clk_ofst); in mdp_comp_init()
1824 if (IS_ERR(comp->clks[i])) in mdp_comp_init()
1828 mdp_get_subsys_id(mdp, dev, node, comp); in mdp_comp_init()
1831 if (is_bypass_gce_event(comp->type) || in mdp_comp_init()
1832 of_property_read_u32_index(node, "mediatek,gce-events", in mdp_comp_init()
1836 comp->gce_event[MDP_GCE_EVENT_SOF] = event; in mdp_comp_init()
1839 if (is_dma_capable(comp->type)) { in mdp_comp_init()
1840 if (of_property_read_u32_index(node, "mediatek,gce-events", in mdp_comp_init()
1843 return -EINVAL; in mdp_comp_init()
1849 comp->gce_event[MDP_GCE_EVENT_EOF] = event; in mdp_comp_init()
1854 static void mdp_comp_deinit(struct mdp_comp *comp) in mdp_comp_deinit() argument
1856 if (!comp) in mdp_comp_deinit()
1859 if (comp->comp_dev && comp->clks) { in mdp_comp_deinit()
1860 devm_kfree(&comp->mdp_dev->pdev->dev, comp->clks); in mdp_comp_deinit()
1861 comp->clks = NULL; in mdp_comp_deinit()
1864 if (comp->regs) in mdp_comp_deinit()
1865 iounmap(comp->regs); in mdp_comp_deinit()
1872 struct device *dev = &mdp->pdev->dev; in mdp_comp_create()
1873 struct mdp_comp *comp; in mdp_comp_create() local
1876 if (mdp->comp[id]) in mdp_comp_create()
1877 return ERR_PTR(-EEXIST); in mdp_comp_create()
1879 comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL); in mdp_comp_create()
1880 if (!comp) in mdp_comp_create()
1881 return ERR_PTR(-ENOMEM); in mdp_comp_create()
1883 ret = mdp_comp_init(mdp, node, comp, id); in mdp_comp_create()
1885 devm_kfree(dev, comp); in mdp_comp_create()
1888 mdp->comp[id] = comp; in mdp_comp_create()
1889 mdp->comp[id]->mdp_dev = mdp; in mdp_comp_create()
1892 dev->of_node->name, comp->type, comp->alias_id, id, comp->inner_id, in mdp_comp_create()
1893 (u32)comp->reg_base, comp->regs); in mdp_comp_create()
1894 return comp; in mdp_comp_create()
1899 struct device *dev = &mdp->pdev->dev; in mdp_comp_sub_create()
1903 parent = dev->of_node->parent; in mdp_comp_sub_create()
1909 struct mdp_comp *comp; in mdp_comp_sub_create() local
1911 of_id = of_match_node(mdp->mdp_data->mdp_sub_comp_dt_ids, node); in mdp_comp_sub_create()
1915 dev_dbg(dev, "Skipping disabled sub comp. %pOF\n", in mdp_comp_sub_create()
1920 type = (enum mdp_comp_type)(uintptr_t)of_id->data; in mdp_comp_sub_create()
1925 "Fail to get sub comp. id: type %d alias %d\n", in mdp_comp_sub_create()
1927 ret = -EINVAL; in mdp_comp_sub_create()
1932 comp = mdp_comp_create(mdp, node, id); in mdp_comp_sub_create()
1933 if (IS_ERR(comp)) { in mdp_comp_sub_create()
1934 ret = PTR_ERR(comp); in mdp_comp_sub_create()
1949 for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) { in mdp_comp_destroy()
1950 if (mdp->comp[i]) { in mdp_comp_destroy()
1951 if (is_dma_capable(mdp->comp[i]->type)) in mdp_comp_destroy()
1952 pm_runtime_disable(mdp->comp[i]->comp_dev); in mdp_comp_destroy()
1953 mdp_comp_deinit(mdp->comp[i]); in mdp_comp_destroy()
1954 devm_kfree(mdp->comp[i]->comp_dev, mdp->comp[i]); in mdp_comp_destroy()
1955 mdp->comp[i] = NULL; in mdp_comp_destroy()
1962 struct device *dev = &mdp->pdev->dev; in mdp_comp_config()
1967 p_id = mdp->mdp_data->mdp_plat_id; in mdp_comp_config()
1969 parent = dev->of_node->parent; in mdp_comp_config()
1975 struct mdp_comp *comp; in mdp_comp_config() local
1987 type = (enum mdp_comp_type)(uintptr_t)of_id->data; in mdp_comp_config()
1998 comp = mdp_comp_create(mdp, node, id); in mdp_comp_config()
1999 if (IS_ERR(comp)) { in mdp_comp_config()
2000 ret = PTR_ERR(comp); in mdp_comp_config()
2006 if (!is_dma_capable(comp->type)) in mdp_comp_config()
2008 pm_runtime_enable(comp->comp_dev); in mdp_comp_config()
2026 struct device *dev = &mdp->pdev->dev; in mdp_comp_ctx_config()
2033 return -EINVAL; in mdp_comp_ctx_config()
2041 return -EINVAL; in mdp_comp_ctx_config()
2045 return -EINVAL; in mdp_comp_ctx_config()
2048 ctx->comp = mdp->comp[public_id]; in mdp_comp_ctx_config()
2049 if (!ctx->comp) { in mdp_comp_ctx_config()
2051 return -EINVAL; in mdp_comp_ctx_config()
2054 ctx->param = param; in mdp_comp_ctx_config()
2060 return -EINVAL; in mdp_comp_ctx_config()
2061 ctx->input = &frame->inputs[arg]; in mdp_comp_ctx_config()
2067 return -EINVAL; in mdp_comp_ctx_config()
2074 return -EINVAL; in mdp_comp_ctx_config()
2075 ctx->outputs[i] = &frame->outputs[arg]; in mdp_comp_ctx_config()