Lines Matching defs:base
62 phys_addr_t base = ctx->comp->reg_base;
80 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_RESET, BIT(0), BIT(0));
81 MM_REG_POLL_MASK(cmd, subsys_id, base, MDP_RDMA_MON_STA_1, BIT(8), BIT(8));
82 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_RESET, 0x0, BIT(0));
94 phys_addr_t base = ctx->comp->reg_base;
101 MM_REG_WRITE_MASK(cmd, subsys_id, base,
104 MM_REG_WRITE_MASK(cmd, subsys_id, base,
109 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_GMCIF_CON,
119 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg, 0x03C8FE0F);
123 /* Setup source buffer base */
128 MM_REG_WRITE(cmd, subsys_id, base,
135 MM_REG_WRITE(cmd, subsys_id, base,
144 MM_REG_WRITE_MASK(cmd, subsys_id, base,
157 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_CON, reg, rdma_con_mask);
159 /* Setup source buffer base */
164 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg);
170 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg);
176 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg);
183 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0, reg);
189 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1, reg);
195 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2, reg);
202 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
209 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
217 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0,
225 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_0,
230 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_0,
235 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_0,
240 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_1,
245 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_1,
250 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_1,
255 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_2,
260 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_2,
265 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_2,
270 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_3,
284 phys_addr_t base = ctx->comp->reg_base;
290 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0));
297 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0, reg);
306 MM_REG_WRITE(cmd, subsys_id, base,
316 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1, reg);
323 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2, reg);
330 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg,
338 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE,
346 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1,
358 MM_REG_WRITE_MASK(cmd, subsys_id, base,
368 phys_addr_t base = ctx->comp->reg_base;
382 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0));
396 phys_addr_t base = ctx->comp->reg_base;
400 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_ENABLE, 0x10000, BIT(16));
401 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16));
403 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0));
420 phys_addr_t base = ctx->comp->reg_base;
426 MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0);
435 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0));
443 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_1, reg, 0x03FFFDF3);
449 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x0FFFC290);
455 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP, reg,
462 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP, reg,
472 phys_addr_t base = ctx->comp->reg_base;
482 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x00003800);
488 MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg);
499 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_1,
506 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET,
513 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET,
520 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET,
527 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET,
534 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET,
541 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET,
548 MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg);
602 phys_addr_t base = ctx->comp->reg_base;
615 MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0,
632 phys_addr_t base = ctx->comp->reg_base;
636 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0));
637 MM_REG_POLL_MASK(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0));
641 MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0);
643 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0));
644 MM_REG_POLL_MASK(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0));
653 phys_addr_t base = ctx->comp->reg_base;
657 /* Write frame base address */
662 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg);
668 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg);
674 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg);
679 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_SCAN_10BIT,
684 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_PENDING_ZERO,
690 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_CTRL_2,
699 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_CTRL, reg, 0xF131510F);
704 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_DMA_PREULTRA, reg,
713 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_STRIDE, reg, 0x0000FFFF);
720 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_STRIDE_C, reg, 0xFFFF);
726 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_STRIDE_V, reg, 0xFFFF);
733 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3);
736 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000,
740 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31));
749 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_FIFO_TEST, reg,
758 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, reg,
763 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_ROT_EN,
773 phys_addr_t base = ctx->comp->reg_base;
782 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_OFST_ADDR, reg, 0x0FFFFFFF);
789 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_OFST_ADDR_C, reg, 0x0FFFFFFF);
796 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_OFST_ADDR_V, reg,
804 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_IN_SIZE, reg, 0x1FFF1FFF);
811 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_TAR_SIZE, reg, 0x1FFF1FFF);
817 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_CROP_OFST, reg, 0x1FFF1FFF);
823 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, reg,
827 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0));
836 phys_addr_t base = ctx->comp->reg_base;
850 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0,
854 MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_ROT_EN, 0x0, BIT(0));
869 phys_addr_t base = ctx->comp->reg_base;
873 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_RST, BIT(0), BIT(0));
874 MM_REG_POLL_MASK(cmd, subsys_id, base, WDMA_FLOW_CTRL_DBG, BIT(0), BIT(0));
875 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_RST, 0x0, BIT(0));
883 phys_addr_t base = ctx->comp->reg_base;
887 MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050);
892 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_CFG, reg, 0x0F01B8F0);
893 /* Setup frame base address */
896 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, reg);
899 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, reg);
902 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, reg);
906 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_W_IN_BYTE, reg,
911 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_UV_PITCH, reg,
914 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF,
923 phys_addr_t base = ctx->comp->reg_base;
930 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_ADDR_OFFSET, reg,
935 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_U_ADDR_OFFSET, reg,
940 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_V_ADDR_OFFSET, reg,
945 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_SRC_SIZE, reg, 0x3FFF3FFF);
949 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_CLIP_SIZE, reg, 0x3FFF3FFF);
953 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_CLIP_COORD, reg, 0x3FFF3FFF);
956 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_EN, BIT(0), BIT(0));
963 phys_addr_t base = ctx->comp->reg_base;
968 MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_EN, 0x0, BIT(0));
983 phys_addr_t base = ctx->comp->reg_base;
994 MM_REG_WRITE(cmd, subsys_id, base,
998 MM_REG_WRITE(cmd, subsys_id, base,
1003 MM_REG_WRITE(cmd, subsys_id, base,
1011 phys_addr_t base = ctx->comp->reg_base;
1014 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_TDSHP_CTRL, BIT(0), BIT(0));
1016 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_TDSHP_CFG, BIT(1), BIT(1));
1025 phys_addr_t base = ctx->comp->reg_base;
1031 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_TDSHP_CFG, reg, BIT(0));
1039 phys_addr_t base = ctx->comp->reg_base;
1045 MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_INPUT_SIZE, reg);
1049 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_OFFSET, reg,
1054 MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_SIZE, reg);
1058 MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00, reg);
1062 MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01, reg);
1076 phys_addr_t base = ctx->comp->reg_base;
1079 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_START, 0x1,
1081 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_WIN_X_MAIN, 0xFFFF0000);
1082 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_WIN_Y_MAIN, 0xFFFF0000);
1085 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_CM1_EN, 0x0, BIT(0));
1086 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_CM2_EN, 0x0, BIT(0));
1089 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_INTEN, 0x7, 0x7);
1091 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_OUT_SEL, 0x333, 0x333);
1100 phys_addr_t base = ctx->comp->reg_base;
1106 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_START, reg);
1114 phys_addr_t base = ctx->comp->reg_base;
1120 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_WIDTH,
1125 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_HEIGHT,
1140 phys_addr_t base = ctx->comp->reg_base;
1144 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_CCORR_EN, BIT(0), BIT(0));
1146 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_CCORR_CFG, BIT(0), BIT(0));
1153 phys_addr_t base = ctx->comp->reg_base;
1168 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_CCORR_SIZE,
1181 phys_addr_t base = ctx->comp->reg_base;
1185 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_AAL_EN, BIT(0), BIT(0));
1194 phys_addr_t base = ctx->comp->reg_base;
1200 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_AAL_CFG_MAIN, reg, BIT(7));
1204 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_AAL_CFG, reg, BIT(0));
1212 phys_addr_t base = ctx->comp->reg_base;
1218 MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_SIZE, reg);
1222 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_AAL_OUTPUT_OFFSET, reg,
1227 MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_SIZE, reg);
1241 phys_addr_t base = ctx->comp->reg_base;
1245 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_TOP, BIT(0), BIT(0));
1254 phys_addr_t base = ctx->comp->reg_base;
1260 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(29) | BIT(28));
1264 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_RELAY, reg, BIT(0));
1272 phys_addr_t base = ctx->comp->reg_base;
1278 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TILE_POS, reg);
1282 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_SIZE_0, reg, 0x1FFF1FFF);
1286 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_SIZE_1, reg, 0x1FFF1FFF);
1290 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_SIZE_2, reg, 0x1FFF1FFF);
1294 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0, reg, 0x00003FFF);
1298 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1, reg, 0x00003FFF);
1302 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(6) | BIT(5));
1307 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_HIST_ADDR, reg, BIT(9));
1321 phys_addr_t base = ctx->comp->reg_base;
1324 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_FG_TRIGGER, BIT(2), BIT(2));
1325 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_FG_TRIGGER, 0x0, BIT(2));
1334 phys_addr_t base = ctx->comp->reg_base;
1340 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, reg, BIT(0));
1344 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_FG_FG_CK_EN, reg, 0x7);
1352 phys_addr_t base = ctx->comp->reg_base;
1358 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, reg);
1362 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, reg);
1376 phys_addr_t base = ctx->comp->reg_base;
1379 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_EN, BIT(0));
1382 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, BIT(9));
1383 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_DP_CON, BIT(0));
1392 phys_addr_t base = ctx->comp->reg_base;
1398 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_OVL_L0_CON, reg, BIT(29) | BIT(28));
1402 MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_OVL_SRC_CON, reg, BIT(0));
1410 phys_addr_t base = ctx->comp->reg_base;
1416 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_SRC_SIZE, reg);
1421 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_ROI_SIZE, reg);
1435 phys_addr_t base = ctx->comp->reg_base;
1438 MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_CON, BIT(1));
1440 MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_W_SIZE, 0);
1441 MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_H_SIZE, 0);
1449 phys_addr_t base = ctx->comp->reg_base;
1455 MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_PIC_SIZE, reg);
1710 phys_addr_t base;
1715 base = 0L;
1717 base = res.start;
1721 comp->reg_base = base;
1830 dev_dbg(dev, "%s type:%d alias:%d public id:%d inner id:%d base:%#x regs:%p\n",