Lines Matching +full:0 +full:x4038
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
12 /* [15:0] The Version register for H264 core (Read Only) */
13 #define TW5864_H264REV 0x0000
15 #define TW5864_EMU 0x0004
18 #define TW5864_EMU_EN_DDR BIT(0)
40 #define TW5864_UNDECLARED_H264REV_PART2 0x0008
42 #define TW5864_SLICE 0x000c
45 #define TW5864_VLC_SLICE_END BIT(0)
52 * [15:0] Two bit for each channel (channel 0 ~ 7). Each two bits are the buffer
55 #define TW5864_ENC_BUF_PTR_REC1 0x0010
57 /* [5:0] DSP_MB_QP and [15:10] DSP_LPF_OFFSET */
58 #define TW5864_DSP_QP 0x0018
60 /* [5:0] H264 QP Value for codec */
61 #define TW5864_DSP_MB_QP 0x003f
64 * (Default 0)
66 #define TW5864_DSP_LPF_OFFSET 0xfc00
68 #define TW5864_DSP_CODEC 0x001c
71 * 0: Encode (TW5864 Default)
74 #define TW5864_DSP_CODEC_MODE BIT(0)
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
81 * 0 4CIF in 1 MB
86 * 0 2 falf D1 in 1 MB
97 #define TW5864_DSP_SEN 0x0020
99 /* Org Buffer Base for Luma (default 0) */
100 #define TW5864_DSP_SEN_PIC_LU 0x000f
102 #define TW5864_DSP_SEN_PIC_CHM 0x00f0
104 #define TW5864_DSP_SEN_PIC_MAX 0x0700
107 * (Default 0)
109 #define TW5864_DSP_SEN_HFULL 0x1000
111 #define TW5864_DSP_REF_PIC 0x0024
113 /* Ref Buffer Base for Luma (default 0) */
114 #define TW5864_DSP_REF_PIC_LU 0x000f
116 #define TW5864_DSP_REF_PIC_CHM 0x00f0
118 #define TW5864_DSP_REF_PIC_MAX 0x0700
120 /* [15:0] SEN_EN_CH[n] SENIF original frame capture enable for each channel */
121 #define TW5864_SEN_EN_CH 0x0028
123 #define TW5864_DSP 0x002c
126 #define TW5864_DSP_ENC_CHN 0x000f
128 #define TW5864_DSP_MB_WAIT 0x0010
131 * 0 DDRB
134 #define TW5864_DSP_CHROM_SW 0x0020
136 #define TW5864_DSP_FLW_CNTL 0x0040
138 * If DSP_MB_WAIT == 0, MB delay is DSP_MB_DELAY * 16
141 #define TW5864_DSP_MB_DELAY 0x0f00
143 #define TW5864_DDR 0x0030
146 #define TW5864_DDR_PAGE_CNTL 0x00ff
151 * 0 Select DDRA
157 * 0 Single R/W Access (Host <-> DDR)
163 /* SENIF_ORG_FRM_PTR [15:0] */
164 #define TW5864_SENIF_ORG_FRM_PTR1 0x0038
166 #define TW5864_SENIF_ORG_FRM_PTR2 0x003c
168 #define TW5864_DSP_SEN_MODE 0x0040
170 #define TW5864_DSP_SEN_MODE_CH0 0x000f
171 #define TW5864_DSP_SEN_MODE_CH1 0x00f0
174 * [15:0]: ENC_BUF_PTR_REC[31:16] Two bit for each channel (channel 8 ~ 15).
177 #define TW5864_ENC_BUF_PTR_REC2 0x004c
181 * [1:0] CH0_MV_PTR, ..., [15:14] CH7_MV_PTR
183 #define TW5864_CH_MV_PTR1 0x0060
185 * [1:0] CH8_MV_PTR, ..., [15:14] CH15_MV_PTR
187 #define TW5864_CH_MV_PTR2 0x0064
190 * [15:0] Reset Current MV Flag Status Pointer for Channel n (one bit each)
192 #define TW5864_RST_MV_PTR 0x0068
193 #define TW5864_INTERLACING 0x0200
205 * 0 Normal Un-Shuffled Frame
226 * 0 Single Stream
230 #define TW5864_DSP_REF 0x0204
233 #define TW5864_DSP_REF_FRM 0x000f
235 #define TW5864_DSP_WIN_SIZE 0x02f0
237 #define TW5864_DSP_SKIP 0x0208
241 * 0 DSP_SKIP_OFFSET value is not used (default 8)
244 #define TW5864_DSP_SKIP_OFEN 0x0080
246 #define TW5864_DSP_SKIP_OFFSET 0x007f
248 #define TW5864_MOTION_SEARCH_ETC 0x020c
251 #define TW5864_QPEL_EN BIT(0)
263 #define TW5864_DSP_ENC_REC 0x0210
266 #define TW5864_DSP_ENC_REF_PTR 0x0007
268 #define TW5864_DSP_REC_BUF_PTR 0x7000
270 /* [15:0] Lambda Value for H264 */
271 #define TW5864_DSP_REF_MVP_LAMBDA 0x0214
273 #define TW5864_DSP_PIC_MAX_MB 0x0218
276 #define TW5864_DSP_PIC_MAX_MB_Y 0x007f
278 #define TW5864_DSP_PIC_MAX_MB_X 0x7f00
281 #define TW5864_DSP_ENC_ORG_PTR_REG 0x021c
283 #define TW5864_DSP_ENC_ORG_PTR_MASK 0x7000
288 #define TW5864_DSP_OSD_ATTRI_BASE 0x0220
290 #define TW5864_DSP_OSD_ENABLE 0x0228
292 /* 0x0280 ~ 0x029c - Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */
293 #define TW5864_ME_MV_VEC1 0x0280
294 /* 0x02a0 ~ 0x02bc - Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */
295 #define TW5864_ME_MV_VEC2 0x02a0
296 /* 0x02c0 ~ 0x02dc - Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */
297 #define TW5864_ME_MV_VEC3 0x02c0
298 /* 0x02e0 ~ 0x02fc - Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */
299 #define TW5864_ME_MV_VEC4 0x02e0
302 * [5:0]
308 #define TW5864_DSP_I4x4_OFFSET 0x040c
312 * 0x5 Only 4x4
313 * 0x6 Only 16x16
314 * 0x7 16x16 & 4x4
316 #define TW5864_DSP_INTRA_MODE 0x0410
319 #define TW5864_DSP_INTRA_MODE_4x4 0x5
320 #define TW5864_DSP_INTRA_MODE_16x16 0x6
321 #define TW5864_DSP_INTRA_MODE_4x4_AND_16x16 0x7
323 * [5:0] WEIGHT Factor for I4x4 cost calculation (QP dependent)
325 #define TW5864_DSP_I4x4_WEIGHT 0x0414
328 * [7:0] Offset used to affect Intra/ME model decision
334 #define TW5864_DSP_RESID_MODE_OFFSET 0x0604
336 /* 0x0800 ~ 0x09ff - Quantization TABLE Values */
337 #define TW5864_QUAN_TAB 0x0800
339 /* Valid channel value [0; f], frame value [0; 3] */
341 (0x0c00 | (channel << 4) | (frame << 2))
343 #define TW5864_FRAME_BUS1 0x0d00
346 * 0 Interlaced in part A in bus n
348 #define TW5864_PROG_A BIT(0)
351 * 0 Interlaced in part B in bus n
356 * 0 Field Mode in bus n
360 * 0 4CIF in bus n
365 /* Bus 1 goes in TW5864_FRAME_BUS1 in [4:0] */
367 #define TW5864_FRAME_BUS2 0x0d04
368 /* Bus 3 goes in TW5864_FRAME_BUS2 in [4:0] */
371 /* [15:0] Horizontal Mirror for channel n */
372 #define TW5864_SENIF_HOR_MIR 0x0d08
373 /* [15:0] Vertical Mirror for channel n */
374 #define TW5864_SENIF_VER_MIR 0x0d0c
378 * 0x15f: 4 CIF
379 * 0x2cf: 1 D1 + 3 CIF
380 * 0x2cf: 2 D1
382 * 0x15f: 4 CIF
383 * 0x2cf: 1 D1 + 3 CIF
384 * 0x2cf: 2 D1
386 * 0x11f: 4CIF (PAL)
387 * 0x23f: 1D1 + 3CIF (PAL)
388 * 0x23f: 2 D1 (PAL)
389 * 0x0ef: 4CIF (NTSC)
390 * 0x1df: 1D1 + 3CIF (NTSC)
391 * 0x1df: 2 D1 (NTSC)
393 * 0x11f: 4CIF (PAL)
394 * 0x23f: 1D1 + 3CIF (PAL)
395 * 0x23f: 2 D1 (PAL)
396 * 0x0ef: 4CIF (NTSC)
397 * 0x1df: 1D1 + 3CIF (NTSC)
398 * 0x1df: 2 D1 (NTSC)
400 #define TW5864_FRAME_WIDTH_BUS_A(bus) (0x0d10 + 0x0010 * bus)
401 #define TW5864_FRAME_WIDTH_BUS_B(bus) (0x0d14 + 0x0010 * bus)
402 #define TW5864_FRAME_HEIGHT_BUS_A(bus) (0x0d18 + 0x0010 * bus)
403 #define TW5864_FRAME_HEIGHT_BUS_B(bus) (0x0d1c + 0x0010 * bus)
407 * 0: the bus mapped Channel n Half D1
409 #define TW5864_FULL_HALF_FLAG 0x0d50
412 * 0 The bus mapped Channel select partA Mode
415 #define TW5864_FULL_HALF_MODE_SEL 0x0d54
417 #define TW5864_VLC 0x1000
420 #define TW5864_VLC_SLICE_QP 0x003f
423 * 1 Normal (VLC output= [31:0])
424 * 0 Swap (VLC output={[23:16],[31:24],[7:0], [15:8]})
431 #define TW5864_VLC_BIT_ALIGN_MASK (0x1f << 8)
435 * 0 CPU read VLC stream
442 * 0 Non PCI Master Mode
446 * 0 Enable Adding 03 to VLC header and stream
453 * 0 VLC is not ready in buffer n (SW clear)
456 #define TW5864_VLC_BUF_RDY_MASK (0xff << 24)
459 #define TW5864_SLICE_TOTAL_BIT 0x1004
461 #define TW5864_RES_TOTAL_BIT 0x1008
463 #define TW5864_VLC_BUF 0x100c
466 #define TW5864_VLC_BK0_FULL BIT(0)
473 /* VLC string length in either buffer 0 or 1 at end of frame */
475 #define TW5864_VLC_STREAM_LEN_MASK (0x1ff << 4)
477 /* [15:0] Total coefficient number in a frame */
478 #define TW5864_TOTAL_COEF_NO 0x1010
479 /* [0] VLC Encoder Interrupt. Write '1' to clear */
480 #define TW5864_VLC_DSP_INTR 0x1014
481 /* [31:0] VLC stream CRC checksum */
482 #define TW5864_VLC_STREAM_CRC 0x1018
484 #define TW5864_VLC_RD 0x101c
488 * 0 Read VLC Stream Memory
490 #define TW5864_VLC_RD_MEM BIT(0)
493 * 0 Read VLC Stream Memory in single mode
497 /* 0x2000 ~ 0x2ffc - H264 Stream Memory Map */
500 * VLC_STREAM_MEM[0] address: 0x2000
501 * VLC_STREAM_MEM[1] address: 0x2004
503 * VLC_STREAM_MEM[3FF] address: 0x2ffc
505 #define TW5864_VLC_STREAM_MEM_START 0x2000
506 #define TW5864_VLC_STREAM_MEM_MAX_OFFSET 0x3ff
509 /* 0x4000 ~ 0x4ffc - Audio Register Map */
510 /* [31:0] config 1ms cnt = Realtime clk/1000 */
511 #define TW5864_CFG_1MS_CNT 0x4000
513 #define TW5864_ADPCM 0x4004
516 #define TW5864_ADPCM_DEC BIT(0)
522 #define TW5864_AUD 0x4008
525 #define TW5864_AUD_ORG_CH_EN 0x00ff
529 * 0 16bit
535 * 0 PCM
538 #define TW5864_AUD_TYPE (0xf << 18)
541 * 0 8K
545 /* Channel ID used to select audio channel (0 to 16) for loopback */
547 #define TW5864_TESTLOOP_CHID (0x1f << 24)
551 * 0 Asynchronous Mode or PCI target mode
556 #define TW5864_AUD_ADPCM 0x400c
559 #define TW5864_AUD_ADPCM_CH_EN 0x00ff
563 #define TW5864_PC_BLOCK_ADPCM_RD_NO 0x4018
564 #define TW5864_PC_BLOCK_ADPCM_RD_NO_MASK 0x1f
568 * Bit[2:0] ch0
586 #define TW5864_ADPCM_ENC_XX_MASK 0x3fff
588 /* ADPCM_ENC_WR_PTR[29:0] */
589 #define TW5864_ADPCM_ENC_WR_PTR1 0x401c
591 #define TW5864_ADPCM_ENC_WR_PTR2 0x4020
593 /* ADPCM_ENC_RD_PTR[29:0] */
594 #define TW5864_ADPCM_ENC_RD_PTR1 0x4024
596 #define TW5864_ADPCM_ENC_RD_PTR2 0x4028
598 /* [3:0] rd ch0, [7:4] rd ch1, [11:8] wr ch0, [15:12] wr ch1 */
599 #define TW5864_ADPCM_DEC_RD_WR_PTR 0x402c
603 * Bit[3:0] ch0
621 /* AD_ORIG_WR_PTR[31:0] */
622 #define TW5864_AD_ORIG_WR_PTR1 0x4030
624 #define TW5864_AD_ORIG_WR_PTR2 0x4034
626 #define TW5864_AD_ORIG_WR_PTR3 0x4038
628 /* AD_ORIG_RD_PTR[31:0] */
629 #define TW5864_AD_ORIG_RD_PTR1 0x403c
631 #define TW5864_AD_ORIG_RD_PTR2 0x4040
633 #define TW5864_AD_ORIG_RD_PTR3 0x4044
635 #define TW5864_PC_BLOCK_ORIG_RD_NO 0x4048
636 #define TW5864_PC_BLOCK_ORIG_RD_NO_MASK 0x1f
638 #define TW5864_PCI_AUD 0x404c
641 * The register is applicable to PCI initiator mode only. Used to select PCM(0)
644 #define TW5864_PCI_DATA_SEL 0xffff
647 * 0 Flow control disabled. TW5864 continuously sends audio frame to PC
658 /* [1:0] CS valid to data valid CLK cycles when writing operation */
659 #define TW5864_CS2DAT_CNT 0x8000
660 /* [2:0] Data valid signal width by system clock cycles */
661 #define TW5864_DATA_VLD_WIDTH 0x8004
663 #define TW5864_SYNC 0x8008
666 * 0 vlc stream to synchronous port
671 * 0 SYNC Address sampled on Rising edge
674 #define TW5864_SYNC_ADR_EDGE BIT(0)
677 * 0 No system delay
684 * 0 Rising edge output
690 * [1:0]
693 * 2'b10 phase set to 0 degree
696 #define TW5864_I2C_PHASE_CFG 0x800c
707 /* SYSPLL_M[7:0] */
708 #define TW5864_SYSPLL1 0x8018
710 #define TW5864_SYSPLL_M_LOW 0x00ff
712 /* [2:0]: SYSPLL_M[10:8], [7:3]: SYSPLL_N[4:0] */
713 #define TW5864_SYSPLL2 0x8019
715 #define TW5864_SYSPLL_M_HI 0x07
717 #define TW5864_SYSPLL_N_LOW (0x1f << 3)
720 * [1:0]: SYSPLL_N[6:5], [3:2]: SYSPLL_P, [4]: SYSPLL_IREF, [7:5]: SYSPLL_CP_SEL
722 #define TW5864_SYSPLL3 0x8020
724 #define TW5864_SYSPLL_N_HI 0x03
726 #define TW5864_SYSPLL_P (0x03 << 2)
729 * 0 Lower current (default)
735 * 0 1,5 uA
745 #define TW5864_SYSPLL_CP_SEL (0x07 << 5)
748 * [1:0]: SYSPLL_VCO, [3:2]: SYSPLL_LP_X8, [5:4]: SYSPLL_ICP_SEL,
751 #define TW5864_SYSPLL4 0x8021
760 #define TW5864_SYSPLL_VCO 0x03
764 * 0 38.5K ohms
769 #define TW5864_SYSPLL_LP_X8 (0x03 << 2)
778 #define TW5864_SYSPLL_ICP_SEL (0x03 << 4)
781 * 0 no 5pF (default)
787 * 0 Falling edge (default)
792 /* [0]: SYSPLL_RST, [4]: SYSPLL_PD */
793 #define TW5864_SYSPLL5 0x8024
796 #define TW5864_SYSPLL_RST BIT(0)
800 #define TW5864_PLL_CFG 0x801c
807 #define TW5864_SRST BIT(0)
827 #define TW5864_SPLL 0x8028
829 /* 0x8800 ~ 0x88fc - Interrupt Register Map */
831 * Trigger mode of interrupt source 0 ~ 15
833 * 0 Level trigger mode
835 #define TW5864_TRIGGER_MODE_L 0x8800
837 #define TW5864_TRIGGER_MODE_H 0x8804
838 /* Enable of interrupt source 0 ~ 15 */
839 #define TW5864_INTR_ENABLE_L 0x8808
841 #define TW5864_INTR_ENABLE_H 0x880c
842 /* Clear interrupt command of interrupt source 0 ~ 15 */
843 #define TW5864_INTR_CLR_L 0x8810
845 #define TW5864_INTR_CLR_H 0x8814
847 * Assertion of interrupt source 0 ~ 15
849 * 0 Low level or neg-edge is assertion
851 #define TW5864_INTR_ASSERT_L 0x8818
853 #define TW5864_INTR_ASSERT_H 0x881c
857 * 0 Interrupt output is low assertion
859 #define TW5864_INTR_OUT_LEVEL 0x8820
861 * Status of interrupt source 0 ~ 15
862 * Bit[0]: VLC 4k RAM interrupt
866 * Bit[4]: gpio 0 interrupt
877 #define TW5864_INTR_STATUS_L 0x8838
880 * Bit[0]: Reserved
893 #define TW5864_INTR_STATUS_H 0x883c
896 #define TW5864_INTR_VLC_RAM BIT(0)
900 /* n belongs to [0; 7] */
912 /* 0x9000 ~ 0x920c - Video Capture (VIF) Register Map */
916 * 0 Channel Disabled
918 #define TW5864_H264EN_CH_STATUS 0x9000
920 * [15:0] H264EN_CH_EN[n] H264 Encoding Path Enable for channel
922 * 0 Channel Disabled
924 #define TW5864_H264EN_CH_EN 0x9004
929 * 0 Does not downscale
931 #define TW5864_H264EN_CH_DNS 0x9008
935 * 0 Interlaced (TW5864 default)
937 #define TW5864_H264EN_CH_PROG 0x900c
939 * [3:0] H264EN_BUS_MAX_CH[n]
941 * 0 Max 4 channels
944 #define TW5864_H264EN_BUS_MAX_CH 0x9010
950 #define TW5864_H264EN_RATE_MAX_LINE_EVEN 0x1f
952 #define TW5864_H264EN_RATE_MAX_LINE_ODD (0x1f << 5)
954 * [4:0] H264EN_RATE_MAX_LINE_0
957 #define TW5864_H264EN_RATE_MAX_LINE_REG1 0x9014
959 * [4:0] H264EN_RATE_MAX_LINE_2
962 #define TW5864_H264EN_RATE_MAX_LINE_REG2 0x9018
970 * Note: To be used with 0x9008 register to configure the frame size
973 * [1:0]: H264EN_CH0_FMT,
976 #define TW5864_H264EN_CH_FMT_REG1 0x9020
978 * [1:0]: H264EN_CH8_FMT (?),
981 #define TW5864_H264EN_CH_FMT_REG2 0x9024
987 (0x9100 + bus * 0x20 + channel * 0x08)
989 (0x9104 + bus * 0x20 + channel * 0x08)
995 #define TW5864_H264EN_BUS0_MAP 0x9200
996 #define TW5864_H264EN_BUS1_MAP 0x9204
997 #define TW5864_H264EN_BUS2_MAP 0x9208
998 #define TW5864_H264EN_BUS3_MAP 0x920c
1001 #define TW5864_UNDECLARED_ERROR_FLAGS_0x9218 0x9218
1003 #define TW5864_GPIO1 0x9800
1004 #define TW5864_GPIO2 0x9804
1007 #define TW5864_GPIO_DATA 0x00ff
1010 #define TW5864_GPIO_OEN (0xff << 8)
1012 /* 0xa000 ~ 0xa8ff - DDR Controller Register Map */
1015 * [2:0] Data valid counter after read command to DDR. This is the delay value
1019 #define TW5864_RD_ACK_VLD_MUX 0xa000
1021 #define TW5864_DDR_PERIODS 0xa004
1027 #define TW5864_TRAS_CNT_MAX 0x000f
1033 #define TW5864_RFC_CNT_MAX (0x0f << 8)
1039 #define TW5864_TCD_CNT_MAX (0x0f << 4)
1042 #define TW5864_TWR_CNT_MAX (0x0f << 12)
1045 * [2:0] CAS latency, the delay cycle between internal read command and the
1048 #define TW5864_CAS_LATENCY 0xa008
1050 * [15:0] Maximum average periodic refresh, the value is based on the current
1053 #define TW5864_DDR_REF_CNTR_MAX 0xa00c
1055 * DDR_ON_CHIP_MAP [1:0]
1056 * 0 256M DDR on board
1060 * 0 Only one DDR chip
1063 #define TW5864_DDR_ON_CHIP_MAP 0xa01c
1064 #define TW5864_DDR_SELFTEST_MODE 0xa020
1067 * 0 Common read/write mode
1070 #define TW5864_MASTER_MODE BIT(0)
1072 * 0 DDR self-test single read/write
1077 * 0 DDR self-test write command
1083 * 0 write 32'haaaa5555 to DDR
1088 #define TW5864_DATA_MODE (0x3 << 4)
1090 /* [7:0] The maximum data of one burst in DDR self-test mode */
1091 #define TW5864_BURST_CNTR_MAX 0xa024
1092 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1093 #define TW5864_DDR_PROC_CNTR_MAX_L 0xa028
1095 #define TW5864_DDR_PROC_CNTR_MAX_H 0xa02c
1096 /* [0]: Start one DDR self-test */
1097 #define TW5864_DDR_SELF_TEST_CMD 0xa030
1098 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1099 #define TW5864_ERR_CNTR_L 0xa034
1101 #define TW5864_ERR_CNTR_H_AND_FLAG 0xa038
1104 #define TW5864_ERR_CNTR_H_MASK 0x3fff
1106 #define TW5864_END_FLAG 0x8000
1109 * DDR Controller B: same as 0xa000 ~ 0xa038, but add TW5864_DDR_B_OFFSET to all
1112 #define TW5864_DDR_B_OFFSET 0x0800
1114 /* 0xb004 ~ 0xb018 - HW version/ARB12 Register Map */
1115 /* [15:0] Default is C013 */
1116 #define TW5864_HW_VERSION 0xb004
1118 #define TW5864_REQS_ENABLE 0xb010
1121 #define TW5864_AUD_DATA_IN_ENB BIT(0)
1141 #define TW5864_ARB12 0xb018
1146 #define TW5864_ARB12_TIME_OUT_CNT 0x7fff
1148 /* 0xb800 ~ 0xb80c - Indirect Access Register Map */
1157 * (1) Write IND_DATA at 0xb804 ~ 0xb807
1158 * (2) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1159 * (3) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "1", ENABLE to "1"
1161 * (1) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1162 * (2) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "0", ENABLE to "1"
1163 * (3) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1164 * (4) Read IND_DATA from 0xb804 ~ 0xb807
1166 #define TW5864_IND_CTL 0xb800
1169 #define TW5864_IND_ADDR 0x0000ffff
1170 /* Wait until this bit is "0" before using indirect access */
1177 /* [31:0] Data used to read/write indirect register space */
1178 #define TW5864_IND_DATA 0xb804
1180 /* 0xc000 ~ 0xc7fc - Preview Register Map */
1183 * [15:0] Status of Vsync Synchronized PCI_PV_CH_EN (Read Only)
1185 * 0 Channel Disabled
1187 #define TW5864_PCI_PV_CH_STATUS 0xc000
1189 * [15:0] PCI Preview Path Enable for channel n
1191 * 0 Channel Disable
1193 #define TW5864_PCI_PV_CH_EN 0xc004
1195 /* 0xc800 ~ 0xc804 - JPEG Capture Register Map */
1197 /* 0xd000 ~ 0xd0fc - JPEG Control Register Map */
1200 /* 0xe000 ~ 0xfc04 - Motion Vector Register Map */
1202 /* ME Motion Vector data (Four Byte Each) 0xe000 ~ 0xe7fc */
1203 #define TW5864_ME_MV_VEC_START 0xe000
1204 #define TW5864_ME_MV_VEC_MAX_OFFSET 0x1ff
1207 #define TW5864_MV 0xfc00
1210 #define TW5864_MV_BK0_FULL BIT(0)
1221 #define TW5864_MV_LEN (0xff << 5)
1222 /* The configured status bit written into bit 15 of 0xfc04 */
1225 #define TW5864_MPI_DDR_SEL_REG 0xfc04
1229 * 0 MV is saved in internal DPR
1234 /* 0x18000 ~ 0x181fc - PCI Master/Slave Control Map */
1235 #define TW5864_PCI_INTR_STATUS 0x18000
1254 #define TW5864_PCI_INTR_CTL 0x18004
1257 #define TW5864_PCI_MAST_ENB BIT(0)
1259 #define TW5864_MVD_VLC_MAST_ENB 0x06
1260 /* (Need to set 0 in TW5864A) */
1272 #define TW5864_AU_MAST_ENB_CHN (0xffff << 8)
1290 #define TW5864_PREV_AND_AU_INTR 0x18008
1293 #define TW5864_PREV_INTR_REG 0x0000ffff
1296 #define TW5864_AU_INTR_REG (0xffff << 16)
1298 #define TW5864_MASTER_ENB_REG 0x1800c
1316 #define TW5864_PREV_AND_AU_BUF_FLAG 0x18010
1319 #define TW5864_PREV_BUF_FLAG 0xffff
1322 #define TW5864_AUDIO_BUF_FLAG (0xffff << 16)
1324 #define TW5864_IIC 0x18014
1327 #define TW5864_IIC_DATA 0x00ff
1330 #define TW5864_IIC_REG_ADDR (0xff << 8)
1331 /* rd/wr flag rd=1,wr=0 */
1335 #define TW5864_IIC_DEV_ADDR (0x7f << 17)
1343 #define TW5864_RST_AND_IF_INFO 0x18018
1346 #define TW5864_APP_SOFT_RST BIT(0)
1349 #define TW5864_PCI_INF_VERSION (0xffff << 16)
1352 #define TW5864_VLC_CRC_REG 0x1801c
1357 #define TW5864_VLC_MAX_LENGTH 0x18020
1359 #define TW5864_VLC_LENGTH 0x18024
1361 #define TW5864_VLC_INTRA_CRC_I_REG 0x18028
1363 #define TW5864_VLC_INTRA_CRC_O_REG 0x1802c
1365 #define TW5864_VLC_PAR_CRC_REG 0x18030
1367 #define TW5864_VLC_PAR_LENGTH_REG 0x18034
1369 #define TW5864_VLC_PAR_I_REG 0x18038
1371 #define TW5864_VLC_PAR_O_REG 0x1803c
1375 * PREV_PCI_ENB_CHN[0] Enable 9th preview channel (9CIF prev) or 1D1 channel in
1379 #define TW5864_PREV_PCI_ENB_CHN 0x18040
1381 #define TW5864_PREV_FRAME_FORMAT_IN 0x18044
1383 #define TW5864_IIC_ENB 0x18048
1386 * 0 1ms
1391 #define TW5864_PCI_INTTM_SCALE 0x1804c
1400 #define TW5864_VLC_STREAM_BASE_ADDR 0x18080
1402 #define TW5864_MV_STREAM_BASE_ADDR 0x18084
1403 /* 0x180a0 ~ 0x180bc: audio burst base address. Skipped. */
1404 /* 0x180c0 ~ 0x180dc: JPEG Push Mode Buffer Base Address. Skipped. */
1405 /* 0x18100 ~ 0x1817c: preview burst base address. Skipped. */
1407 /* 0x80000 ~ 0x87fff - DDR Burst RW Register Map */
1408 #define TW5864_DDR_CTL 0x80000
1412 #define TW5864_BRST_LENGTH (0x3fff << 2)
1415 * 0 Read Burst from DDR
1438 /* [27:0] DDR Access Address. Bit [1:0] has to be 0 */
1439 #define TW5864_DDR_ADDR 0x80004
1440 /* DDR Access Internal Buffer Address. Bit [1:0] has to be 0 */
1441 #define TW5864_DPR_BUF_ADDR 0x80008
1443 #define TW5864_DPR_BUF_START 0x84000
1444 /* 0x84000 - 0x87ffc */
1445 #define TW5864_DPR_BUF_SIZE 0x4000
1449 * The indirect space is accessed through 0xb800 ~ 0xb807 registers in direct
1453 /* Allowed channel values: [0; 3] */
1455 #define TW5864_INDIR_VIN_0(channel) (0x000 + channel * 0x010)
1460 * 0 Video detected.
1465 * 0 Horizontal sync PLL is not locked.
1470 * 0 Sub-carrier PLL is not locked.
1475 * 0 Odd field is being decoded.
1480 * 0 Vertical logic is not locked.
1485 * 0 Color burst signal detected.
1489 * 0 60Hz source detected
1494 #define TW5864_INDIR_VIN_0_DET50 BIT(0)
1496 #define TW5864_INDIR_VIN_1(channel) (0x001 + channel * 0x010)
1505 * 0 = Non-standard signal
1511 * 0 = interlaced signal
1517 * 0 = None (default)
1519 * **Note: VSHP must be set to '0' if COMB = 0
1521 #define TW5864_INDIR_VIN_1_VSHP 0x07
1523 /* HDELAY_XY[7:0] */
1524 #define TW5864_INDIR_VIN_2_HDELAY_XY_LO(channel) (0x002 + channel * 0x010)
1525 /* HACTIVE_XY[7:0] */
1526 #define TW5864_INDIR_VIN_3_HACTIVE_XY_LO(channel) (0x003 + channel * 0x010)
1527 /* VDELAY_XY[7:0] */
1528 #define TW5864_INDIR_VIN_4_VDELAY_XY_LO(channel) (0x004 + channel * 0x010)
1529 /* VACTIVE_XY[7:0] */
1530 #define TW5864_INDIR_VIN_5_VACTIVE_XY_LO(channel) (0x005 + channel * 0x010)
1532 #define TW5864_INDIR_VIN_6(channel) (0x006 + channel * 0x010)
1534 #define TW5864_INDIR_VIN_6_HDELAY_XY_HI 0x03
1536 #define TW5864_INDIR_VIN_6_HACTIVE_XY_HI (0x03 << 2)
1543 * is 0x00f for NTSC and 0x00a for PAL.
1561 * purplish tone. The default value is 0o (00h). This is effective only on NTSC
1564 #define TW5864_INDIR_VIN_7_HUE(channel) (0x007 + channel * 0x010)
1566 #define TW5864_INDIR_VIN_8(channel) (0x008 + channel * 0x010)
1571 * 0 Low
1576 * 0 None
1580 #define TW5864_INDIR_VIN_8_CTI (0x03 << 4)
1584 * signals. There are 16 levels of control with "0" having no effect on the
1588 #define TW5864_INDIR_VIN_8_SHARPNESS 0x0f
1592 * gain of 1. The range adjustment is from 0% to 255% at 1% per step. The
1595 #define TW5864_INDIR_VIN_9_CNTRST(channel) (0x009 + channel * 0x010)
1599 * complement form. Positive value increases brightness. A value 0 has no
1602 #define TW5864_INDIR_VIN_A_BRIGHT(channel) (0x00a + channel * 0x010)
1609 * flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has
1612 #define TW5864_INDIR_VIN_B_SAT_U(channel) (0x00b + channel * 0x010)
1619 * flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has
1622 #define TW5864_INDIR_VIN_C_SAT_V(channel) (0x00c + channel * 0x010)
1625 #define TW5864_INDIR_VIN_D(channel) (0x00d + channel * 0x010)
1637 * 0 Type 3 color stripe protection
1639 #define TW5864_INDIR_VIN_D_CTYPE2 BIT(0)
1642 #define TW5864_INDIR_VIN_E(channel) (0x00e + channel * 0x010)
1646 * 0 Idle
1652 * 0 NTSC (M)
1662 #define TW5864_INDIR_VIN_E_STDNOW (0x07 << 4)
1666 * 0 Enable VACTIVE and HDELAY shadow registers value depending on STANDARD.
1672 * 0 NTSC (M)
1681 #define TW5864_INDIR_VIN_E_STANDARD 0x07
1683 #define TW5864_INDIR_VIN_F(channel) (0x00f + channel * 0x010)
1688 * 0 Manual initiation of auto format detection is done. (Default)
1704 #define TW5864_INDIR_VIN_F_NTSCEN BIT(0)
1709 #define TW5864_INDIR_VD_108_POL 0x041
1710 #define TW5864_INDIR_VD_108_POL_VD12 BIT(0)
1719 * 0 0.25
1736 /* [3:0] channel 0, [7:4] channel 1 */
1737 #define TW5864_INDIR_AIGAIN1 0x060
1738 /* [3:0] channel 2, [7:4] channel 3 */
1739 #define TW5864_INDIR_AIGAIN2 0x061
1743 #define TW5864_INDIR_AIN_0x06D 0x06d
1747 * 0 PCM output (default)
1753 #define TW5864_INDIR_AIN_LAWMD (0x03 << 6)
1756 * 0 Apply individual mixing ratio value for each audio (default)
1761 * Enable the mute function for audio channel AINn when n is 0 to 3. It effects
1764 * 0 Normal
1767 #define TW5864_INDIR_AIN_MIX_MUTE 0x1f
1771 #define TW5864_INDIR_AIN_0x0E3 0x0e3
1782 * 0 Not inversed (Default)
1788 * 0 Not inversed (Default)
1793 * ACKI [21:0] control automatic set up with AFMD registers
1795 * 0 ACKI [21:0] registers set up ACKI control
1801 * 0 8kHz setting (Default)
1807 #define TW5864_INDIR_AIN_0x0E3_AFMD 0x07
1809 #define TW5864_INDIR_AIN_0x0E4 0x0e4
1813 * 0 L/R half length separated output (Default).
1819 * 0 High periods is one 27MHz clock period (default).
1829 * 0 No delay
1835 * 0 no delay
1841 * 0 No delay (Default). This is for I2S type 1T delay input interface.
1843 * type 0T delay input interface.
1848 * 0 PCM input (Default)
1853 #define TW5864_INDIR_AIN_0x0E4_INLAWMD 0x03
1859 #define TW5864_INDIR_AIN_A5DETENA 0x0e5
1865 * [2:0]: REV_ID The revision number is 0h
1867 #define TW5864_INDIR_ID 0x0fe
1869 #define TW5864_INDIR_IN_PIC_WIDTH(channel) (0x200 + 4 * channel)
1870 #define TW5864_INDIR_IN_PIC_HEIGHT(channel) (0x201 + 4 * channel)
1871 #define TW5864_INDIR_OUT_PIC_WIDTH(channel) (0x202 + 4 * channel)
1872 #define TW5864_INDIR_OUT_PIC_HEIGHT(channel) (0x203 + 4 * channel)
1876 #define TW5864_INDIR_CROP_ETC 0x260
1879 #define TW5864_INDIR_CROP_ETC_CROP_EN 0x4
1884 * 15:0 Motion detection interrupt for channel 0 ~ 15
1885 * 31:16 Night detection interrupt for channel 0 ~ 15
1886 * 47:32 Blind detection interrupt for channel 0 ~ 15
1887 * 63:48 No video interrupt for channel 0 ~ 15
1888 * 79:64 Line mode underflow interrupt for channel 0 ~ 15
1889 * 95:80 Line mode overflow interrupt for channel 0 ~ 15
1891 /* 0x2d0~0x2d7: [63:0] bits */
1892 #define TW5864_INDIR_INTERRUPT1 0x2d0
1893 /* 0x2e0~0x2e3: [95:64] bits */
1894 #define TW5864_INDIR_INTERRUPT2 0x2e0
1897 * Interrupt mask register for interrupts in 0x2d0 ~ 0x2d7
1898 * 15:0 Motion detection interrupt for channel 0 ~ 15
1899 * 31:16 Night detection interrupt for channel 0 ~ 15
1900 * 47:32 Blind detection interrupt for channel 0 ~ 15
1901 * 63:48 No video interrupt for channel 0 ~ 15
1902 * 79:64 Line mode underflow interrupt for channel 0 ~ 15
1903 * 95:80 Line mode overflow interrupt for channel 0 ~ 15
1905 /* 0x2d8~0x2df: [63:0] bits */
1906 #define TW5864_INDIR_INTERRUPT_MASK1 0x2d8
1907 /* 0x2e8~0x2eb: [95:64] bits */
1908 #define TW5864_INDIR_INTERRUPT_MASK2 0x2e8
1910 /* [11:0]: Interrupt summary register for interrupts & interrupt mask from in
1911 * 0x2d0 ~ 0x2d7 and 0x2d8 ~ 0x2df
1912 * bit 0: interrupt occurs in 0x2d0 & 0x2d8
1913 * bit 1: interrupt occurs in 0x2d1 & 0x2d9
1914 * bit 2: interrupt occurs in 0x2d2 & 0x2da
1915 * bit 3: interrupt occurs in 0x2d3 & 0x2db
1916 * bit 4: interrupt occurs in 0x2d4 & 0x2dc
1917 * bit 5: interrupt occurs in 0x2d5 & 0x2dd
1918 * bit 6: interrupt occurs in 0x2d6 & 0x2de
1919 * bit 7: interrupt occurs in 0x2d7 & 0x2df
1920 * bit 8: interrupt occurs in 0x2e0 & 0x2e8
1921 * bit 9: interrupt occurs in 0x2e1 & 0x2e9
1922 * bit 10: interrupt occurs in 0x2e2 & 0x2ea
1923 * bit 11: interrupt occurs in 0x2e3 & 0x2eb
1925 #define TW5864_INDIR_INTERRUPT_SUMMARY 0x2f0
1928 /* valid value for channel is [0:15] */
1929 #define TW5864_INDIR_DETECTION_CTL0(channel) (0x300 + channel * 0x08)
1933 * 0 Enable motion and blind detection (default)
1939 * 0 None Operation (default)
1945 * 0 Automatic trigger mode of motion detection (default)
1951 * 0 Low threshold (More sensitive) (default)
1955 #define TW5864_INDIR_DETECTION_CTL0_BD_CELSENS 0x03
1957 #define TW5864_INDIR_DETECTION_CTL1(channel) (0x301 + channel * 0x08)
1961 * 0 More Sensitive (default)
1966 #define TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS (0x0f << 4)
1969 * 0 0 pixel (default)
1973 #define TW5864_INDIR_DETECTION_CTL1_MD_PIXEL_OS 0x0f
1975 #define TW5864_INDIR_DETECTION_CTL2(channel) (0x302 + channel * 0x08)
1979 * 0 Update reference field every field (default)
1985 * 0 Detecting motion for only odd field (default)
1991 #define TW5864_INDIR_DETECTION_CTL2_MD_FIELD (0x03 << 5)
1994 * 0 More sensitive (default)
1998 #define TW5864_INDIR_DETECTION_CTL2_MD_LVSENS 0x1f
2000 #define TW5864_INDIR_DETECTION_CTL3(channel) (0x303 + channel * 0x08)
2004 * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default)
2010 #define TW5864_INDIR_DETECTION_CTL3_MD_CELSENS (0x03 << 6)
2014 * In MD_DUAL_EN = 1, MD_SPEED should be limited to 0 ~ 31.
2015 * 0 1 field intervals (default)
2022 #define TW5864_INDIR_DETECTION_CTL3_MD_SPEED 0x3f
2024 #define TW5864_INDIR_DETECTION_CTL4(channel) (0x304 + channel * 0x08)
2028 * 0 More Sensitive (default)
2033 #define TW5864_INDIR_DETECTION_CTL4_MD_SPSENS (0x0f << 4)
2036 * 0 Low threshold (More sensitive) (default)
2040 #define TW5864_INDIR_DETECTION_CTL4_BD_LVSENS 0x0f
2042 #define TW5864_INDIR_DETECTION_CTL5(channel) (0x305 + channel * 0x08)
2045 * 0 Low threshold (More sensitive) (default)
2050 #define TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS (0x0f << 4)
2053 * 0 Low threshold (More sensitive) (default)
2057 #define TW5864_INDIR_DETECTION_CTL5_ND_LVSENS 0x0f
2060 * [11:0] The base address of the motion detection buffer. This address is in
2064 #define TW5864_INDIR_MD_BASE_ADDR 0x380
2068 * 0x3a0 ~ 0x3b7. Before reading back motion result, always set this first.
2070 #define TW5864_INDIR_RGR_MOTION_SEL 0x382
2072 /* [15:0] MD strobe has been performed at channel n (read only) */
2073 #define TW5864_INDIR_MD_STRB 0x386
2075 #define TW5864_INDIR_NOVID_DET 0x388
2077 #define TW5864_INDIR_MD_DET 0x38a
2079 #define TW5864_INDIR_BD_DET 0x38c
2081 #define TW5864_INDIR_ND_DET 0x38e
2083 /* 192 bit motion flag of the channel specified by RGR_MOTION_SEL in 0x382 */
2084 #define TW5864_INDIR_MOTION_FLAG 0x3a0
2088 * [9:0] The motion cell count of a specific channel selected by 0x382. This is
2091 #define TW5864_INDIR_MD_DI_CNT 0x3b8
2093 #define TW5864_INDIR_MD_DI_CELLSENS 0x3ba
2095 #define TW5864_INDIR_MD_DI_LVSENS 0x3bb
2097 /* 192 bit motion mask of the channel specified by MASK_CH_SEL in 0x3fe */
2098 #define TW5864_INDIR_MOTION_MASK 0x3e0
2101 /* [4:0] The channel selection to access masks in 0x3e0 ~ 0x3f7 */
2102 #define TW5864_INDIR_MASK_CH_SEL 0x3fe
2107 #define TW5864_INDIR_DDRA_DLL_DQS_SEL0 0xee6
2108 #define TW5864_INDIR_DDRA_DLL_DQS_SEL1 0xee7
2109 #define TW5864_INDIR_DDRA_DLL_CLK90_SEL 0xee8
2110 #define TW5864_INDIR_DDRA_DLL_TEST_SEL_AND_TAP_S 0xee9
2112 #define TW5864_INDIR_DDRB_DLL_DQS_SEL0 0xeeb
2113 #define TW5864_INDIR_DDRB_DLL_DQS_SEL1 0xeec
2114 #define TW5864_INDIR_DDRB_DLL_CLK90_SEL 0xeed
2115 #define TW5864_INDIR_DDRB_DLL_TEST_SEL_AND_TAP_S 0xeee
2117 #define TW5864_INDIR_RESET 0xef0
2122 #define TW5864_INDIR_PV_VD_CK_POL 0xefd
2126 #define TW5864_INDIR_CLK0_SEL 0xefe
2127 #define TW5864_INDIR_CLK0_SEL_VD_SHIFT 0
2128 #define TW5864_INDIR_CLK0_SEL_VD_MASK 0x3
2130 #define TW5864_INDIR_CLK0_SEL_PV_MASK (0x3 << 2)
2132 #define TW5864_INDIR_CLK0_SEL_PV2_MASK (0x3 << 4)