Lines Matching refs:SYSTEM_CONTROL_REG_BASE
32 #define SYSTEM_CONTROL_REG_BASE 0x0880 macro
71 #define MUX_MODE_CTRL (SYSTEM_CONTROL_REG_BASE + 0x00)
87 #define INTERNAL_RST (SYSTEM_CONTROL_REG_BASE + 0x04)
88 #define PERIPHERAL_CTRL (SYSTEM_CONTROL_REG_BASE + 0x08)
89 #define GPIO_0to7_CTRL (SYSTEM_CONTROL_REG_BASE + 0x0C)
90 #define GPIO_8to15_CTRL (SYSTEM_CONTROL_REG_BASE + 0x10)
91 #define GPIO_16to24_CTRL (SYSTEM_CONTROL_REG_BASE + 0x14)
92 #define GPIO_INT_SRC_CFG (SYSTEM_CONTROL_REG_BASE + 0x18)
93 #define SYS_BUF_STATUS (SYSTEM_CONTROL_REG_BASE + 0x1C)
94 #define PCIE_IP_REG_ACS (SYSTEM_CONTROL_REG_BASE + 0x20)
95 #define PCIE_IP_REG_ACS_ADDR (SYSTEM_CONTROL_REG_BASE + 0x24)
96 #define PCIE_IP_REG_ACS_DATA (SYSTEM_CONTROL_REG_BASE + 0x28)