1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2013--2024 Intel Corporation
13 #include "ipu6-bus.h"
14 #include "ipu6-isys.h"
15 #include "ipu6-platform-isys-csi2-reg.h"
31  * - req: 0 for read, 1 for write
32  * - 12 bits address
33  * - 8bits data (will ignore for read)
34  * --24----16------4-----0
35  * --|-data-|-addr-|-req-|
66 	struct device *dev = &isys->adev->auxdev.dev;  in dwc_dphy_write()
67 	void __iomem *isys_base = isys->pdata->base;  in dwc_dphy_write()
70 	dev_dbg(dev, "write: reg 0x%lx = data 0x%x", base + addr - isys_base,  in dwc_dphy_write()
77 	struct device *dev = &isys->adev->auxdev.dev;  in dwc_dphy_read()
78 	void __iomem *isys_base = isys->pdata->base;  in dwc_dphy_read()
83 	dev_dbg(dev, "read: reg 0x%lx = data 0x%x", base + addr - isys_base,  in dwc_dphy_read()
95 	mask = (1 << width) - 1;  in dwc_dphy_write_mask()
108 	return val & ((1 << width) - 1);  in dwc_dphy_read_mask()
115 	struct device *dev = &isys->adev->auxdev.dev;  in dwc_dphy_ifc_read()
116 	void __iomem *isys_base = isys->pdata->base;  in dwc_dphy_ifc_read()
142 	struct device *dev = &isys->adev->auxdev.dev;  in dwc_dphy_ifc_write()
143 	void __iomem *isys_base = isys->pdata->base;  in dwc_dphy_ifc_write()
171 	mask = (1 << width) - 1;  in dwc_dphy_ifc_write_mask()
187 	return ((val >> shift) & ((1 << width) - 1));  in dwc_dphy_ifc_read_mask()
192 	struct device *dev = &isys->adev->auxdev.dev;  in dwc_dphy_pwr_up()
266 	{0x2c,	1414,	1588,	1500,	335},
274 	{0x2f,	1794,	2008,	1900,	255},
293 	while (i--) {  in get_hsfreq_by_mbps()
305 	struct ipu6_bus_device *adev = isys->adev;  in ipu6_isys_dwc_phy_config()
306 	struct device *dev = &adev->auxdev.dev;  in ipu6_isys_dwc_phy_config()
307 	struct ipu6_device *isp = adev->isp;  in ipu6_isys_dwc_phy_config()
317 		return -EINVAL;  in ipu6_isys_dwc_phy_config()
324 	if (isys->phy_termcal_val) {  in ipu6_isys_dwc_phy_config()
328 					isys->phy_termcal_val, 4, 4);  in ipu6_isys_dwc_phy_config()
353 	 * Set cfgclkfreqrange[5:0] = round[(Fcfg_clk(MHz)-17)*4]  in ipu6_isys_dwc_phy_config()
354 	 * (38.4 - 17) * 4 = ~85 (0x55)  in ipu6_isys_dwc_phy_config()
356 	cfg_clk_freqrange = (isp->buttress.ref_clk - 170) * 4 / 10;  in ipu6_isys_dwc_phy_config()
358 		isp->buttress.ref_clk, cfg_clk_freqrange);  in ipu6_isys_dwc_phy_config()
396 	/* Turn off slave PHY LP-RX clk lane */  in ipu6_isys_dwc_phy_aggr_setup()
404 	struct device *dev = &isys->adev->auxdev.dev;  in ipu6_isys_dwc_phy_powerup_ack()
420 	if (phy_id != PHY_E || isys->phy_termcal_val)  in ipu6_isys_dwc_phy_powerup_ack()
426 		isys->phy_termcal_val = dwc_dphy_ifc_read_mask(isys, phy_id,  in ipu6_isys_dwc_phy_powerup_ack()
429 			isys->phy_termcal_val);  in ipu6_isys_dwc_phy_powerup_ack()
437 	dev_dbg(&isys->adev->auxdev.dev, "Reset phy %u", phy_id);  in ipu6_isys_dwc_phy_reset()
452 	struct device *dev = &isys->adev->auxdev.dev;  in ipu6_isys_dwc_phy_set_power()
453 	void __iomem *isys_base = isys->pdata->base;  in ipu6_isys_dwc_phy_set_power()
459 	port = cfg->port;  in ipu6_isys_dwc_phy_set_power()
461 	if (!isys_base || port >= isys->pdata->ipdata->csi2.nports) {  in ipu6_isys_dwc_phy_set_power()
463 		return -EINVAL;  in ipu6_isys_dwc_phy_set_power()
466 	nlanes = cfg->nlanes;  in ipu6_isys_dwc_phy_set_power()
469 		dev_err(dev, "invalid csi-port %u with %u lanes\n", port,  in ipu6_isys_dwc_phy_set_power()
471 		return -EINVAL;  in ipu6_isys_dwc_phy_set_power()
474 	link_freq = ipu6_isys_csi2_get_link_freq(&isys->csi2[port]);  in ipu6_isys_dwc_phy_set_power()
510 		dev_dbg(dev, "config phy %u with %u lanes in non-aggr mode\n",  in ipu6_isys_dwc_phy_set_power()