17 #define IPU6_DWC_DPHY_BASE(i)			(0x238038 + 0x34 * (i))
18 #define IPU6_DWC_DPHY_RSTZ			0x00
19 #define IPU6_DWC_DPHY_SHUTDOWNZ			0x04
20 #define IPU6_DWC_DPHY_HSFREQRANGE		0x08
21 #define IPU6_DWC_DPHY_CFGCLKFREQRANGE		0x0c
22 #define IPU6_DWC_DPHY_TEST_IFC_ACCESS_MODE	0x10
23 #define IPU6_DWC_DPHY_TEST_IFC_REQ		0x14
24 #define IPU6_DWC_DPHY_TEST_IFC_REQ_COMPLETION	0x18
25 #define IPU6_DWC_DPHY_DFT_CTRL0			0x28
26 #define IPU6_DWC_DPHY_DFT_CTRL1			0x2c
27 #define IPU6_DWC_DPHY_DFT_CTRL2			0x30
31  * - req: 0 for read, 1 for write
34  * --24----16------4-----0
39 				  FIELD_PREP(GENMASK(1, 0), req))
41 #define TEST_IFC_REQ_READ	0
45 #define TEST_IFC_ACCESS_MODE_FSM	0
49 	PHY_FSM_STATE_POWERON = 0,
70 	dev_dbg(dev, "write: reg 0x%lx = data 0x%x", base + addr - isys_base,  in dwc_dphy_write()
83 	dev_dbg(dev, "read: reg 0x%lx = data 0x%x", base + addr - isys_base,  in dwc_dphy_read()
123 		       IFC_REQ(TEST_IFC_REQ_READ, addr, 0));  in dwc_dphy_ifc_read()
125 	ret = readl_poll_timeout(reg, completion, !(completion & BIT(0)),  in dwc_dphy_ifc_read()
132 	*val = completion >> 8 & 0xff;  in dwc_dphy_ifc_read()
134 	dev_dbg(dev, "DWC ifc read 0x%x = 0x%x", addr, *val);  in dwc_dphy_ifc_read()
136 	return 0;  in dwc_dphy_ifc_read()
153 	ret = readl_poll_timeout(reg, completion, !(completion & BIT(0)),  in dwc_dphy_ifc_write()
185 		return 0;  in dwc_dphy_ifc_read_mask()
204 				phy_id, 0x1e, 0, 4);  in dwc_dphy_pwr_up()
207 		dev_err(dev, "Dphy %d power up failed, state 0x%x", phy_id,  in dwc_dphy_pwr_up()
222 #define DPHY_FREQ_RANGE_INVALID_INDEX	(0xff)
224 	{0x00,	80,	97,	80,	335},
225 	{0x10,	80,	107,	90,	335},
226 	{0x20,	84,	118,	100,	335},
227 	{0x30,	93,	128,	110,	335},
228 	{0x01,	103,	139,	120,	335},
229 	{0x11,	112,	149,	130,	335},
230 	{0x21,	122,	160,	140,	335},
231 	{0x31,	131,	170,	150,	335},
232 	{0x02,	141,	181,	160,	335},
233 	{0x12,	150,	191,	170,	335},
234 	{0x22,	160,	202,	180,	335},
235 	{0x32,	169,	212,	190,	335},
236 	{0x03,	183,	228,	205,	335},
237 	{0x13,	198,	244,	220,	335},
238 	{0x23,	212,	259,	235,	335},
239 	{0x33,	226,	275,	250,	335},
240 	{0x04,	250,	301,	275,	335},
241 	{0x14,	274,	328,	300,	335},
242 	{0x25,	297,	354,	325,	335},
243 	{0x35,	321,	380,	350,	335},
244 	{0x05,	369,	433,	400,	335},
245 	{0x16,	416,	485,	450,	335},
246 	{0x26,	464,	538,	500,	335},
247 	{0x37,	511,	590,	550,	335},
248 	{0x07,	559,	643,	600,	335},
249 	{0x18,	606,	695,	650,	335},
250 	{0x28,	654,	748,	700,	335},
251 	{0x39,	701,	800,	750,	335},
252 	{0x09,	749,	853,	800,	335},
253 	{0x19,	796,	905,	850,	335},
254 	{0x29,	844,	958,	900,	335},
255 	{0x3a,	891,	1010,	950,	335},
256 	{0x0a,	939,	1063,	1000,	335},
257 	{0x1a,	986,	1115,	1050,	335},
258 	{0x2a,	1034,	1168,	1100,	335},
259 	{0x3b,	1081,	1220,	1150,	335},
260 	{0x0b,	1129,	1273,	1200,	335},
261 	{0x1b,	1176,	1325,	1250,	335},
262 	{0x2b,	1224,	1378,	1300,	335},
263 	{0x3c,	1271,	1430,	1350,	335},
264 	{0x0c,	1319,	1483,	1400,	335},
265 	{0x1c,	1366,	1535,	1450,	335},
266 	{0x2c,	1414,	1588,	1500,	335},
267 	{0x3d,	1461,	1640,	1550,	208},
268 	{0x0d,	1509,	1693,	1600,	214},
269 	{0x1d,	1556,	1745,	1650,	221},
270 	{0x2e,	1604,	1798,	1700,	228},
271 	{0x3e,	1651,	1850,	1750,	234},
272 	{0x0e,	1699,	1903,	1800,	241},
273 	{0x1e,	1746,	1955,	1850,	248},
274 	{0x2f,	1794,	2008,	1900,	255},
275 	{0x3f,	1841,	2060,	1950,	261},
276 	{0x0f,	1889,	2113,	2000,	268},
277 	{0x40,	1936,	2165,	2050,	275},
278 	{0x41,	1984,	2218,	2100,	281},
279 	{0x42,	2031,	2270,	2150,	288},
280 	{0x43,	2079,	2323,	2200,	294},
281 	{0x44,	2126,	2375,	2250,	302},
282 	{0x45,	2174,	2428,	2300,	308},
283 	{0x46,	2221,	2480,	2350,	315},
284 	{0x47,	2269,	2500,	2400,	321},
285 	{0x48,	2316,	2500,	2450,	328},
286 	{0x49,	2364,	2500,	2500,	335}
321 			    freqranges[index].hsfreq, 0, 7);  in ipu6_isys_dwc_phy_config()
325 		dwc_dphy_ifc_write_mask(isys, phy_id, 0x20a, 0x1, 0, 1);  in ipu6_isys_dwc_phy_config()
326 		dwc_dphy_ifc_write_mask(isys, phy_id, 0x209, 0x3, 0, 2);  in ipu6_isys_dwc_phy_config()
327 		dwc_dphy_ifc_write_mask(isys, phy_id, 0x209,  in ipu6_isys_dwc_phy_config()
333 	 * frequency on bit 0 of register 0xe4  in ipu6_isys_dwc_phy_config()
335 	dwc_dphy_ifc_write_mask(isys, phy_id, 0xe4, 0x1, 0, 1);  in ipu6_isys_dwc_phy_config()
337 	 * configure registers 0xe2, 0xe3 with the  in ipu6_isys_dwc_phy_config()
339 	 * 0x1cc(460)  in ipu6_isys_dwc_phy_config()
342 	dwc_dphy_ifc_write_mask(isys, phy_id, 0xe2,  in ipu6_isys_dwc_phy_config()
343 				osc_freq_target & 0xff, 0, 8);  in ipu6_isys_dwc_phy_config()
344 	dwc_dphy_ifc_write_mask(isys, phy_id, 0xe3,  in ipu6_isys_dwc_phy_config()
345 				(osc_freq_target >> 8) & 0xf, 0, 4);  in ipu6_isys_dwc_phy_config()
349 		dwc_dphy_ifc_write_mask(isys, phy_id, 0x8, 0x1, 5, 1);  in ipu6_isys_dwc_phy_config()
353 	 * Set cfgclkfreqrange[5:0] = round[(Fcfg_clk(MHz)-17)*4]  in ipu6_isys_dwc_phy_config()
354 	 * (38.4 - 17) * 4 = ~85 (0x55)  in ipu6_isys_dwc_phy_config()
360 			    cfg_clk_freqrange, 0, 8);  in ipu6_isys_dwc_phy_config()
362 	dwc_dphy_write_mask(isys, phy_id, IPU6_DWC_DPHY_DFT_CTRL2, 0x1, 4, 1);  in ipu6_isys_dwc_phy_config()
363 	dwc_dphy_write_mask(isys, phy_id, IPU6_DWC_DPHY_DFT_CTRL2, 0x1, 8, 1);  in ipu6_isys_dwc_phy_config()
365 	return 0;  in ipu6_isys_dwc_phy_config()
372 	dwc_dphy_ifc_write_mask(isys, master, 0x133, 0x1, 0, 1);  in ipu6_isys_dwc_phy_aggr_setup()
373 	dwc_dphy_ifc_write_mask(isys, slave, 0x133, 0x0, 0, 1);  in ipu6_isys_dwc_phy_aggr_setup()
376 	dwc_dphy_ifc_write_mask(isys, master, 0x307, 0x1, 2, 1);  in ipu6_isys_dwc_phy_aggr_setup()
377 	dwc_dphy_ifc_write_mask(isys, slave, 0x307, 0x0, 2, 1);  in ipu6_isys_dwc_phy_aggr_setup()
380 	dwc_dphy_ifc_write_mask(isys, master, 0x508, 0x1, 5, 1);  in ipu6_isys_dwc_phy_aggr_setup()
381 	dwc_dphy_ifc_write_mask(isys, slave, 0x508, 0x1, 5, 1);  in ipu6_isys_dwc_phy_aggr_setup()
382 	dwc_dphy_ifc_write_mask(isys, master, 0x708, 0x1, 5, 1);  in ipu6_isys_dwc_phy_aggr_setup()
383 	dwc_dphy_ifc_write_mask(isys, slave, 0x708, 0x1, 5, 1);  in ipu6_isys_dwc_phy_aggr_setup()
386 	dwc_dphy_ifc_write_mask(isys, master, 0x308, 0x0, 3, 1);  in ipu6_isys_dwc_phy_aggr_setup()
387 	dwc_dphy_ifc_write_mask(isys, slave, 0x308, 0x1, 3, 1);  in ipu6_isys_dwc_phy_aggr_setup()
390 	dwc_dphy_ifc_write_mask(isys, slave, 0xe0, 0x3, 0, 2);  in ipu6_isys_dwc_phy_aggr_setup()
393 	dwc_dphy_ifc_write_mask(isys, slave, 0xe1, 0x1, 1, 1);  in ipu6_isys_dwc_phy_aggr_setup()
394 	dwc_dphy_ifc_write_mask(isys, slave, 0x307, 0x1, 3, 1);  in ipu6_isys_dwc_phy_aggr_setup()
397 	dwc_dphy_ifc_write_mask(isys, slave, 0x304, 0x1, 7, 1);  in ipu6_isys_dwc_phy_aggr_setup()
398 	dwc_dphy_ifc_write_mask(isys, slave, 0x305, 0xa, 0, 5);  in ipu6_isys_dwc_phy_aggr_setup()
409 	if (ret != 0) {  in ipu6_isys_dwc_phy_powerup_ack()
415 	dwc_dphy_write_mask(isys, phy_id, IPU6_DWC_DPHY_DFT_CTRL2, 0, 4, 1);  in ipu6_isys_dwc_phy_powerup_ack()
416 	dwc_dphy_write_mask(isys, phy_id, IPU6_DWC_DPHY_DFT_CTRL2, 0, 8, 1);  in ipu6_isys_dwc_phy_powerup_ack()
421 		return 0;  in ipu6_isys_dwc_phy_powerup_ack()
424 	rescal_done = dwc_dphy_ifc_read_mask(isys, phy_id, 0x221, 7, 1);  in ipu6_isys_dwc_phy_powerup_ack()
427 							       0x220, 2, 4);  in ipu6_isys_dwc_phy_powerup_ack()
432 	return 0;  in ipu6_isys_dwc_phy_powerup_ack()
439 	dwc_dphy_write(isys, phy_id, IPU6_DWC_DPHY_SHUTDOWNZ, 0);  in ipu6_isys_dwc_phy_reset()
440 	dwc_dphy_write(isys, phy_id, IPU6_DWC_DPHY_RSTZ, 0);  in ipu6_isys_dwc_phy_reset()
467 	/* only port 0, 2 and 4 support 4 lanes */  in ipu6_isys_dwc_phy_set_power()
475 	if (link_freq < 0) {  in ipu6_isys_dwc_phy_set_power()
528 		return 0;  in ipu6_isys_dwc_phy_set_power()
535 	return 0;  in ipu6_isys_dwc_phy_set_power()