Lines Matching +full:audio +full:- +full:video
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * cx88x-hw.h - CX2388x register offsets
5 * Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)
71 #define MO_VID_INTMSK 0x200050 // Video interrupt mask
72 #define MO_VID_INTSTAT 0x200054 // Video interrupt status
73 #define MO_VID_INTMSTAT 0x200058 // Video interrupt masked status
74 #define MO_VID_INTSSTAT 0x20005C // Video interrupt set status
75 #define MO_AUD_INTMSK 0x200060 // Audio interrupt mask
76 #define MO_AUD_INTSTAT 0x200064 // Audio interrupt status
77 #define MO_AUD_INTMSTAT 0x200068 // Audio interrupt masked status
78 #define MO_AUD_INTSSTAT 0x20006C // Audio interrupt set status
92 // DMA Channels 1-6 belong to SPIPE
96 // DMA Channels 9-20 belong to SPIPE
150 * Video registers
153 #define MO_VIDY_DMA 0x310000 // {64}RWp Video Y
154 #define MO_VIDU_DMA 0x310008 // {64}RWp Video U
155 #define MO_VIDV_DMA 0x310010 // {64}RWp Video V
198 #define MO_VIDY_GPCNT 0x31C020 // {16}RO Video Y general purpose counter
199 #define MO_VIDU_GPCNT 0x31C024 // {16}RO Video U general purpose counter
200 #define MO_VIDV_GPCNT 0x31C028 // {16}RO Video V general purpose counter
202 #define MO_VIDY_GPCNTRL 0x31C030 // {2}WO Video Y general purpose control
203 #define MO_VIDU_GPCNTRL 0x31C034 // {2}WO Video U general purpose control
204 #define MO_VIDV_GPCNTRL 0x31C038 // {2}WO Video V general purpose control
206 #define MO_VID_DMACNTRL 0x31C040 // {8}RW Video DMA control
207 #define MO_VID_XFR_STAT 0x31C044 // {1}RO Video transfer status
210 * audio registers
213 #define MO_AUDD_DMA 0x320000 // {64}RWp Audio downstream
214 #define MO_AUDU_DMA 0x320008 // {64}RWp Audio upstream
215 #define MO_AUDR_DMA 0x320010 // {64}RWp Audio RDS (downstream)
216 #define MO_AUDD_GPCNT 0x32C020 // {16}RO Audio down general purpose counter
217 #define MO_AUDU_GPCNT 0x32C024 // {16}RO Audio up general purpose counter
218 #define MO_AUDR_GPCNT 0x32C028 // {16}RO Audio RDS general purpose counter
219 #define MO_AUDD_GPCNTRL 0x32C030 // {2}WO Audio down general purpose control
220 #define MO_AUDU_GPCNTRL 0x32C034 // {2}WO Audio up general purpose control
221 #define MO_AUDR_GPCNTRL 0x32C038 // {2}WO Audio RDS general purpose control
222 #define MO_AUD_DMACNTRL 0x32C040 // {6}RW Audio DMA control
223 #define MO_AUD_XFR_STAT 0x32C044 // {1}RO Audio transfer status
224 #define MO_AUDD_LNGTH 0x32C048 // {12}RW Audio down line length
225 #define MO_AUDR_LNGTH 0x32C04C // {12}RW Audio RDS line length
421 // Audio QAM Register Addresses
482 #define MO_M2M_XSUM 0x35C028 // {32}RO M2M XOR-Checksum
528 #define MO_GPHST_MUX16 0x380064 // Host muxed 16-bit transfer parameters
661 // Video