Lines Matching +full:200 +full:mhz

223 	 *	4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz  in cx18_init_power()
239 	 * crystal value at all, it will assume 28.636360 MHz, the crystal  in cx18_init_power()
242 	 *	xtal_freq = 28.636360 MHz  in cx18_init_power()
247 	 * Below I aim to run the PLLs' VCOs near 400 MHz to minimize errors.  in cx18_init_power()
254 	/* the fast clock is at 200/245 MHz */  in cx18_init_power()
255 	/* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/  in cx18_init_power()
256 	/* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/  in cx18_init_power()
265 	/* set slow clock to 125/120 MHz */  in cx18_init_power()
266 	/* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */  in cx18_init_power()
267 	/* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */  in cx18_init_power()
273 	/* mpeg clock pll 54MHz */  in cx18_init_power()
274 	/* xtal_freq * 0xf.15f17f0 / 8 = 54 MHz: 432 MHz before post-divide */  in cx18_init_power()
290 	/* SER = 54MHz */  in cx18_init_power()
415 	cx18_msleep_timeout(200, 0);  in cx18_firmware_init()