17 #define CX18_PROC_SOFT_RESET		0xc70010
18 #define CX18_DDR_SOFT_RESET		0xc70014
19 #define CX18_CLOCK_SELECT1		0xc71000
20 #define CX18_CLOCK_SELECT2		0xc71004
21 #define CX18_HALF_CLOCK_SELECT1		0xc71008
22 #define CX18_HALF_CLOCK_SELECT2		0xc7100C
23 #define CX18_CLOCK_POLARITY1		0xc71010
24 #define CX18_CLOCK_POLARITY2		0xc71014
25 #define CX18_ADD_DELAY_ENABLE1		0xc71018
26 #define CX18_ADD_DELAY_ENABLE2		0xc7101C
27 #define CX18_CLOCK_ENABLE1		0xc71020
28 #define CX18_CLOCK_ENABLE2		0xc71024
30 #define CX18_REG_BUS_TIMEOUT_EN		0xc72024
32 #define CX18_FAST_CLOCK_PLL_INT		0xc78000
33 #define CX18_FAST_CLOCK_PLL_FRAC	0xc78004
34 #define CX18_FAST_CLOCK_PLL_POST	0xc78008
35 #define CX18_FAST_CLOCK_PLL_PRESCALE	0xc7800C
36 #define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010
38 #define CX18_SLOW_CLOCK_PLL_INT		0xc78014
39 #define CX18_SLOW_CLOCK_PLL_FRAC	0xc78018
40 #define CX18_SLOW_CLOCK_PLL_POST	0xc7801C
41 #define CX18_MPEG_CLOCK_PLL_INT		0xc78040
42 #define CX18_MPEG_CLOCK_PLL_FRAC	0xc78044
43 #define CX18_MPEG_CLOCK_PLL_POST	0xc78048
44 #define CX18_PLL_POWER_DOWN		0xc78088
45 #define CX18_SW1_INT_STATUS             0xc73104
46 #define CX18_SW1_INT_ENABLE_PCI         0xc7311C
47 #define CX18_SW2_INT_SET                0xc73140
48 #define CX18_SW2_INT_STATUS             0xc73144
49 #define CX18_ADEC_CONTROL		0xc78120
51 #define CX18_DDR_REQUEST_ENABLE		0xc80000
52 #define CX18_DDR_CHIP_CONFIG		0xc80004
53 #define CX18_DDR_REFRESH		0xc80008
54 #define CX18_DDR_TIMING1		0xc8000C
55 #define CX18_DDR_TIMING2		0xc80010
56 #define CX18_DDR_POWER_REG		0xc8001C
58 #define CX18_DDR_TUNE_LANE		0xc80048
59 #define CX18_DDR_INITIAL_EMRS		0xc80054
60 #define CX18_DDR_MB_PER_ROW_7		0xc8009C
61 #define CX18_DDR_BASE_63_ADDR		0xc804FC
63 #define CX18_WMB_CLIENT02		0xc90108
64 #define CX18_WMB_CLIENT05		0xc90114
65 #define CX18_WMB_CLIENT06		0xc90118
66 #define CX18_WMB_CLIENT07		0xc9011C
67 #define CX18_WMB_CLIENT08		0xc90120
68 #define CX18_WMB_CLIENT09		0xc90124
69 #define CX18_WMB_CLIENT10		0xc90128
70 #define CX18_WMB_CLIENT11		0xc9012C
71 #define CX18_WMB_CLIENT12		0xc90130
72 #define CX18_WMB_CLIENT13		0xc90134
73 #define CX18_WMB_CLIENT14		0xc90138
75 #define CX18_DSP0_INTERRUPT_MASK	0xd0004C
77 #define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */
78 #define APU_ROM_SYNC2 0x72646548 /* "rdeH" */
103 	for (i = 0; i < fw->size; i += 4096) {  in load_cpu_fw_direct()
111 				cx18_setup_page(cx, 0);  in load_cpu_fw_direct()
135 	u32 offset = 0;  in load_apu_fw_direct()
136 	u32 apu_version = 0;  in load_apu_fw_direct()
142 		cx18_setup_page(cx, 0);  in load_apu_fw_direct()
146 	*entry_addr = 0;  in load_apu_fw_direct()
151 	apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];  in load_apu_fw_direct()
155 		seghdr.sync1 = le32_to_cpu(shptr[0]);  in load_apu_fw_direct()
168 		if (*entry_addr == 0)  in load_apu_fw_direct()
172 		for (i = 0; i < seghdr.size; i += 4096) {  in load_apu_fw_direct()
183 					cx18_setup_page(cx, 0);  in load_apu_fw_direct()
195 	cx18_setup_page(cx, 0);  in load_apu_fw_direct()
202 	cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,  in cx18_halt_firmware()
203 				  0x0000000F, 0x000F000F);  in cx18_halt_firmware()
204 	cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL,  in cx18_halt_firmware()
205 				  0x00000002, 0x00020002);  in cx18_halt_firmware()
212 	cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN);  in cx18_init_power()
215 	cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL,  in cx18_init_power()
216 				  0x00000000, 0x00020002);  in cx18_init_power()
255 	/* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/  in cx18_init_power()
256 	/* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/  in cx18_init_power()
257 	cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);  in cx18_init_power()
258 	cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,  in cx18_init_power()
266 	/* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */  in cx18_init_power()
267 	/* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */  in cx18_init_power()
268 	cx18_write_reg(cx, lowpwr ? 0xD : 0xC, CX18_SLOW_CLOCK_PLL_INT);  in cx18_init_power()
269 	cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F,  in cx18_init_power()
274 	/* xtal_freq * 0xf.15f17f0 / 8 = 54 MHz: 432 MHz before post-divide */  in cx18_init_power()
275 	cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);  in cx18_init_power()
276 	cx18_write_reg(cx, 0x2BE2FE, CX18_MPEG_CLOCK_PLL_FRAC);  in cx18_init_power()
295 		cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1,  in cx18_init_power()
296 					  0x00000020, 0xFFFFFFFF);  in cx18_init_power()
297 		cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2,  in cx18_init_power()
298 					  0x00000004, 0xFFFFFFFF);  in cx18_init_power()
301 		cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1,  in cx18_init_power()
302 					  0x00000004, 0x00060006);  in cx18_init_power()
303 		cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2,  in cx18_init_power()
304 					  0x00000006, 0x00060006);  in cx18_init_power()
307 	cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1,  in cx18_init_power()
308 				  0x00000002, 0xFFFFFFFF);  in cx18_init_power()
309 	cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2,  in cx18_init_power()
310 				  0x00000104, 0xFFFFFFFF);  in cx18_init_power()
311 	cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1,  in cx18_init_power()
312 				  0x00009026, 0xFFFFFFFF);  in cx18_init_power()
313 	cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2,  in cx18_init_power()
314 				  0x00003105, 0xFFFFFFFF);  in cx18_init_power()
319 	cx18_msleep_timeout(10, 0);  in cx18_init_memory()
320 	cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET,  in cx18_init_memory()
321 				  0x00000000, 0x00010001);  in cx18_init_memory()
322 	cx18_msleep_timeout(10, 0);  in cx18_init_memory()
326 	cx18_msleep_timeout(10, 0);  in cx18_init_memory()
332 	cx18_msleep_timeout(10, 0);  in cx18_init_memory()
338 	cx18_msleep_timeout(10, 0);  in cx18_init_memory()
340 	cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET,  in cx18_init_memory()
341 				  0x00000000, 0x00020002);  in cx18_init_memory()
342 	cx18_msleep_timeout(10, 0);  in cx18_init_memory()
345 	cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG);  in cx18_init_memory()
347 	cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN,  in cx18_init_memory()
348 				  0x00000001, 0x00010001);  in cx18_init_memory()
350 	cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7);  in cx18_init_memory()
351 	cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR);  in cx18_init_memory()
353 	cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02);  /* AO */  in cx18_init_memory()
354 	cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09);  /* AI2 */  in cx18_init_memory()
355 	cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05);  /* VIM1 */  in cx18_init_memory()
356 	cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06);  /* AI1 */  in cx18_init_memory()
357 	cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07);  /* 3D comb */  in cx18_init_memory()
358 	cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10);  /* ME */  in cx18_init_memory()
359 	cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12);  /* ENC */  in cx18_init_memory()
360 	cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13);  /* PK */  in cx18_init_memory()
361 	cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11);  /* RC */  in cx18_init_memory()
362 	cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14);  /* AVO */  in cx18_init_memory()
375 	cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK);  in cx18_firmware_init()
378 	cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,  in cx18_firmware_init()
379 				  0x0000000F, 0x000F000F);  in cx18_firmware_init()
381 	cx18_msleep_timeout(1, 0);  in cx18_firmware_init()
384 	if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) == 0) {  in cx18_firmware_init()
393 	if (sz <= 0)  in cx18_firmware_init()
399 	fw_entry_addr = 0;  in cx18_firmware_init()
402 	if (sz <= 0)  in cx18_firmware_init()
406 	cx18_write_reg_expect(cx, 0x00080000, CX18_PROC_SOFT_RESET,  in cx18_firmware_init()
407 				  0x00000000, 0x00080008);  in cx18_firmware_init()
410 	for (retries = 0;  in cx18_firmware_init()
413 		cx18_msleep_timeout(10, 0);  in cx18_firmware_init()
415 	cx18_msleep_timeout(200, 0);  in cx18_firmware_init()
435 	sz = cx18_vapi_result(cx, api_args, CX18_CPU_DEBUG_PEEK32, 1, 0);  in cx18_firmware_init()
436 	if (sz < 0)  in cx18_firmware_init()
440 	cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400);  in cx18_firmware_init()
441 	return 0;  in cx18_firmware_init()