Lines Matching +full:384 +full:mhz
25 * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz in set_audclk_freq()
41 * crystal value at all, it will assume 28.636360 MHz, the crystal in set_audclk_freq()
44 * xtal_freq = 28.636360 MHz in set_audclk_freq()
49 * Below I aim to run the PLLs' VCOs near 400 MHz to minimize error. in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
82 /* AUD_COUNT = 0x2fff = 8 samples * 4 * 384 - 1 */ in set_audclk_freq()
101 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
105 /* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/ in set_audclk_freq()
117 /* AUD_COUNT = 0x92ff = 49 samples * 2 * 384 - 1 */ in set_audclk_freq()
136 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
140 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz p-pd*/ in set_audclk_freq()
152 /* AUD_COUNT = 0x5fff = 4 samples * 16 * 384 - 1 */ in set_audclk_freq()
173 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
177 /* xtal * 0xd.bb3a060/0x30 = 32000 * 256: 393 MHz p-pd*/ in set_audclk_freq()
212 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
216 /* xtal * 0xe.3150f90/0x24 = 44100 * 256: 406 MHz p-pd*/ in set_audclk_freq()
251 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
255 /* xtal * 0xd.bb3a060/0x20 = 48000 * 256: 393 MHz p-pd*/ in set_audclk_freq()