Lines Matching +full:vref +full:- +full:p
1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
152 #define SVC_MODE_PAL BIT(2) /* 0=NTSC(480i/p) 1=PAL(576i/p) */
165 #define RT_MAN_CTRL_RT_B BIT(1) /* enable TMDS pull-up on Input B */
166 #define RT_MAN_CTRL_RT_A BIT(0) /* enable TMDS pull-up on Input A */
212 #define PCLK_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
227 /* Page 0x01 - HDMI info and packets */
247 /* Page 0x12 - HDMI Extra control and debug */
279 /* Page 0x13 - HDMI Extra control and debug */
351 /* Page 0x14 - Audio Extra control and debug */
399 /* Page 0x21 - EDID content */
409 /* Page 0x30 - NV Configuration */
429 /* Page 0x80 - CEC */
545 #define OF_FMT_422_SMPT 1L /* YUV422 semi-planar */
550 #define HS_HREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
562 #define VS_VREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
567 #define VS_VREF_SEL_VREF_VHREF 1L /* VREF from VHREF */
568 #define VS_VREF_SEL_VREF_HDMI 2L /* VREF from HDMI */
573 #define DE_FREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
578 #define DE_FREF_SEL_DE_VHREF 0L /* DE from VHREF (HREF and not(VREF) */
586 #define RESET_KSV BIT(5) /* Reset KSV-FIFO */
612 #define AUDIO_LAYOUT_LAYOUT1 BIT(0) /* Layout1: AP0-3 vs Layout0:AP0 */