Lines Matching +full:page +full:- +full:mode +full:- +full:read +full:- +full:delay

1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
140 /* Service Mode */
165 #define RT_MAN_CTRL_RT_B	BIT(1)	/* enable TMDS pull-up on Input B */
166 #define RT_MAN_CTRL_RT_A	BIT(0)	/* enable TMDS pull-up on Input A */
212 #define PCLK_DELAY_SHIFT	4	/* Pixel delay (-8..+7) */
227 /* Page 0x01 - HDMI info and packets */
244 #define HDMI_FLAGS_AUD_FIFO_OF	BIT(1)	/* FIFO read/write pointers crossed */
245 #define HDMI_FLAGS_AUD_FIFO_LOW	BIT(0)	/* FIFO read ptr within 2 of write */
247 /* Page 0x12 - HDMI Extra control and debug */
279 /* Page 0x13 - HDMI Extra control and debug */
300 #define HDCP_DE_MODE_MASK	0xc0	/* DE Measurement mode */
302 #define HDCP_DE_REGEN_EN	BIT(5)	/* enable regen mode */
305 #define HDCP_DE_COMP_MASK	0x07	/* DE Composition mode */
351 /* Page 0x14 - Audio Extra control and debug */
368 /* Page 0x20: EDID and Hotplug Detect */
399 /* Page 0x21 - EDID content */
409 /* Page 0x30 - NV Configuration */
429 /* Page 0x80 - CEC */
440 #define INTERRUPT_MODE		BIT(3) /* HDMI mode module */
476 #define MASK_READ_DONE		BIT(4) /* End of down EDID read */
483 #define MASK_HDMI_FLG		BIT(7) /* HDMI mode/avmute/encrypt/FIFO fail */
545 #define OF_FMT_422_SMPT		1L	/* YUV422 semi-planar */
550 #define HS_HREF_DELAY_SHIFT	4	/* Pixel delay (-8..+7) */
562 #define VS_VREF_DELAY_SHIFT	4	/* Pixel delay (-8..+7) */
573 #define DE_FREF_DELAY_SHIFT	4	/* Pixel delay (-8..+7) */
586 #define RESET_KSV		BIT(5)	/* Reset KSV-FIFO */
612 #define AUDIO_LAYOUT_LAYOUT1	BIT(0)  /* Layout1: AP0-3 vs Layout0:AP0 */