Lines Matching +full:fifo +full:- +full:depth +full:- +full:bits
1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
165 #define RT_MAN_CTRL_RT_B BIT(1) /* enable TMDS pull-up on Input B */
166 #define RT_MAN_CTRL_RT_A BIT(0) /* enable TMDS pull-up on Input A */
212 #define PCLK_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
227 /* Page 0x01 - HDMI info and packets */
244 #define HDMI_FLAGS_AUD_FIFO_OF BIT(1) /* FIFO read/write pointers crossed */
245 #define HDMI_FLAGS_AUD_FIFO_LOW BIT(0) /* FIFO read ptr within 2 of write */
247 /* Page 0x12 - HDMI Extra control and debug */
279 /* Page 0x13 - HDMI Extra control and debug */
334 /* CGU_DBG_SEL bits */
341 /* REG_MAN_SUS_HDMI_SEL / REG_MAN_HDMI_SET bits */
351 /* Page 0x14 - Audio Extra control and debug */
399 /* Page 0x21 - EDID content */
409 /* Page 0x30 - NV Configuration */
429 /* Page 0x80 - CEC */
445 /* INT_FLG_CLR_HDCP bits */
453 /* INT_FLG_CLR_RATE bits */
463 /* INT_FLG_CLR_SUS (Start Up Sequencer) bits */
472 /* INT_FLG_CLR_DDC bits */
482 /* INT_FLG_CLR_MODE bits */
483 #define MASK_HDMI_FLG BIT(7) /* HDMI mode/avmute/encrypt/FIFO fail */
490 #define MASK_DC_MODE BIT(0) /* deepcolor color depth changed */
492 /* INT_FLG_CLR_INFO bits (Infoframe Change Status) */
501 /* INT_FLG_CLR_AUDIO bits */
507 #define MASK_ERROR_FIFO_PT BIT(0) /* Audio FIFO pointer error */
509 /* INT_FLG_CLR_AFE bits */
545 #define OF_FMT_422_SMPT 1L /* YUV422 semi-planar */
550 #define HS_HREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
562 #define VS_VREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
573 #define DE_FREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
583 /* HDMI_SOFT_RST bits */
586 #define RESET_KSV BIT(5) /* Reset KSV-FIFO */
593 /* HDMI_INFO_RST bits */
595 #define RESET_FIFO BIT(4) /* Reset Audio FIFO control */
599 #define RESET_AUDIO BIT(0) /* Reset Audio FIFO control */
601 /* HDCP_BCAPS bits */
610 #define AUDIO_LAYOUT_SP_FLAG BIT(2) /* sp flag used by FIFO */
612 #define AUDIO_LAYOUT_LAYOUT1 BIT(0) /* Layout1: AP0-3 vs Layout0:AP0 */