Lines Matching +full:audio +full:- +full:formatter +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
131 #define DETECT_5V_B BIT(1) /* 5V present on input B */
135 #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */
136 #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */
137 #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */
138 #define INPUT_SEL_B BIT(0) /* 0=inputA 1=inputB */
144 #define SVC_MODE_CLK2_XTLDIV2 1L
149 #define SVC_MODE_CLK1_XTLDIV2 1L
151 #define SVC_MODE_RAMP BIT(3) /* 0=colorbar 1=ramp */
152 #define SVC_MODE_PAL BIT(2) /* 0=NTSC(480i/p) 1=PAL(576i/p) */
153 #define SVC_MODE_INT_PROG BIT(1) /* 0=interlaced 1=progressive */
159 #define HPD_MAN_CTRL_HPD_B BIT(1) /* Assert HPD High for Input A */
165 #define RT_MAN_CTRL_RT_B BIT(1) /* enable TMDS pull-up on Input B */
166 #define RT_MAN_CTRL_RT_A BIT(0) /* enable TMDS pull-up on Input A */
170 #define VDP_CTRL_FORMATTER_BP BIT(4) /* bypass formatter */
171 #define VDP_CTRL_PREFILTER_BP BIT(1) /* bypass prefilter */
175 #define VHREF_INT_DET BIT(7) /* interlace detect: 1=alt 0=frame */
179 #define VHREF_VSYNC_FDW 1L
185 #define VHREF_STD_DET_NTSC 1L
188 #define VHREF_VREF_SRC_STD BIT(2) /* 1=from standard 0=manual */
189 #define VHREF_HREF_SRC_STD BIT(1) /* 1=from standard 0=manual */
190 #define VHREF_HSYNC_SEL_HS BIT(0) /* 1=HS 0=VS */
197 #define AUDIO_OUT_ENABLE_AP1 BIT(1)
206 #define FILTERS_CTRL_2TAP 1L /* 2 Taps */
212 #define PCLK_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
217 #define PCLK_SEL_X2 1L
225 #define PIX_REPEAT_CHROMA 1
227 /* Page 0x01 - HDMI info and packets */
238 #define HDMI_FLAGS_AUDIO BIT(7) /* Audio packet in last videoframe */
243 #define HDMI_FLAGS_AUD_LAYOUT BIT(2) /* Layout status Audio sample packet */
244 #define HDMI_FLAGS_AUD_FIFO_OF BIT(1) /* FIFO read/write pointers crossed */
247 /* Page 0x12 - HDMI Extra control and debug */
269 #define PON_EN 1
275 #define CLK_CFG_SEL_ACLK_EN BIT(1)
279 /* Page 0x13 - HDMI Extra control and debug */
311 #define HDCP_DE_COMP_CH1 1L
326 #define HDMI_CTRL_MUTE_OFF 1L
331 #define HDMI_CTRL_HDCP_OESS 1L
338 #define CGU_DBG_VDP_CLK_SEL BIT(1)
348 #define MAN_RST_TMDS_ENC BIT(1)
351 /* Page 0x14 - Audio Extra control and debug */
358 /* Audio Clock Configuration */
362 #define AUDIO_CLOCK_SEL_32FS 1L /* 32*fs */
380 #define EDID_ENABLE_B_EN BIT(1)
387 #define HPD_POWER_BP_HIGH 1L
388 #define HPD_POWER_EDID_ONLY BIT(1)
396 #define HPD_AUTO_HPD_PRV_CH BIT(1)
399 /* Page 0x21 - EDID content */
409 /* Page 0x30 - NV Configuration */
429 /* Page 0x80 - CEC */
438 #define INTERRUPT_AUDIO BIT(5) /* Audio module */
442 #define INTERRUPT_DDC BIT(1) /* DDC module */
450 #define MASK_STATE_C5 BIT(1) /* HDCP State C5 reached */
460 #define MASK_RATE_A_ACT BIT(1) /* Rate measurement presence change */
469 #define MASK_SUS_CH BIT(1) /* Selected input changed */
479 #define MASK_HDP_PULSE_END BIT(1) /* End of Hot Plug Detect pulse */
487 #define MASK_ACP BIT(3) /* Audio Content Protection packet */
489 #define MASK_DC_PHASE BIT(1) /* deepcolor pixel phase needs update */
494 #define MASK_AUD_IF BIT(5) /* Audio */
498 #define MASK_VS_IF_OTHER_BK1 BIT(1) /* Vendor Specific (bank1) */
502 #define MASK_AUDIO_FREQ_FLG BIT(5) /* Audio freq change */
504 #define MASK_MUTE_FLG BIT(3) /* Audio Mute */
506 #define MASK_UNMUTE_FIFO BIT(1) /* Audio Unmute */
507 #define MASK_ERROR_FIFO_PT BIT(0) /* Audio FIFO pointer error */
516 #define MASK_AFE_ASU_STATE BIT(1) /* ASU state is reached */
519 /* Audio Output */
524 #define AUDCFG_BUS_SPDIF 1L
527 #define AUDCFG_I2SW_32 1L
528 #define AUDCFG_AUTO_MUTE_EN BIT(3) /* Enable Automatic audio mute */
531 #define AUDCFG_HBR_DEMUX 1L /* demuxed via AP0:AP3 */
535 #define AUDCFG_TYPE_OBA 2L /* One Bit Audio (OBA) */
536 #define AUDCFG_TYPE_HBR 1L /* High Bit Rate (HBR) */
537 #define AUDCFG_TYPE_PCM 0L /* Audio samples */
539 /* Video Formatter */
545 #define OF_FMT_422_SMPT 1L /* YUV422 semi-planar */
550 #define HS_HREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
552 #define HS_HREF_INV_SHIFT 2 /* polarity (1=invert) */
556 #define HS_HREF_SEL_HREF_VHREF 1L /* HREF from VHREF */
562 #define VS_VREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
563 #define VS_VREF_INV_SHIFT 2 /* polarity (1=invert) */
567 #define VS_VREF_SEL_VREF_VHREF 1L /* VREF from VHREF */
573 #define DE_FREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
575 #define DE_FREF_INV_SHIFT 2 /* polarity (1=invert) */
579 #define DE_FREF_SEL_FREF_VHREF 1L /* FREF from VHREF */
586 #define RESET_KSV BIT(5) /* Reset KSV-FIFO */
590 #define RESET_EP BIT(1) /* Reset Error protection */
595 #define RESET_FIFO BIT(4) /* Reset Audio FIFO control */
598 #define RESET_IF BIT(1) /* Clear all Audio infoframe packets */
599 #define RESET_AUDIO BIT(0) /* Reset Audio FIFO control */
606 #define HDCP_11 BIT(1) /* HDCP 1.1 supported */
609 /* Audio output formatter */
611 #define AUDIO_LAYOUT_MANUAL BIT(1) /* manual layout (vs per pkt) */
612 #define AUDIO_LAYOUT_LAYOUT1 BIT(0) /* Layout1: AP0-3 vs Layout0:AP0 */