Lines Matching +full:3 +full:l
143 #define SVC_MODE_CLK2_XTL 0L
144 #define SVC_MODE_CLK2_XTLDIV2 1L
145 #define SVC_MODE_CLK2_HDMIX2 3L
148 #define SVC_MODE_CLK1_XTAL 0L
149 #define SVC_MODE_CLK1_XTLDIV2 1L
150 #define SVC_MODE_CLK1_HDMI 3L
151 #define SVC_MODE_RAMP BIT(3) /* 0=colorbar 1=ramp */
178 #define VHREF_VSYNC_AUTO 0L
179 #define VHREF_VSYNC_FDW 1L
180 #define VHREF_VSYNC_EVEN 2L
181 #define VHREF_VSYNC_ODD 3L
183 #define VHREF_STD_DET_SHIFT 3
184 #define VHREF_STD_DET_PAL 0L
185 #define VHREF_STD_DET_NTSC 1L
186 #define VHREF_STD_DET_AUTO 2L
187 #define VHREF_STD_DET_OFF 3L
195 #define AUDIO_OUT_ENABLE_AP3 BIT(3)
205 #define FILTERS_CTRL_OFF 0L /* off */
206 #define FILTERS_CTRL_2TAP 1L /* 2 Taps */
207 #define FILTERS_CTRL_7TAP 2L /* 7 Taps */
208 #define FILTERS_CTRL_2_7TAP 3L /* 2/7 Taps */
216 #define PCLK_SEL_X1 0L
217 #define PCLK_SEL_X2 1L
218 #define PCLK_SEL_DIV2 2L
219 #define PCLK_SEL_DIV4 3L
242 #define HDMI_FLAGS_AVMUTE BIT(3) /* AVMUTE */
304 #define HDCP_DE_FILTER_SHIFT 3
306 #define HDCP_DE_COMP_MIXED 6L
307 #define HDCP_DE_COMP_OR 5L
308 #define HDCP_DE_COMP_AND 4L
309 #define HDCP_DE_COMP_CH3 3L
310 #define HDCP_DE_COMP_CH2 2L
311 #define HDCP_DE_COMP_CH1 1L
312 #define HDCP_DE_COMP_CH0 0L
325 #define HDMI_CTRL_MUTE_AUTO 0L
326 #define HDMI_CTRL_MUTE_OFF 1L
327 #define HDMI_CTRL_MUTE_ON 2L
330 #define HDMI_CTRL_HDCP_EESS 2L
331 #define HDMI_CTRL_HDCP_OESS 1L
332 #define HDMI_CTRL_HDCP_AUTO 0L
336 #define CGU_DBG_CLK_SEL_SHIFT 3
346 #define MAN_DIS_TMDS_FLOW BIT(3)
361 #define AUDIO_CLOCK_SEL_16FS 0L /* 16*fs */
362 #define AUDIO_CLOCK_SEL_32FS 1L /* 32*fs */
363 #define AUDIO_CLOCK_SEL_64FS 2L /* 64*fs */
364 #define AUDIO_CLOCK_SEL_128FS 3L /* 128*fs */
365 #define AUDIO_CLOCK_SEL_256FS 4L /* 256*fs */
366 #define AUDIO_CLOCK_SEL_512FS 5L /* 512*fs */
386 #define HPD_POWER_BP_LOW 0L
387 #define HPD_POWER_BP_HIGH 1L
394 #define HPD_AUTO_HPD_UNSEL BIT(3)
440 #define INTERRUPT_MODE BIT(3) /* HDMI mode module */
448 #define MASK_HDCP_DLRAM BIT(3) /* HDCP end download keys from SRAM */
458 #define MASK_RATE_A_DRIFT BIT(3) /* Rate measurement drifted */
467 #define MASK_SUS_END BIT(3) /* SUS last state reached */
477 #define MASK_RX_DDC_SW BIT(3) /* Output DDC switching finished */
487 #define MASK_ACP BIT(3) /* Audio Content Protection packet */
496 #define MASK_AVI_IF BIT(3) /* Auxiliary Video IF */
504 #define MASK_MUTE_FLG BIT(3) /* Audio Mute */
514 #define MASK_AFE_PLL_LOCK BIT(3) /* TMDS PLL is locked */
523 #define AUDCFG_BUS_I2S 0L
524 #define AUDCFG_BUS_SPDIF 1L
526 #define AUDCFG_I2SW_16 0L
527 #define AUDCFG_I2SW_32 1L
528 #define AUDCFG_AUTO_MUTE_EN BIT(3) /* Enable Automatic audio mute */
530 #define AUDCFG_HBR_STRAIGHT 0L /* straight via AP0 */
531 #define AUDCFG_HBR_DEMUX 1L /* demuxed via AP0:AP3 */
534 #define AUDCFG_TYPE_DST 3L /* Direct Stream Transfer (DST) */
535 #define AUDCFG_TYPE_OBA 2L /* One Bit Audio (OBA) */
536 #define AUDCFG_TYPE_HBR 1L /* High Bit Rate (HBR) */
537 #define AUDCFG_TYPE_PCM 0L /* Audio samples */
542 #define OF_TRC BIT(3) /* timing codes (SAV/EAV) */
544 #define OF_FMT_444 0L /* RGB444/YUV444 */
545 #define OF_FMT_422_SMPT 1L /* YUV422 semi-planar */
546 #define OF_FMT_422_CCIR 2L /* YUV422 CCIR656 */
551 #define HS_HREF_PXQ_SHIFT 3 /* Timing codes from HREF */
555 #define HS_HREF_SEL_HS_VHREF 0L /* HS from VHREF */
556 #define HS_HREF_SEL_HREF_VHREF 1L /* HREF from VHREF */
557 #define HS_HREF_SEL_HREF_HDMI 2L /* HREF from HDMI */
558 #define HS_HREF_SEL_NONE 3L /* not generated */
566 #define VS_VREF_SEL_VS_VHREF 0L /* VS from VHREF */
567 #define VS_VREF_SEL_VREF_VHREF 1L /* VREF from VHREF */
568 #define VS_VREF_SEL_VREF_HDMI 2L /* VREF from HDMI */
569 #define VS_VREF_SEL_NONE 3L /* not generated */
574 #define DE_FREF_DE_PXQ_SHIFT 3 /* Timing codes from DE */
578 #define DE_FREF_SEL_DE_VHREF 0L /* DE from VHREF (HREF and not(VREF) */
579 #define DE_FREF_SEL_FREF_VHREF 1L /* FREF from VHREF */
580 #define DE_FREF_SEL_FREF_HDMI 2L /* FREF from HDMI */
581 #define DE_FREF_SEL_NONE 3L /* not generated */
588 #define RESET_HCFG BIT(3) /* Reset HDCP DDC part */
596 #define RESET_GAMUT BIT(3) /* Clear Gamut packet */
612 #define AUDIO_LAYOUT_LAYOUT1 BIT(0) /* Layout1: AP0-3 vs Layout0:AP0 */