Lines Matching +full:vsync +full:- +full:polarity +full:- +full:high
1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/v4l2-dv-timings.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-dv-timings.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-fwnode.h>
31 #include <dt-bindings/media/tda1997x.h>
40 MODULE_PARM_DESC(debug, "debug level (0-2)");
45 "HBR", /* High Bit Rate Audio */
46 "OBA", /* One-Bit Audio */
71 "Full Range (0-255)",
72 "Limited Range (16-235)",
78 "YUV422 semi-planar", /* YUV422 16bit data base, 8bpp */
121 "YUV709 -> RGB full",
122 -256, -2048, -2048,
123 4769, -2183, -873,
129 "YUV601 -> RGB full",
130 -256, -2048, -2048,
131 4769, -3330, -1602,
137 "RGB limited -> RGB full",
138 -256, -256, -256,
145 "RGB limited -> ITU601",
146 -256, -256, -256,
148 -1754, 2095, -341,
149 -1388, -707, 2095,
153 "RGB limited -> ITU709",
154 -256, -256, -256,
156 -1894, 2087, -190,
157 -1607, -477, 2087,
161 "RGB full -> ITU601",
164 -1506, 1799, -293,
165 -1192, -607, 1799,
169 "RGB full -> ITU709",
172 -1627, 1792, -163,
173 -1380, -410, 1792,
303 return &container_of(ctrl->handler, struct tda1997x_state, hdl)->sd;
311 val = i2c_smbus_read_byte_data(state->client_cec, reg);
313 v4l_err(state->client, "read reg error: reg=%2x\n", reg);
314 val = -1;
325 ret = i2c_smbus_write_byte_data(state->client_cec, reg, val);
327 v4l_err(state->client, "write reg error:reg=%2x,val=%2x\n",
329 ret = -1;
335 /* -----------------------------------------------------------------------------
344 if (state->page != page) {
345 ret = i2c_smbus_write_byte_data(state->client,
348 v4l_err(state->client,
353 state->page = page;
363 mutex_lock(&state->page_lock);
365 val = -1;
369 val = i2c_smbus_read_byte_data(state->client, reg&0xff);
371 v4l_err(state->client, "read reg error: reg=%2x\n", reg & 0xff);
372 val = -1;
377 mutex_unlock(&state->page_lock);
441 mutex_lock(&state->page_lock);
443 ret = -1;
447 ret = i2c_smbus_write_byte_data(state->client, reg & 0xff, val);
449 v4l_err(state->client, "write reg error:reg=%2x,val=%2x\n",
451 ret = -1;
456 mutex_unlock(&state->page_lock);
489 /* -----------------------------------------------------------------------------
496 HPD_HIGH_BP, /* HIGH */
526 /* HPD high */
542 /* HPD high */
564 struct v4l2_subdev *sd = &state->sd;
568 /* Set HPD high */
572 state->edid.present = 1;
580 cancel_delayed_work_sync(&state->delayed_work_enable_hpd);
593 schedule_delayed_work(&state->delayed_work_enable_hpd, HZ / 10);
596 /* -----------------------------------------------------------------------------
606 v4l_dbg(1, debug, state->client, "%s code=0x%x\n", __func__, code);
612 state->vid_fmt = OF_FMT_444;
617 state->vid_fmt = OF_FMT_422_SMPT;
622 state->vid_fmt = OF_FMT_422_CCIR;
625 v4l_err(state->client, "incompatible format (0x%x)\n", code);
626 return -EINVAL;
628 v4l_dbg(1, debug, state->client, "%s code=0x%x fmt=%s\n", __func__,
629 code, vidfmt_names[state->vid_fmt]);
630 state->mbus_code = code;
638 * full-range and YUV is to be limited range.
640 * RGB full-range uses values from 0 to 255 which is recommended on a monitor
648 struct hdmi_avi_infoframe *avi = &state->avi_infoframe;
649 struct v4l2_hdmi_colorimetry *c = &state->colorimetry;
661 v4l_dbg(1, debug, state->client, "input:%s quant:%s output:%s\n",
662 hdmi_colorspace_names[avi->colorspace],
663 v4l2_quantization_names[c->quantization],
664 vidfmt_names[state->vid_fmt]);
665 state->conv = NULL;
666 switch (state->vid_fmt) {
670 if (c->colorspace == V4L2_COLORSPACE_SRGB) {
671 if (c->quantization == V4L2_QUANTIZATION_LIM_RANGE)
672 state->conv = &conv_matrix[RGBLIMITED_RGBFULL];
674 if (c->colorspace == V4L2_COLORSPACE_REC709)
675 state->conv = &conv_matrix[ITU709_RGBFULL];
676 else if (c->colorspace == V4L2_COLORSPACE_SMPTE170M)
677 state->conv = &conv_matrix[ITU601_RGBFULL];
682 case OF_FMT_422_SMPT: /* semi-planar */
685 if ((c->colorspace == V4L2_COLORSPACE_SRGB) &&
686 (c->quantization == V4L2_QUANTIZATION_FULL_RANGE)) {
687 if (state->timings.bt.height <= 576)
688 state->conv = &conv_matrix[RGBFULL_ITU601];
690 state->conv = &conv_matrix[RGBFULL_ITU709];
691 } else if ((c->colorspace == V4L2_COLORSPACE_SRGB) &&
692 (c->quantization == V4L2_QUANTIZATION_LIM_RANGE)) {
693 if (state->timings.bt.height <= 576)
694 state->conv = &conv_matrix[RGBLIMITED_ITU601];
696 state->conv = &conv_matrix[RGBLIMITED_ITU709];
701 if (state->conv) {
702 v4l_dbg(1, debug, state->client, "%s\n",
703 state->conv->name);
709 io_write16(sd, REG_VDP_MATRIX + 0, state->conv->offint1);
710 io_write16(sd, REG_VDP_MATRIX + 2, state->conv->offint2);
711 io_write16(sd, REG_VDP_MATRIX + 4, state->conv->offint3);
713 io_write16(sd, REG_VDP_MATRIX + 6, state->conv->p11coef);
714 io_write16(sd, REG_VDP_MATRIX + 8, state->conv->p12coef);
715 io_write16(sd, REG_VDP_MATRIX + 10, state->conv->p13coef);
716 io_write16(sd, REG_VDP_MATRIX + 12, state->conv->p21coef);
717 io_write16(sd, REG_VDP_MATRIX + 14, state->conv->p22coef);
718 io_write16(sd, REG_VDP_MATRIX + 16, state->conv->p23coef);
719 io_write16(sd, REG_VDP_MATRIX + 18, state->conv->p31coef);
720 io_write16(sd, REG_VDP_MATRIX + 20, state->conv->p32coef);
721 io_write16(sd, REG_VDP_MATRIX + 22, state->conv->p33coef);
723 io_write16(sd, REG_VDP_MATRIX + 24, state->conv->offout1);
724 io_write16(sd, REG_VDP_MATRIX + 26, state->conv->offout2);
725 io_write16(sd, REG_VDP_MATRIX + 28, state->conv->offout3);
735 io_write16(sd, REG_BLK_GY, blanking_codes->code_gy);
736 io_write16(sd, REG_BLK_BU, blanking_codes->code_bu);
737 io_write16(sd, REG_BLK_RV, blanking_codes->code_rv);
746 const struct v4l2_bt_timings *bt = &state->timings.bt;
755 href_start = bt->hbackporch + bt->hsync + 1;
756 href_end = href_start + bt->width;
757 vref_f1_start = bt->height + bt->vbackporch + bt->vsync +
758 bt->il_vbackporch + bt->il_vsync +
759 bt->il_vfrontporch;
760 vref_f1_width = bt->vbackporch + bt->vsync + bt->vfrontporch;
765 if (bt->interlaced) {
766 vref_f2_start = (bt->height / 2) +
767 (bt->il_vbackporch + bt->il_vsync - 1);
768 vref_f2_width = bt->il_vbackporch + bt->il_vsync +
769 bt->il_vfrontporch;
770 fieldref_f2_start = vref_f2_start + bt->il_vfrontporch +
780 * horiz area where the VHREF module consider a VSYNC a new frame
786 if (state->chip_revision == 0)
805 * horiz and vert ref values (non-active pixel areas) of the generator
818 /* F1/F2 FREF, field polarity */
830 struct v4l2_subdev *sd = &state->sd;
831 struct tda1997x_platform_data *pdata = &state->pdata;
835 /* Configure pixel clock generator: delay, polarity, rate */
836 reg = (state->vid_fmt == OF_FMT_422_CCIR) ?
838 reg |= pdata->vidout_delay_pclk << PCLK_DELAY_SHIFT;
839 reg |= pdata->vidout_inv_pclk << PCLK_INV_SHIFT;
842 /* Configure pre-filter */
845 if ((state->vid_fmt == OF_FMT_422_SMPT) ||
846 (state->vid_fmt == OF_FMT_422_CCIR)) {
854 reg = state->vid_fmt & OF_FMT_MASK;
855 if (state->vid_fmt == OF_FMT_422_CCIR)
862 /* pre-filter is needed unless (REG_FILTERS_CTRL == 0) */
868 if (state->vid_fmt == OF_FMT_444)
874 if ((pdata->vidout_delay_vs < 4) || (pdata->vidout_delay_hs < 4))
878 /* Configure DE output signal: delay, polarity, and source */
879 reg = pdata->vidout_delay_de << DE_FREF_DELAY_SHIFT |
880 pdata->vidout_inv_de << DE_FREF_INV_SHIFT |
881 pdata->vidout_sel_de << DE_FREF_SEL_SHIFT;
884 /* Configure HS/HREF output signal: delay, polarity, and source */
885 if (state->vid_fmt != OF_FMT_422_CCIR) {
886 reg = pdata->vidout_delay_hs << HS_HREF_DELAY_SHIFT |
887 pdata->vidout_inv_hs << HS_HREF_INV_SHIFT |
888 pdata->vidout_sel_hs << HS_HREF_SEL_SHIFT;
893 /* Configure VS/VREF output signal: delay, polarity, and source */
894 if (state->vid_fmt != OF_FMT_422_CCIR) {
895 reg = pdata->vidout_delay_vs << VS_VREF_DELAY_SHIFT |
896 pdata->vidout_inv_vs << VS_VREF_INV_SHIFT |
897 pdata->vidout_sel_vs << VS_VREF_SEL_SHIFT;
910 struct tda1997x_platform_data *pdata = &state->pdata;
914 if (!pdata->audout_format)
917 /* channel assignment (CEA-861-D Table 20) */
922 switch (pdata->audout_format) {
930 switch (state->audio_type) {
943 if (pdata->audout_layout == 1) {
946 if (pdata->audout_format == AUDFMT_TYPE_SPDIF)
954 if (pdata->audout_width == 32)
960 if (pdata->audio_auto_mute)
962 /* clock polarity */
963 if (pdata->audout_invert_clk)
968 reg = (pdata->audout_layout) ? AUDIO_LAYOUT_LAYOUT1 : 0;
969 if (!pdata->audout_layoutauto)
1006 if (pdata->audout_format == AUDFMT_TYPE_I2S)
1032 /* Disable REFTIM to restart start-up-sequencer (SUS) */
1045 struct v4l2_subdev *sd = &state->sd;
1094 struct v4l2_subdev *sd = &state->sd;
1105 u16 vtot, vact, vfront1, vfront2, vsync, vback1, vback2;
1107 if (!state->input_detect[0] && !state->input_detect[1])
1108 return -ENOLINK;
1131 vsync = io_read(sd, REG_FMT_V_SYNC);
1136 htot, hact, hfront, hsync, hback, hsync_pos ? '+' : '-',
1137 vtot, vact, vfront1, vfront2, vsync, vback1, vback2, vsync_pos ? '+' : '-');
1142 timings->type = V4L2_DV_BT_656_1120;
1143 timings->bt.width = hact;
1144 timings->bt.hfrontporch = hfront;
1145 timings->bt.hsync = hsync;
1146 timings->bt.hbackporch = hback;
1147 timings->bt.height = vact;
1148 timings->bt.vfrontporch = vfront1;
1149 timings->bt.vsync = vsync;
1150 timings->bt.vbackporch = vback1;
1151 timings->bt.interlaced = interlaced ? V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1152 timings->bt.polarities = vsync_pos ? V4L2_DV_VSYNC_POS_POL : 0;
1153 timings->bt.polarities |= hsync_pos ? V4L2_DV_HSYNC_POS_POL : 0;
1155 timings->bt.pixelclock = (u64)htot * vtot * 27000000;
1157 timings->bt.il_vfrontporch = vfront2;
1158 timings->bt.il_vsync = timings->bt.vsync;
1159 timings->bt.il_vbackporch = vback2;
1160 do_div(timings->bt.pixelclock, vper * 2 /* full frame */);
1162 timings->bt.il_vfrontporch = 0;
1163 timings->bt.il_vsync = 0;
1164 timings->bt.il_vbackporch = 0;
1165 do_div(timings->bt.pixelclock, vper);
1168 (u32)timings->bt.pixelclock / 500, NULL, NULL);
1169 v4l2_print_dv_timings(sd->name, "Detected format: ", timings, false);
1176 struct v4l2_subdev *sd = &state->sd;
1236 struct v4l2_hdmi_colorimetry *c = &state->colorimetry;
1238 state->colorimetry = v4l2_hdmi_rx_colorimetry(&state->avi_infoframe,
1240 state->timings.bt.height);
1242 if (c->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) {
1243 switch (state->rgb_quantization_range) {
1245 c->quantization = V4L2_QUANTIZATION_FULL_RANGE;
1248 c->quantization = V4L2_QUANTIZATION_LIM_RANGE;
1252 v4l_dbg(1, debug, state->client,
1254 state->avi_infoframe.colorspace, c->colorspace,
1255 state->avi_infoframe.colorimetry,
1256 v4l2_quantization_names[c->quantization],
1257 state->avi_infoframe.content_type);
1264 struct v4l2_subdev *sd = &state->sd;
1274 v4l_err(state->client,
1279 hdmi_infoframe_log(KERN_INFO, &state->client->dev, &frame);
1286 state->audio_samplerate = 32000;
1289 state->audio_samplerate = 44100;
1292 state->audio_samplerate = 48000;
1295 state->audio_samplerate = 88200;
1298 state->audio_samplerate = 96000;
1301 state->audio_samplerate = 176400;
1304 state->audio_samplerate = 192000;
1314 state->audio_samplesize = 16;
1317 state->audio_samplesize = 20;
1320 state->audio_samplesize = 24;
1328 state->audio_channels = frame.audio.channels;
1330 frame.audio.channel_allocation != state->audio_ch_alloc) {
1332 state->audio_ch_alloc = frame.audio.channel_allocation;
1333 tda1997x_configure_audout(sd, state->audio_ch_alloc);
1341 state->avi_infoframe = frame.avi;
1351 /* ConfigurePixelRepeater: repeat n-times each pixel */
1368 struct v4l2_subdev *sd = &state->sd;
1376 if (state->mptrw_in_progress)
1377 state->mptrw_in_progress = 0;
1389 state->hdmi_status = 0;
1402 v4l_err(state->client, "BAD SUS STATUS\n");
1408 v4l2_subdev_notify_event(&state->sd, &tda1997x_ev_fmt);
1414 struct v4l2_subdev *sd = &state->sd;
1421 if (state->mptrw_in_progress)
1422 state->mptrw_in_progress = 0;
1427 v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
1434 struct v4l2_subdev *sd = &state->sd;
1463 if ((irq_status & mask) != (state->activity_status & mask)) {
1466 v4l_info(state->client,
1467 "HDMI-%c: Digital Activity Lost\n",
1476 if (state->chip_revision == 0)
1479 state->input_detect[input] = 0;
1485 v4l_info(state->client,
1486 "HDMI-%c: Digital Activity Detected\n",
1488 state->input_detect[input] = 1;
1492 state->activity_status = (irq_status & mask);
1499 struct v4l2_subdev *sd = &state->sd;
1526 struct v4l2_subdev *sd = &state->sd;
1553 state->audio_samplerate = freq[reg & 7];
1554 v4l_info(state->client, "Audio Frequency Change: %dHz\n",
1555 state->audio_samplerate);
1560 state->audio_type = AUDCFG_TYPE_DST;
1562 state->audio_type = AUDCFG_TYPE_OBA;
1564 state->audio_type = AUDCFG_TYPE_HBR;
1566 state->audio_type = AUDCFG_TYPE_PCM;
1567 v4l_info(state->client, "Audio Type: %s\n",
1568 audtype_names[state->audio_type]);
1574 struct v4l2_subdev *sd = &state->sd;
1582 state->mptrw_in_progress = 0;
1595 struct v4l2_subdev *sd = &state->sd;
1598 mutex_lock(&state->lock);
1626 mutex_unlock(&state->lock);
1631 /* -----------------------------------------------------------------------------
1643 mutex_lock(&state->lock);
1659 state->input_detect[0], state->input_detect[1],
1661 if (!state->input_detect[0] && !state->input_detect[1])
1667 mutex_unlock(&state->lock);
1677 v4l_dbg(1, debug, state->client, "%s\n", __func__);
1679 if (v4l2_match_dv_timings(&state->timings, timings, 0, false))
1684 return -ERANGE;
1686 mutex_lock(&state->lock);
1687 state->timings = *timings;
1692 mutex_unlock(&state->lock);
1702 v4l_dbg(1, debug, state->client, "%s\n", __func__);
1703 mutex_lock(&state->lock);
1704 *timings = state->timings;
1705 mutex_unlock(&state->lock);
1716 v4l_dbg(1, debug, state->client, "%s\n", __func__);
1718 mutex_lock(&state->lock);
1720 mutex_unlock(&state->lock);
1730 /* -----------------------------------------------------------------------------
1741 mf->code = state->mbus_codes[0];
1752 v4l_dbg(1, debug, state->client, "%s %d\n", __func__, code->index);
1753 if (code->index >= ARRAY_SIZE(state->mbus_codes))
1754 return -EINVAL;
1756 if (!state->mbus_codes[code->index])
1757 return -EINVAL;
1759 code->code = state->mbus_codes[code->index];
1770 bt = &state->timings.bt;
1771 format->width = bt->width;
1772 format->height = bt->height;
1773 format->colorspace = state->colorimetry.colorspace;
1774 format->field = (bt->interlaced) ?
1784 v4l_dbg(1, debug, state->client, "%s pad=%d which=%d\n",
1785 __func__, format->pad, format->which);
1787 tda1997x_fill_format(state, &format->format);
1789 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1792 fmt = v4l2_subdev_state_get_format(sd_state, format->pad);
1793 format->format.code = fmt->code;
1795 format->format.code = state->mbus_code;
1808 v4l_dbg(1, debug, state->client, "%s pad=%d which=%d fmt=0x%x\n",
1809 __func__, format->pad, format->which, format->format.code);
1811 for (i = 0; i < ARRAY_SIZE(state->mbus_codes); i++) {
1812 if (format->format.code == state->mbus_codes[i]) {
1813 code = state->mbus_codes[i];
1818 code = state->mbus_codes[0];
1820 tda1997x_fill_format(state, &format->format);
1821 format->format.code = code;
1823 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1826 fmt = v4l2_subdev_state_get_format(sd_state, format->pad);
1827 *fmt = format->format;
1829 int ret = tda1997x_setup_format(state, format->format.code);
1833 /* mbus_code has changed - re-configure csc/vidout */
1845 v4l_dbg(1, debug, state->client, "%s pad=%d\n", __func__, edid->pad);
1846 memset(edid->reserved, 0, sizeof(edid->reserved));
1848 if (edid->start_block == 0 && edid->blocks == 0) {
1849 edid->blocks = state->edid.blocks;
1853 if (!state->edid.present)
1854 return -ENODATA;
1856 if (edid->start_block >= state->edid.blocks)
1857 return -EINVAL;
1859 if (edid->start_block + edid->blocks > state->edid.blocks)
1860 edid->blocks = state->edid.blocks - edid->start_block;
1862 memcpy(edid->edid, state->edid.edid + edid->start_block * 128,
1863 edid->blocks * 128);
1873 v4l_dbg(1, debug, state->client, "%s pad=%d\n", __func__, edid->pad);
1874 memset(edid->reserved, 0, sizeof(edid->reserved));
1876 if (edid->start_block != 0)
1877 return -EINVAL;
1879 if (edid->blocks == 0) {
1880 state->edid.blocks = 0;
1881 state->edid.present = 0;
1886 if (edid->blocks > 2) {
1887 edid->blocks = 2;
1888 return -E2BIG;
1895 io_write(sd, REG_EDID_IN_BYTE0 + i, edid->edid[i]);
1899 io_write(sd, REG_EDID_IN_BYTE128 + i, edid->edid[i+128]);
1902 memcpy(state->edid.edid, edid->edid, 256);
1903 state->edid.blocks = edid->blocks;
1937 /* -----------------------------------------------------------------------------
1953 v4l_err(state->client,
1958 hdmi_infoframe_log(KERN_INFO, &state->client->dev, &frame);
1967 struct hdmi_avi_infoframe *avi = &state->avi_infoframe;
1969 v4l2_info(sd, "-----Chip status-----\n");
1970 v4l2_info(sd, "Chip: %s N%d\n", state->info->name,
1971 state->chip_revision + 1);
1972 v4l2_info(sd, "EDID Enabled: %s\n", state->edid.present ? "yes" : "no");
1974 v4l2_info(sd, "-----Signal status-----\n");
1980 v4l2_info(sd, "-----Video Timings-----\n");
1982 case -ENOLINK:
1985 case -ERANGE:
1989 v4l2_print_dv_timings(sd->name, "Configured format: ",
1990 &state->timings, true);
1992 v4l2_info(sd, "-----Color space-----\n");
1994 hdmi_colorspace_names[avi->colorspace],
1995 (avi->colorspace == HDMI_COLORSPACE_RGB) ? "" :
1996 hdmi_colorimetry_names[avi->colorimetry],
1997 v4l2_quantization_names[state->colorimetry.quantization]);
1999 vidfmt_names[state->vid_fmt]);
2000 v4l2_info(sd, "Color space conversion: %s", state->conv ?
2001 state->conv->name : "None");
2003 v4l2_info(sd, "-----Audio-----\n");
2004 if (state->audio_channels) {
2005 v4l2_info(sd, "audio: %dch %dHz\n", state->audio_channels,
2006 state->audio_samplerate);
2011 v4l2_info(sd, "-----Infoframes-----\n");
2023 switch (sub->type) {
2029 return -EINVAL;
2039 /* -----------------------------------------------------------------------------
2053 /* -----------------------------------------------------------------------------
2062 switch (ctrl->id) {
2065 state->rgb_quantization_range = ctrl->val;
2071 return -EINVAL;
2079 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
2080 ctrl->val = state->avi_infoframe.content_type;
2083 return -EINVAL;
2094 struct tda1997x_platform_data *pdata = &state->pdata;
2100 if (state->chip_revision == 0) {
2105 /* reset infoframe at end of start-up-sequencer */
2109 /* Enable TMDS pull-ups */
2165 if (state->chip_revision == 0)
2169 if (state->chip_revision == 0)
2180 if (state->chip_revision == 0)
2200 /* reset start-up-sequencer to force format detection */
2213 v4l_dbg(1, debug, state->client, "vidout_cfg[%d]=0x%02x\n", i,
2214 pdata->vidout_port_cfg[i]);
2215 io_write(sd, REG_VP35_32_CTRL + i, pdata->vidout_port_cfg[i]);
2222 switch (pdata->audout_mclk_fs) {
2254 state->hdmi_status = io_read(sd, REG_HDMI_FLAGS);
2266 state->supplies);
2270 state->supplies);
2292 struct tda1997x_platform_data *pdata = &state->pdata;
2303 * - HREF: active high from start to end of row
2304 * - VS: Vertical Sync active high at beginning of frame
2305 * - DE: Active high when data valid
2306 * - A_CLK: 128*Fs
2308 pdata->vidout_sel_hs = HS_HREF_SEL_HREF_VHREF;
2309 pdata->vidout_sel_vs = VS_VREF_SEL_VREF_HDMI;
2310 pdata->vidout_sel_de = DE_FREF_SEL_DE_VHREF;
2312 np = state->client->dev.of_node;
2313 ep = of_graph_get_endpoint_by_regs(np, 0, -1);
2315 return -EINVAL;
2322 pdata->vidout_bus_type = bus_cfg.bus_type;
2324 /* polarity of HS/VS/DE */
2327 pdata->vidout_inv_hs = 1;
2329 pdata->vidout_inv_vs = 1;
2331 pdata->vidout_inv_de = 1;
2332 pdata->vidout_bus_width = bus_cfg.bus.parallel.bus_width;
2335 ret = of_property_count_u32_elems(np, "nxp,vidout-portcfg");
2340 of_property_read_u32_index(np, "nxp,vidout-portcfg",
2342 of_property_read_u32_index(np, "nxp,vidout-portcfg",
2345 pdata->vidout_port_cfg[reg] = val;
2348 v4l_err(state->client, "nxp,vidout-portcfg missing\n");
2349 return -EINVAL;
2353 pdata->audout_layoutauto = true;
2355 pdata->audout_format = AUDFMT_TYPE_DISABLED;
2356 if (!of_property_read_string(np, "nxp,audout-format", &str)) {
2358 pdata->audout_format = AUDFMT_TYPE_I2S;
2360 pdata->audout_format = AUDFMT_TYPE_SPDIF;
2362 v4l_err(state->client, "nxp,audout-format invalid\n");
2363 return -EINVAL;
2365 if (!of_property_read_u32(np, "nxp,audout-layout", &v)) {
2371 v4l_err(state->client,
2372 "nxp,audout-layout invalid\n");
2373 return -EINVAL;
2375 pdata->audout_layout = v;
2377 if (!of_property_read_u32(np, "nxp,audout-width", &v)) {
2383 v4l_err(state->client,
2384 "nxp,audout-width invalid\n");
2385 return -EINVAL;
2387 pdata->audout_width = v;
2389 if (!of_property_read_u32(np, "nxp,audout-mclk-fs", &v)) {
2399 v4l_err(state->client,
2400 "nxp,audout-mclk-fs invalid\n");
2401 return -EINVAL;
2403 pdata->audout_mclk_fs = v;
2415 state->supplies[i].supply = tda1997x_supply_name[i];
2417 return devm_regulator_bulk_get(&state->client->dev,
2419 state->supplies);
2424 struct v4l2_subdev *sd = &state->sd;
2430 state->tmdsb_clk = (reg >> 6) & 0x01; /* use tmds clock B_inv for B */
2431 state->tmdsb_soc = (reg >> 5) & 0x01; /* tmds of input B */
2432 state->port_30bit = (reg >> 2) & 0x03; /* 30bit vs 24bit */
2433 state->output_2p5 = (reg >> 1) & 0x01; /* output supply 2.5v */
2443 dev_err(&state->client->dev, "unsupported chip ID\n");
2444 return -EIO;
2446 if (state->info->type != type) {
2447 dev_err(&state->client->dev, "chip id mismatch\n");
2448 return -EIO;
2452 state->chip_revision = io_read(sd, REG_CMTP_REG11);
2462 /* -----------------------------------------------------------------------------
2466 /* refine sample-rate based on HDMI source */
2472 struct snd_soc_component *component = dai->component;
2473 struct snd_pcm_runtime *rtd = substream->runtime;
2476 rate = state->audio_samplerate;
2480 dev_err(component->dev, "failed to constrain samplerate to %dHz\n",
2484 dev_info(component->dev, "set samplerate constraint to %dHz\n", rate);
2538 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2539 return -EIO;
2543 return -ENOMEM;
2545 state->client = client;
2546 pdata = &state->pdata;
2547 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2550 oid = of_match_node(tda1997x_of_id, client->dev.of_node);
2551 state->info = oid->data;
2558 } else if (client->dev.platform_data) {
2560 client->dev.platform_data;
2561 state->info =
2562 (const struct tda1997x_chip_info *)id->driver_data;
2563 state->pdata = *pdata;
2566 ret = -ENODEV;
2578 mutex_init(&state->page_lock);
2579 mutex_init(&state->lock);
2580 state->page = 0xff;
2582 INIT_DELAYED_WORK(&state->delayed_work_enable_hpd,
2591 sd = &state->sd;
2593 sd->internal_ops = &tda1997x_internal_ops;
2594 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2595 id->name, i2c_adapter_id(client->adapter),
2596 client->addr);
2597 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
2598 sd->entity.function = MEDIA_ENT_F_DV_DECODER;
2599 sd->entity.ops = &tda1997x_media_ops;
2601 /* set allowed mbus modes based on chip, bus-type, and bus-width */
2603 mbus_codes = state->mbus_codes;
2604 switch (state->info->type) {
2606 switch (pdata->vidout_bus_type) {
2608 switch (pdata->vidout_bus_width) {
2619 switch (pdata->vidout_bus_width) {
2634 switch (pdata->vidout_bus_type) {
2636 switch (pdata->vidout_bus_width) {
2651 switch (pdata->vidout_bus_width) {
2671 if (WARN_ON(i > ARRAY_SIZE(state->mbus_codes))) {
2672 ret = -EINVAL;
2677 tda1997x_setup_format(state, state->mbus_codes[0]);
2678 state->timings = cea1920x1080;
2684 state->colorimetry.colorspace = V4L2_COLORSPACE_SRGB;
2685 state->colorimetry.quantization = V4L2_QUANTIZATION_FULL_RANGE;
2694 if (state->chip_revision != 0) {
2699 v4l_info(client, "NXP %s N%d detected\n", state->info->name,
2700 state->chip_revision + 1);
2702 pdata->vidout_bus_width,
2703 (pdata->vidout_bus_type == V4L2_MBUS_PARALLEL) ?
2706 if (pdata->audout_format) {
2708 pdata->audout_layout ? 2 : 8,
2709 audfmt_names[pdata->audout_format],
2710 pdata->audout_layout,
2711 pdata->audout_mclk_fs);
2715 state->client_cec = devm_i2c_new_dummy_device(&client->dev,
2716 client->adapter, ret);
2717 if (IS_ERR(state->client_cec)) {
2718 ret = PTR_ERR(state->client_cec);
2729 hdl = &state->hdl;
2736 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
2738 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2740 state->rgb_quantization_range_ctrl = v4l2_ctrl_new_std_menu(hdl,
2744 state->sd.ctrl_handler = hdl;
2745 if (hdl->error) {
2746 ret = hdl->error;
2752 state->pads[TDA1997X_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
2753 ret = media_entity_pads_init(&sd->entity, TDA1997X_NUM_PADS,
2754 state->pads);
2765 if (pdata->audout_format) {
2768 if (pdata->audout_width == 32)
2773 ret = devm_snd_soc_register_component(&state->client->dev,
2777 dev_err(&client->dev, "register audio codec failed\n");
2780 v4l_info(state->client, "registered audio codec\n");
2784 ret = devm_request_threaded_irq(&client->dev, client->irq,
2789 v4l_err(client, "irq%d reg failed: %d\n", client->irq, ret);
2796 media_entity_cleanup(&sd->entity);
2798 v4l2_ctrl_handler_free(&state->hdl);
2800 cancel_delayed_work(&state->delayed_work_enable_hpd);
2801 mutex_destroy(&state->page_lock);
2802 mutex_destroy(&state->lock);
2806 dev_err(&client->dev, "%s failed: %d\n", __func__, ret);
2815 struct tda1997x_platform_data *pdata = &state->pdata;
2817 if (pdata->audout_format) {
2818 mutex_destroy(&state->audio_lock);
2821 disable_irq(state->client->irq);
2825 media_entity_cleanup(&sd->entity);
2826 v4l2_ctrl_handler_free(&state->hdl);
2827 regulator_bulk_disable(TDA1997X_NUM_SUPPLIES, state->supplies);
2828 cancel_delayed_work_sync(&state->delayed_work_enable_hpd);
2829 mutex_destroy(&state->page_lock);
2830 mutex_destroy(&state->lock);