1 // SPDX-License-Identifier: GPL-2.0-only
3  * TC358746 - Parallel <-> CSI-2 Bridge
8  *  - Currently only 'Parallel-in -> CSI-out' mode is supported!
13 #include <linux/clk-provider.h>
19 #include <linux/phy/phy-mipi-dphy.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-mc.h>
29 /* 16-bit registers */
80 /* 32-bit registers */
257 /* Get n-th format for pad */
267 		if ((pad == TC358746_SOURCE && fmt->csi_format) ||  in tc358746_get_format_by_idx()
275 	return ERR_PTR(-EINVAL);  in tc358746_get_format_by_idx()
286 		if (pad == TC358746_SINK && fmt->code == code)  in tc358746_get_format_by_code()
289 		if (pad == TC358746_SOURCE && !fmt->csi_format)  in tc358746_get_format_by_code()
292 		if (fmt->code == code)  in tc358746_get_format_by_code()
296 	return ERR_PTR(-EINVAL);  in tc358746_get_format_by_code()
337 	/* 32-bit registers starting from CLW_DPHYCONTTX */  in tc358746_write()
340 	err = regmap_bulk_write(tc358746->regmap, reg, &val, count);  in tc358746_write()
342 		dev_err(tc358746->sd.dev,  in tc358746_write()
353 	/* 32-bit registers starting from CLW_DPHYCONTTX */  in tc358746_read()
357 	err = regmap_bulk_read(tc358746->regmap, reg, val, count);  in tc358746_read()
359 		dev_err(tc358746->sd.dev,  in tc358746_read()
407 	u8 post = tc358746->pll_post_div;  in tc358746_apply_pll_config()
408 	u16 pre = tc358746->pll_pre_div;  in tc358746_apply_pll_config()
409 	u16 mul = tc358746->pll_mul;  in tc358746_apply_pll_config()
421 	/* Pre-div and Multiplicator have a internal +1 logic */  in tc358746_apply_pll_config()
422 	val = PLL_PRD(pre - 1) | PLL_FBD(mul - 1);  in tc358746_apply_pll_config()
452 	source_bitrate = source_link_freq * fmt->bus_width;  in tc358746_calc_vb_size()
454 	csi_bitrate = tc358746->dphy_cfg.lanes * tc358746->pll_rate;  in tc358746_calc_vb_size()
456 	dev_dbg(tc358746->sd.dev,  in tc358746_calc_vb_size()
457 		"Fifo settings params: source-bitrate:%lu csi-bitrate:%lu",  in tc358746_calc_vb_size()
462 		return -EINVAL;  in tc358746_calc_vb_size()
476 		 * fifo-sz, image-width - in bits  in tc358746_calc_vb_size()
477 		 * sbr                  - source_bitrate in bits/s  in tc358746_calc_vb_size()
478 		 * csir                 - csi_bitrate in bits/s  in tc358746_calc_vb_size()
480 		 * image-width / csir >= (image-width - fifo-sz) / sbr  in tc358746_calc_vb_size()
481 		 * image-width * sbr / csir >= image-width - fifo-sz  in tc358746_calc_vb_size()
482 		 * fifo-sz >= image-width - image-width * sbr / csir; with n = csir/sbr  in tc358746_calc_vb_size()
483 		 * fifo-sz >= image-width - image-width / n  in tc358746_calc_vb_size()
487 		tmp = (mbusfmt->width * TC358746_VB_PRECISION) / n;  in tc358746_calc_vb_size()
488 		fifo_sz = mbusfmt->width - tmp;  in tc358746_calc_vb_size()
489 		fifo_sz *= fmt->bpp;  in tc358746_calc_vb_size()
493 	dev_dbg(tc358746->sd.dev,  in tc358746_calc_vb_size()
494 		"Found FIFO size[bits]:%u -> aligned to size[bits]:%u\n",  in tc358746_calc_vb_size()
498 		return -EINVAL;  in tc358746_calc_vb_size()
506 	struct v4l2_subdev *sd = &tc358746->sd;  in tc358746_apply_misc_config()
509 	struct device *dev = sd->dev;  in tc358746_apply_misc_config()
519 	fmt = tc358746_get_format_by_code(TC358746_SINK, mbusfmt->code);  in tc358746_apply_misc_config()
521 	source_pad = media_entity_remote_source_pad_unique(&sd->entity);  in tc358746_apply_misc_config()
523 		dev_err(dev, "Failed to get source pad of %s\n", sd->name);  in tc358746_apply_misc_config()
531 		/* Return -EINVAL in case of source_link_freq is 0 */  in tc358746_apply_misc_config()
532 		err = source_link_freq ?: -EINVAL;  in tc358746_apply_misc_config()
537 	val = PDFMT(fmt->pdformat);  in tc358746_apply_misc_config()
543 	val = PDATAF(fmt->pdataf);  in tc358746_apply_misc_config()
544 	dev_dbg(dev, "CONFCTL[PDATAF]: 0x%x\n", fmt->pdataf);  in tc358746_apply_misc_config()
562 	val = mbusfmt->width * fmt->bpp / 8;  in tc358746_apply_misc_config()
575 	return div64_u64((u64)cfg_val * clk_hz + time_base - 1, time_base);  in tc358746_cfg_to_cnt()
590 	struct phy_configure_opts_mipi_dphy *cfg = &tc358746->dphy_cfg;  in tc358746_apply_dphy_config()
591 	bool non_cont_clk = !!(tc358746->csi_vep.bus.mipi_csi2.flags &  in tc358746_apply_dphy_config()
593 	struct device *dev = tc358746->sd.dev;  in tc358746_apply_dphy_config()
599 	hs_byte_clk = cfg->hs_clk_rate / 8;  in tc358746_apply_dphy_config()
602 	val = tc358746_us_to_cnt(cfg->init, hf_clk) - 1;  in tc358746_apply_dphy_config()
608 	val = tc358746_ps_to_cnt(cfg->lpx, hs_byte_clk) - 1;  in tc358746_apply_dphy_config()
615 	val = tc358746_ps_to_cnt(cfg->clk_prepare, hs_byte_clk) - 1;  in tc358746_apply_dphy_config()
616 	val2 = tc358746_ps_to_cnt(cfg->clk_zero, hs_byte_clk) - 1;  in tc358746_apply_dphy_config()
626 	val = tc358746_ps_to_cnt(cfg->clk_trail, hs_byte_clk);  in tc358746_apply_dphy_config()
632 	val = tc358746_ps_to_cnt(cfg->hs_prepare, hs_byte_clk) - 1;  in tc358746_apply_dphy_config()
633 	val2 = tc358746_ps_to_cnt(cfg->hs_zero, hs_byte_clk) - 1;  in tc358746_apply_dphy_config()
644 	val = tc358746_us_to_cnt(cfg->wakeup, hs_byte_clk);  in tc358746_apply_dphy_config()
645 	val = val / (lptxcnt + 1) - 1;  in tc358746_apply_dphy_config()
651 	val = tc358746_ps_to_cnt(cfg->clk_post, hs_byte_clk);  in tc358746_apply_dphy_config()
657 	val = tc358746_ps_to_cnt(cfg->hs_trail, hs_byte_clk);  in tc358746_apply_dphy_config()
672 	unsigned int lanes = tc358746->dphy_cfg.lanes;  in tc358746_enable_csi_lanes()
678 				   lanes - 1);  in tc358746_enable_csi_lanes()
684 	dev_dbg(tc358746->sd.dev, "CLW_CNTRL: 0x%x\n", val);  in tc358746_enable_csi_lanes()
694 		dev_dbg(tc358746->sd.dev, "D%uW_CNTRL: 0x%x\n", lane, val);  in tc358746_enable_csi_lanes()
710 	dev_dbg(tc358746->sd.dev, "HSTXVREGEN: 0x%x\n", val);  in tc358746_enable_csi_lanes()
717 	unsigned int lanes = tc358746->dphy_cfg.lanes;  in tc358746_enable_csi_module()
722 	 * required to put the lane state back into LP-11 state. The sw reset  in tc358746_enable_csi_module()
740 			      DATA(CSI_MODE | TXHSMD | NOL(lanes - 1)));  in tc358746_enable_csi_module()
772 	return media_entity_to_v4l2_subdev(pad->entity);  in tc358746_get_remote_sd()
781 	dev_dbg(sd->dev, "%sable\n", enable ? "en" : "dis");  in tc358746_s_stream()
783 	src = tc358746_get_remote_sd(&tc358746->pads[TC358746_SINK]);  in tc358746_s_stream()
785 		return -EPIPE;  in tc358746_s_stream()
788 		err = pm_runtime_resume_and_get(sd->dev);  in tc358746_s_stream()
819 		pm_runtime_put_sync_autosuspend(sd->dev);  in tc358746_s_stream()
826 	 * LP-11 state is entered correctly.  in tc358746_s_stream()
840 	pm_runtime_put_sync_autosuspend(sd->dev);  in tc358746_s_stream()
855 	fmt->code = tc358746_src_mbus_code(tc358746_def_fmt.code);  in tc358746_init_state()
866 	fmt = tc358746_get_format_by_idx(code->pad, code->index);  in tc358746_enum_mbus_code()
870 	code->code = fmt->code;  in tc358746_enum_mbus_code()
883 	if (format->pad == TC358746_SOURCE)  in tc358746_set_fmt()
888 	fmt = tc358746_get_format_by_code(format->pad, format->format.code);  in tc358746_set_fmt()
890 		fmt = tc358746_get_format_by_code(format->pad, tc358746_def_fmt.code);  in tc358746_set_fmt()
893 			return -EINVAL;  in tc358746_set_fmt()
896 	format->format.code = fmt->code;  in tc358746_set_fmt()
897 	format->format.field = V4L2_FIELD_NONE;  in tc358746_set_fmt()
899 	dev_dbg(sd->dev, "Update format: %ux%u code:0x%x -> %ux%u code:0x%x",  in tc358746_set_fmt()
900 		sink_fmt->width, sink_fmt->height, sink_fmt->code,  in tc358746_set_fmt()
901 		format->format.width, format->format.height, format->format.code);  in tc358746_set_fmt()
903 	*sink_fmt = format->format;  in tc358746_set_fmt()
907 	src_fmt->code = tc358746_src_mbus_code(sink_fmt->code);  in tc358746_set_fmt()
917 	struct device *dev = tc358746->sd.dev;  in tc358746_find_pll_settings()
927 		dev_err(dev, "HS-Clock above 1 Ghz are not supported\n");  in tc358746_find_pll_settings()
956 		delta = abs(fout - tmp);  in tc358746_find_pll_settings()
973 	tc358746->pll_post_div = postdiv;  in tc358746_find_pll_settings()
974 	tc358746->pll_pre_div = p_best;  in tc358746_find_pll_settings()
975 	tc358746->pll_mul = m_best;  in tc358746_find_pll_settings()
993 		return -EINVAL;  in tc358746_get_mbus_config()
995 	config->type = V4L2_MBUS_CSI2_DPHY;  in tc358746_get_mbus_config()
996 	config->bus.mipi_csi2 = tc358746->csi_vep.bus.mipi_csi2;  in tc358746_get_mbus_config()
1008 	/* 32-bit registers starting from CLW_DPHYCONTTX */  in tc358746_g_register()
1009 	reg->size = reg->reg < CLW_DPHYCONTTX_REG ? 2 : 4;  in tc358746_g_register()
1011 	if (!pm_runtime_get_if_in_use(sd->dev))  in tc358746_g_register()
1014 	err = tc358746_read(tc358746, reg->reg, &val);  in tc358746_g_register()
1015 	reg->val = val;  in tc358746_g_register()
1017 	pm_runtime_put_sync_autosuspend(sd->dev);  in tc358746_g_register()
1027 	if (!pm_runtime_get_if_in_use(sd->dev))  in tc358746_s_register()
1030 	tc358746_write(tc358746, (u32)reg->reg, (u32)reg->val);  in tc358746_s_register()
1032 	pm_runtime_put_sync_autosuspend(sd->dev);  in tc358746_s_register()
1078 	div = tc358746->mclk_postdiv / 2;  in tc358746_mclk_enable()
1079 	val = MCLK_HIGH(div - 1) | MCLK_LOW(div - 1);  in tc358746_mclk_enable()
1080 	dev_dbg(tc358746->sd.dev, "MCLKCTL: %u (0x%x)\n", val, val);  in tc358746_mclk_enable()
1085 	if (tc358746->mclk_prediv == 8)  in tc358746_mclk_enable()
1087 	else if (tc358746->mclk_prediv == 4)  in tc358746_mclk_enable()
1092 	dev_dbg(tc358746->sd.dev, "CLKCTL[MCLKDIV]: %u (0x%x)\n", val, val);  in tc358746_mclk_enable()
1107 	unsigned long pll_rate = tc358746->pll_rate;  in tc358746_find_mclk_settings()
1110 	struct device *dev = tc358746->sd.dev;  in tc358746_find_mclk_settings()
1116 	 *                          MCLK-Div  in tc358746_find_mclk_settings()
1117 	 *           -------------------´`---------------------  in tc358746_find_mclk_settings()
1119 	 *         +-------------+     +------------------------+  in tc358746_find_mclk_settings()
1120 	 *         | MCLK-PreDiv |     |       MCLK-PostDiv     |  in tc358746_find_mclk_settings()
1121 	 * PLL --> |   (2/4/8)   | --> | (mclk_low + mclk_high) | --> MCLK  in tc358746_find_mclk_settings()
1122 	 *         +-------------+     +------------------------+  in tc358746_find_mclk_settings()
1125 	 *   mclk_low/high = 1   --> 2 MCLK-Ref Counts  in tc358746_find_mclk_settings()
1126 	 *   mclk_low/high = 255 --> 256 MCLK-Ref Counts == max.  in tc358746_find_mclk_settings()
1132 	 *   MCLK = PLL / (MCLK-PreDiv * 2 * MCLK-PostDiv)  in tc358746_find_mclk_settings()
1135 	if (mclk_rate == tc358746->mclk_rate)  in tc358746_find_mclk_settings()
1175 	/* The MCLK <-> PLL gap is to high -> use largest possible div */  in tc358746_find_mclk_settings()
1181 	tc358746->mclk_prediv = mclk_prediv;  in tc358746_find_mclk_settings()
1182 	tc358746->mclk_postdiv = mclk_postdiv;  in tc358746_find_mclk_settings()
1183 	tc358746->mclk_rate = best_mclk_rate;  in tc358746_find_mclk_settings()
1222 	return tc358746->pll_rate / (prediv * postdiv);  in tc358746_recalc_rate()
1230 	*parent_rate = tc358746->pll_rate;  in tc358746_mclk_round_rate()
1256 	struct device *dev = tc358746->sd.dev;  in tc358746_setup_mclk_provider()
1261 	if (!device_property_present(dev, "#clock-cells"))  in tc358746_setup_mclk_provider()
1265 	tc358746->mclk_postdiv = 512;  in tc358746_setup_mclk_provider()
1266 	tc358746->mclk_prediv = 8;  in tc358746_setup_mclk_provider()
1268 	mclk_name = "tc358746-mclk";  in tc358746_setup_mclk_provider()
1269 	device_property_read_string(dev, "clock-output-names", &mclk_name);  in tc358746_setup_mclk_provider()
1273 	tc358746->mclk_hw.init = &mclk_initdata;  in tc358746_setup_mclk_provider()
1275 	err = devm_clk_hw_register(dev, &tc358746->mclk_hw);  in tc358746_setup_mclk_provider()
1282 					  &tc358746->mclk_hw);  in tc358746_setup_mclk_provider()
1292 	struct v4l2_subdev *sd = &tc358746->sd;  in tc358746_init_subdev()
1296 	sd->internal_ops = &tc358746_internal_ops;  in tc358746_init_subdev()
1297 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;  in tc358746_init_subdev()
1298 	sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;  in tc358746_init_subdev()
1299 	sd->entity.ops = &tc358746_entity_ops;  in tc358746_init_subdev()
1301 	tc358746->pads[TC358746_SINK].flags = MEDIA_PAD_FL_SINK;  in tc358746_init_subdev()
1302 	tc358746->pads[TC358746_SOURCE].flags = MEDIA_PAD_FL_SOURCE;  in tc358746_init_subdev()
1303 	err = media_entity_pads_init(&sd->entity, TC358746_NR_PADS,  in tc358746_init_subdev()
1304 				     tc358746->pads);  in tc358746_init_subdev()
1310 		media_entity_cleanup(&sd->entity);  in tc358746_init_subdev()
1318 	struct device *dev = tc358746->sd.dev;  in tc358746_init_output_port()
1321 	struct fwnode_handle *ep;  in tc358746_init_output_port()  local
1325 	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), TC358746_SOURCE,  in tc358746_init_output_port()
1327 	if (!ep) {  in tc358746_init_output_port()
1329 		return -EINVAL;  in tc358746_init_output_port()
1332 	/* Currently we only support 'parallel in' -> 'csi out' */  in tc358746_init_output_port()
1333 	vep = &tc358746->csi_vep;  in tc358746_init_output_port()
1334 	vep->bus_type = V4L2_MBUS_CSI2_DPHY;  in tc358746_init_output_port()
1335 	err = v4l2_fwnode_endpoint_alloc_parse(ep, vep);  in tc358746_init_output_port()
1336 	fwnode_handle_put(ep);  in tc358746_init_output_port()
1342 	csi_lanes = vep->bus.mipi_csi2.num_data_lanes;  in tc358746_init_output_port()
1344 	    vep->nr_of_link_frequencies == 0) {  in tc358746_init_output_port()
1345 		dev_err(dev, "error: Invalid CSI-2 settings\n");  in tc358746_init_output_port()
1346 		err = -EINVAL;  in tc358746_init_output_port()
1351 	csi_link_rate = (unsigned long)vep->link_frequencies[0];  in tc358746_init_output_port()
1352 	tc358746->pll_rate = tc358746_find_pll_settings(tc358746, refclk,  in tc358746_init_output_port()
1354 	if (!tc358746->pll_rate) {  in tc358746_init_output_port()
1355 		err = -EINVAL;  in tc358746_init_output_port()
1359 	err = phy_mipi_dphy_get_default_config_for_hsclk(tc358746->pll_rate,  in tc358746_init_output_port()
1360 						csi_lanes, &tc358746->dphy_cfg);  in tc358746_init_output_port()
1374 	struct device *dev = tc358746->sd.dev;  in tc358746_init_hw()
1385 	 /* Ensure that CSI interface is put into LP-11 state */  in tc358746_init_hw()
1396 		return -ENODEV;  in tc358746_init_hw()
1401 		return -ENODEV;  in tc358746_init_hw()
1409 	u64 *link_frequencies = tc358746->csi_vep.link_frequencies;  in tc358746_init_controls()
1413 	err = v4l2_ctrl_handler_init(&tc358746->ctrl_hdl, 1);  in tc358746_init_controls()
1418 	 * The driver currently supports only one link-frequency, regardless of  in tc358746_init_controls()
1423 	ctrl = v4l2_ctrl_new_int_menu(&tc358746->ctrl_hdl, NULL,  in tc358746_init_controls()
1427 		ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;  in tc358746_init_controls()
1429 	err = tc358746->ctrl_hdl.error;  in tc358746_init_controls()
1431 		v4l2_ctrl_handler_free(&tc358746->ctrl_hdl);  in tc358746_init_controls()
1435 	tc358746->sd.ctrl_handler = &tc358746->ctrl_hdl;  in tc358746_init_controls()
1447 	struct media_pad *sink = &tc358746->pads[TC358746_SINK];  in tc358746_notify_bound()
1462 	struct fwnode_handle *ep;  in tc358746_async_register()  local
1465 	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(tc358746->sd.dev),  in tc358746_async_register()
1467 	if (!ep)  in tc358746_async_register()
1468 		return -ENOTCONN;  in tc358746_async_register()
1470 	err = v4l2_fwnode_endpoint_parse(ep, &vep);  in tc358746_async_register()
1472 		fwnode_handle_put(ep);  in tc358746_async_register()
1476 	v4l2_async_subdev_nf_init(&tc358746->notifier, &tc358746->sd);  in tc358746_async_register()
1477 	asd = v4l2_async_nf_add_fwnode_remote(&tc358746->notifier, ep,  in tc358746_async_register()
1479 	fwnode_handle_put(ep);  in tc358746_async_register()
1486 	tc358746->notifier.ops = &tc358746_notify_ops;  in tc358746_async_register()
1488 	err = v4l2_async_nf_register(&tc358746->notifier);  in tc358746_async_register()
1492 	err = v4l2_async_register_subdev(&tc358746->sd);  in tc358746_async_register()
1499 	v4l2_async_nf_unregister(&tc358746->notifier);  in tc358746_async_register()
1501 	v4l2_async_nf_cleanup(&tc358746->notifier);  in tc358746_async_register()
1508 	struct device *dev = &client->dev;  in tc358746_probe()
1514 	tc358746 = devm_kzalloc(&client->dev, sizeof(*tc358746), GFP_KERNEL);  in tc358746_probe()
1516 		return -ENOMEM;  in tc358746_probe()
1518 	tc358746->regmap = devm_regmap_init_i2c(client, &tc358746_regmap_config);  in tc358746_probe()
1519 	if (IS_ERR(tc358746->regmap))  in tc358746_probe()
1520 		return dev_err_probe(dev, PTR_ERR(tc358746->regmap),  in tc358746_probe()
1523 	tc358746->refclk = devm_clk_get(dev, "refclk");  in tc358746_probe()
1524 	if (IS_ERR(tc358746->refclk))  in tc358746_probe()
1525 		return dev_err_probe(dev, PTR_ERR(tc358746->refclk),  in tc358746_probe()
1528 	err = clk_prepare_enable(tc358746->refclk);  in tc358746_probe()
1533 	refclk = clk_get_rate(tc358746->refclk);  in tc358746_probe()
1534 	clk_disable_unprepare(tc358746->refclk);  in tc358746_probe()
1537 		return dev_err_probe(dev, -EINVAL, "Invalid refclk range\n");  in tc358746_probe()
1540 		tc358746->supplies[i].supply = tc358746_supplies[i];  in tc358746_probe()
1543 				      tc358746->supplies);  in tc358746_probe()
1547 	tc358746->reset_gpio = devm_gpiod_get_optional(dev, "reset",  in tc358746_probe()
1549 	if (IS_ERR(tc358746->reset_gpio))  in tc358746_probe()
1550 		return dev_err_probe(dev, PTR_ERR(tc358746->reset_gpio),  in tc358746_probe()
1551 				     "Failed to get reset-gpios\n");  in tc358746_probe()
1562 	 * Keep this order since we need the output port link-frequencies  in tc358746_probe()
1588 	dev_dbg(dev, "%s found @ 0x%x (%s)\n", client->name,  in tc358746_probe()
1589 		client->addr, client->adapter->name);  in tc358746_probe()
1597 	v4l2_ctrl_handler_free(&tc358746->ctrl_hdl);  in tc358746_probe()
1599 	v4l2_fwnode_endpoint_free(&tc358746->csi_vep);  in tc358746_probe()
1601 	v4l2_subdev_cleanup(&tc358746->sd);  in tc358746_probe()
1602 	media_entity_cleanup(&tc358746->sd.entity);  in tc358746_probe()
1613 	v4l2_ctrl_handler_free(&tc358746->ctrl_hdl);  in tc358746_remove()
1614 	v4l2_fwnode_endpoint_free(&tc358746->csi_vep);  in tc358746_remove()
1615 	v4l2_async_nf_unregister(&tc358746->notifier);  in tc358746_remove()
1616 	v4l2_async_nf_cleanup(&tc358746->notifier);  in tc358746_remove()
1618 	media_entity_cleanup(&sd->entity);  in tc358746_remove()
1620 	pm_runtime_disable(sd->dev);  in tc358746_remove()
1621 	pm_runtime_set_suspended(sd->dev);  in tc358746_remove()
1622 	pm_runtime_dont_use_autosuspend(sd->dev);  in tc358746_remove()
1632 	clk_prepare_enable(tc358746->refclk);  in tc358746_clk_enable()
1640 	clk_disable_unprepare(tc358746->refclk);  in tc358746_suspend()
1643 				     tc358746->supplies);  in tc358746_suspend()
1655 	gpiod_set_value(tc358746->reset_gpio, 1);  in tc358746_resume()
1658 				    tc358746->supplies);  in tc358746_resume()
1665 	gpiod_set_value(tc358746->reset_gpio, 0);  in tc358746_resume()
1667 	err = clk_prepare_enable(tc358746->refclk);  in tc358746_resume()
1675 	 * Enable the PLL here since it can be called by the clk-framework or by  in tc358746_resume()
1685 	clk_disable_unprepare(tc358746->refclk);  in tc358746_resume()
1688 			       tc358746->supplies);  in tc358746_resume()
1713 MODULE_DESCRIPTION("Toshiba TC358746 Parallel to CSI-2 bridge driver");