Lines Matching +full:0 +full:xd0
49 MODULE_PARM_DESC(debug, "Debug level (0-1)");
120 return reg < 0x20 && reg != 0x01 && reg != 0x0f && in saa711x_has_reg()
121 (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e; in saa711x_has_reg()
123 return reg < 0x20 && reg != 0x01 && reg != 0x0f && in saa711x_has_reg()
124 reg != 0x14 && reg != 0x18 && reg != 0x19 && in saa711x_has_reg()
125 reg != 0x1d && reg != 0x1e; in saa711x_has_reg()
128 if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f || in saa711x_has_reg()
129 reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) || in saa711x_has_reg()
130 reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) || in saa711x_has_reg()
131 reg == 0x82 || (reg >= 0x89 && reg <= 0x8e))) in saa711x_has_reg()
132 return 0; in saa711x_has_reg()
136 return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && reg < 0x20; in saa711x_has_reg()
138 return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) && in saa711x_has_reg()
139 reg != 0x5d && reg < 0x63; in saa711x_has_reg()
141 return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) && in saa711x_has_reg()
142 (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 && in saa711x_has_reg()
143 reg != 0x81 && reg < 0xf0; in saa711x_has_reg()
145 return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe); in saa711x_has_reg()
147 return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) && in saa711x_has_reg()
148 (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 && in saa711x_has_reg()
149 (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0; in saa711x_has_reg()
159 while (*regs != 0x00) { in saa711x_writeregs()
164 filled with 0 - seems better not to touch on they */ in saa711x_writeregs()
166 if (saa711x_write(sd, reg, data) < 0) in saa711x_writeregs()
169 v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg); in saa711x_writeregs()
172 return 0; in saa711x_writeregs()
186 R_01_INC_DELAY, 0x00, /* reserved */
189 R_02_INPUT_CNTL_1, 0xd0, /* FUSE=3, GUDL=2, MODE=0 */
190 R_03_INPUT_CNTL_2, 0x23, /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0,
191 * GAFIX=0, GAI1=256, GAI2=256 */
192 R_04_INPUT_CNTL_3, 0x00, /* GAI1=256 */
193 R_05_INPUT_CNTL_4, 0x00, /* GAI2=256 */
196 R_06_H_SYNC_START, 0xf3, /* HSB at 13(50Hz) / 17(60Hz)
198 R_07_H_SYNC_STOP, 0xe8, /* HSS seems to be needed to
200 R_08_SYNC_CNTL, 0xc8, /* AUFD=1, FSEL=1, EXFIL=0,
201 * VTRC=1, HPLL=0, VNOI=0 */
202 R_09_LUMA_CNTL, 0x01, /* BYPS=0, PREF=0, BPSS=0,
203 * VBLB=0, UPTCV=0, APER=1 */
204 R_0A_LUMA_BRIGHT_CNTL, 0x80,
205 R_0B_LUMA_CONTRAST_CNTL, 0x47, /* 0b - CONT=1.109 */
206 R_0C_CHROMA_SAT_CNTL, 0x40,
207 R_0D_CHROMA_HUE_CNTL, 0x00,
208 R_0E_CHROMA_CNTL_1, 0x01, /* 0e - CDTO=0, CSTD=0, DCCF=0,
209 * FCTC=0, CHBW=1 */
210 R_0F_CHROMA_GAIN_CNTL, 0x00, /* reserved */
211 R_10_CHROMA_CNTL_2, 0x48, /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */
212 R_11_MODE_DELAY_CNTL, 0x1c, /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1,
213 * OEYC=1, OEHV=1, VIPB=0, COLO=0 */
214 R_12_RT_SIGNAL_CNTL, 0x00, /* 12 - output control 2 */
215 R_13_RT_X_PORT_OUT_CNTL, 0x00, /* 13 - output control 3 */
216 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
217 R_15_VGATE_START_FID_CHG, 0x00,
218 R_16_VGATE_STOP, 0x00,
219 R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
221 0x00, 0x00
235 R_01_INC_DELAY, 0x08,
236 R_02_INPUT_CNTL_1, 0xc2,
237 R_03_INPUT_CNTL_2, 0x30,
238 R_04_INPUT_CNTL_3, 0x00,
239 R_05_INPUT_CNTL_4, 0x00,
240 R_06_H_SYNC_START, 0x89, /* Illegal value -119,
241 * min. value = -108 (0x94) */
242 R_07_H_SYNC_STOP, 0x0d,
243 R_08_SYNC_CNTL, 0x88, /* Not datasheet default.
244 * HTC = VTR mode, should be 0x98 */
245 R_09_LUMA_CNTL, 0x01,
246 R_0A_LUMA_BRIGHT_CNTL, 0x80,
247 R_0B_LUMA_CONTRAST_CNTL, 0x47,
248 R_0C_CHROMA_SAT_CNTL, 0x40,
249 R_0D_CHROMA_HUE_CNTL, 0x00,
250 R_0E_CHROMA_CNTL_1, 0x01,
251 R_0F_CHROMA_GAIN_CNTL, 0x2a,
252 R_10_CHROMA_CNTL_2, 0x08, /* Not datsheet default.
253 * VRLN enabled, should be 0x00 */
254 R_11_MODE_DELAY_CNTL, 0x0c,
255 R_12_RT_SIGNAL_CNTL, 0x07, /* Not datasheet default,
256 * should be 0x01 */
257 R_13_RT_X_PORT_OUT_CNTL, 0x00,
258 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
259 R_15_VGATE_START_FID_CHG, 0x00,
260 R_16_VGATE_STOP, 0x00,
261 R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
263 0x00, 0x00
273 R_01_INC_DELAY, 0x08,
274 R_02_INPUT_CNTL_1, 0xc0,
275 R_03_INPUT_CNTL_2, 0x33,
276 R_04_INPUT_CNTL_3, 0x00,
277 R_05_INPUT_CNTL_4, 0x00,
278 R_06_H_SYNC_START, 0xe9,
279 R_07_H_SYNC_STOP, 0x0d,
280 R_08_SYNC_CNTL, 0x98,
281 R_09_LUMA_CNTL, 0x01,
282 R_0A_LUMA_BRIGHT_CNTL, 0x80,
283 R_0B_LUMA_CONTRAST_CNTL, 0x47,
284 R_0C_CHROMA_SAT_CNTL, 0x40,
285 R_0D_CHROMA_HUE_CNTL, 0x00,
286 R_0E_CHROMA_CNTL_1, 0x01,
287 R_0F_CHROMA_GAIN_CNTL, 0x2a,
288 R_10_CHROMA_CNTL_2, 0x00,
289 R_11_MODE_DELAY_CNTL, 0x0c,
290 R_12_RT_SIGNAL_CNTL, 0x01,
291 R_13_RT_X_PORT_OUT_CNTL, 0x00,
292 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
293 R_15_VGATE_START_FID_CHG, 0x00,
294 R_16_VGATE_STOP, 0x00,
295 R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
297 0x00, 0x00
301 'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
307 R_01_INC_DELAY, 0x48, /* white peak control disabled */
308 R_03_INPUT_CNTL_2, 0x20, /* was 0x30. 0x20: long vertical blanking */
309 R_04_INPUT_CNTL_3, 0x90, /* analog gain set to 0 */
310 R_05_INPUT_CNTL_4, 0x90, /* analog gain set to 0 */
312 R_06_H_SYNC_START, 0xeb, /* horiz sync begin = -21 */
313 R_07_H_SYNC_STOP, 0xe0, /* horiz sync stop = -17 */
314 R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */
315 R_0A_LUMA_BRIGHT_CNTL, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */
316 R_0B_LUMA_CONTRAST_CNTL, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */
317 R_0C_CHROMA_SAT_CNTL, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */
318 R_0D_CHROMA_HUE_CNTL, 0x00,
319 R_0F_CHROMA_GAIN_CNTL, 0x00, /* use automatic gain */
320 R_10_CHROMA_CNTL_2, 0x06, /* chroma: active adaptive combfilter */
321 R_11_MODE_DELAY_CNTL, 0x00,
322 R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */
323 R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */
324 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
325 R_18_RAW_DATA_GAIN_CNTL, 0x40, /* gain 0x00 = nominal */
326 R_19_RAW_DATA_OFF_CNTL, 0x80,
327 R_1A_COLOR_KILL_LVL_CNTL, 0x77, /* recommended value */
328 R_1B_MISC_TVVCRDET, 0x42, /* recommended value */
329 R_1C_ENHAN_COMB_CTRL1, 0xa9, /* recommended value */
330 R_1D_ENHAN_COMB_CTRL2, 0x01, /* recommended value */
333 R_80_GLOBAL_CNTL_1, 0x0, /* No tasks enabled at init */
336 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset device */
337 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* set device programmed, all in operational mode */
338 0x00, 0x00
343 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */
344 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
345 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
346 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */
347 0x00, 0x00
353 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
354 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
356 R_15_VGATE_START_FID_CHG, 0x03,
357 R_16_VGATE_STOP, 0x11,
358 R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
360 R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */
361 R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */
363 R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */
366 R_90_A_TASK_HANDLING_CNTL, 0x80,
367 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
368 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
369 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
371 /* hoffset low (input), 0x0002 is minimum */
372 R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
373 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
375 /* hsize low (input), 0x02d0 = 720 */
376 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
377 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
379 R_98_A_VERT_INPUT_WINDOW_START, 0x05,
380 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
382 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
383 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
385 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
386 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,
388 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
389 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
392 R_C0_B_TASK_HANDLING_CNTL, 0x00,
393 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
394 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
395 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
397 /* 0x0002 is minimum */
398 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
399 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
401 /* 0x02d0 = 720 */
402 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
403 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
405 /* vwindow start 0x12 = 18 */
406 R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
407 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
409 /* vwindow length 0xf8 = 248 */
413 /* hwindow 0x02d0 = 720 */
414 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
415 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
417 R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
418 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0 */
419 R_F5_PULSGEN_LINE_LENGTH, 0xad,
420 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
422 0x00, 0x00
426 R_80_GLOBAL_CNTL_1, 0x00,
427 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
429 R_15_VGATE_START_FID_CHG, 0x37, /* VGATE start */
430 R_16_VGATE_STOP, 0x16,
431 R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
433 R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */
434 R_0E_CHROMA_CNTL_1, 0x07,
436 R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */
439 R_90_A_TASK_HANDLING_CNTL, 0x81,
440 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
441 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
442 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
445 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
446 /* hoffset low (input), 0x0002 is minimum */
447 R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
448 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
450 /* hsize low (input), 0x02d0 = 720 */
451 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
452 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
454 R_98_A_VERT_INPUT_WINDOW_START, 0x03,
455 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
457 /* vsize 0x12 = 18 */
458 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
459 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
461 /* hsize 0x05a0 = 1440 */
462 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
463 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */
464 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */
465 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */
468 R_C0_B_TASK_HANDLING_CNTL, 0x00,
469 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
470 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
471 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
474 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
475 /* hoffset low (input), 0x0002 is minimum. See comment above. */
476 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
477 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
479 /* hsize 0x02d0 = 720 */
480 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
481 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
483 /* voffset 0x16 = 22 */
484 R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
485 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
487 /* vsize 0x0120 = 288 */
488 R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
489 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,
491 /* hsize 0x02d0 = 720 */
492 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
493 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
495 R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
496 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0, (was 0x05) */
497 R_F5_PULSGEN_LINE_LENGTH, 0xb0,
498 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
500 0x00, 0x00
506 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
507 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
508 R_80_GLOBAL_CNTL_1, 0x30, /* Activate both tasks */
509 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
510 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
512 0x00, 0x00
516 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
517 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
518 R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */
519 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
520 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
522 0x00, 0x00
527 R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
528 R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
529 R_84_I_PORT_SIGNAL_DEF, 0x20,
530 R_85_I_PORT_SIGNAL_POLAR, 0x21,
531 R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
532 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
535 R_A0_A_HORIZ_PRESCALING, 0x01,
536 R_A1_A_ACCUMULATION_LENGTH, 0x00,
537 R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
540 R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
541 R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
542 R_A6_A_CHROMA_SATURATION_CNTL, 0x40,
545 R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
546 R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,
548 R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,
551 R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
552 R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,
555 R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,
557 R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
558 R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,
560 R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
561 R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,
563 R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,
565 R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
566 R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
567 R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
568 R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,
570 R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
571 R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
572 R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
573 R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
576 R_D0_B_HORIZ_PRESCALING, 0x01,
577 R_D1_B_ACCUMULATION_LENGTH, 0x00,
578 R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
581 R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
582 R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
583 R_D6_B_CHROMA_SATURATION_CNTL, 0x40,
585 /* hor lum scaling 0x0400 = 1 */
586 R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
587 R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
589 R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,
592 R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
593 R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
596 R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,
598 R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
599 R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
601 R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
602 R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
604 R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,
606 R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
607 R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
608 R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
609 R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,
611 R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
612 R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
613 R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
614 R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,
616 R_F2_NOMINAL_PLL2_DTO, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */
617 R_F3_PLL_INCREMENT, 0x46,
618 R_F4_PLL2_STATUS, 0x00,
619 R_F7_PULSE_A_POS_MSB, 0x4b, /* not the recommended settings! */
620 R_F8_PULSE_B_POS, 0x00,
621 R_F9_PULSE_B_POS_MSB, 0x4b,
622 R_FA_PULSE_C_POS, 0x00,
623 R_FB_PULSE_C_POS_MSB, 0x4b,
626 R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
629 R_40_SLICER_CNTL_1, 0x20, /* No framing code errors allowed. */
630 R_41_LCR_BASE, 0xff,
631 R_41_LCR_BASE+1, 0xff,
632 R_41_LCR_BASE+2, 0xff,
633 R_41_LCR_BASE+3, 0xff,
634 R_41_LCR_BASE+4, 0xff,
635 R_41_LCR_BASE+5, 0xff,
636 R_41_LCR_BASE+6, 0xff,
637 R_41_LCR_BASE+7, 0xff,
638 R_41_LCR_BASE+8, 0xff,
639 R_41_LCR_BASE+9, 0xff,
640 R_41_LCR_BASE+10, 0xff,
641 R_41_LCR_BASE+11, 0xff,
642 R_41_LCR_BASE+12, 0xff,
643 R_41_LCR_BASE+13, 0xff,
644 R_41_LCR_BASE+14, 0xff,
645 R_41_LCR_BASE+15, 0xff,
646 R_41_LCR_BASE+16, 0xff,
647 R_41_LCR_BASE+17, 0xff,
648 R_41_LCR_BASE+18, 0xff,
649 R_41_LCR_BASE+19, 0xff,
650 R_41_LCR_BASE+20, 0xff,
651 R_41_LCR_BASE+21, 0xff,
652 R_41_LCR_BASE+22, 0xff,
653 R_58_PROGRAM_FRAMING_CODE, 0x40,
654 R_59_H_OFF_FOR_SLICER, 0x47,
655 R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
656 R_5D_DID, 0xbd,
657 R_5E_SDID, 0x35,
659 R_02_INPUT_CNTL_1, 0xc4, /* input tuner -> input 4, amplifier active */
661 R_80_GLOBAL_CNTL_1, 0x20, /* enable task B */
662 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
663 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
664 0x00, 0x00
679 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, in saa711x_decode_vps()
680 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, in saa711x_decode_vps()
681 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, in saa711x_decode_vps()
682 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, in saa711x_decode_vps()
683 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, in saa711x_decode_vps()
684 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, in saa711x_decode_vps()
685 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, in saa711x_decode_vps()
686 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, in saa711x_decode_vps()
687 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, in saa711x_decode_vps()
688 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, in saa711x_decode_vps()
689 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87, in saa711x_decode_vps()
690 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3, in saa711x_decode_vps()
691 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85, in saa711x_decode_vps()
692 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1, in saa711x_decode_vps()
693 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, in saa711x_decode_vps()
694 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, in saa711x_decode_vps()
695 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4, in saa711x_decode_vps()
696 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0, in saa711x_decode_vps()
697 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86, in saa711x_decode_vps()
698 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2, in saa711x_decode_vps()
699 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84, in saa711x_decode_vps()
700 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0, in saa711x_decode_vps()
701 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4, in saa711x_decode_vps()
702 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0, in saa711x_decode_vps()
703 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, in saa711x_decode_vps()
704 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, in saa711x_decode_vps()
705 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, in saa711x_decode_vps()
706 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, in saa711x_decode_vps()
707 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, in saa711x_decode_vps()
708 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, in saa711x_decode_vps()
709 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, in saa711x_decode_vps()
710 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, in saa711x_decode_vps()
713 u8 c, err = 0; in saa711x_decode_vps()
715 for (i = 0; i < 2 * 13; i += 2) { in saa711x_decode_vps()
717 c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4); in saa711x_decode_vps()
720 return err & 0xf0; in saa711x_decode_vps()
726 0, 0, 0, 1, 0, 1, 1, 1 in saa711x_decode_wss()
729 int wss = 0; in saa711x_decode_wss()
732 for (i = 0; i < 16; i++) { in saa711x_decode_wss()
757 u8 acc = 0; /* reg 0x3a, audio clock control */ in saa711x_s_clock_freq()
761 return 0; in saa711x_s_clock_freq()
783 acc = 0x80; in saa711x_s_clock_freq()
785 acc |= 0x40; in saa711x_s_clock_freq()
788 acc |= 0x08; in saa711x_s_clock_freq()
794 saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03); in saa711x_s_clock_freq()
795 saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10 << state->double_asclk); in saa711x_s_clock_freq()
798 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff); in saa711x_s_clock_freq()
800 (acpf >> 8) & 0xff); in saa711x_s_clock_freq()
802 (acpf >> 16) & 0x03); in saa711x_s_clock_freq()
804 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff); in saa711x_s_clock_freq()
805 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff); in saa711x_s_clock_freq()
806 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f); in saa711x_s_clock_freq()
808 return 0; in saa711x_s_clock_freq()
821 saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL) & 0x7f; in saa711x_g_volatile_ctrl()
824 return 0; in saa711x_g_volatile_ctrl()
854 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80); in saa711x_s_ctrl()
861 return 0; in saa711x_s_ctrl()
893 return 0; in saa711x_set_size()
900 (u8) (width & 0xff)); in saa711x_set_size()
902 (u8) ((width >> 8) & 0xff)); in saa711x_set_size()
913 (u8) (res & 0xff)); in saa711x_set_size()
915 (u8) ((res >> 8) & 0xff)); in saa711x_set_size()
920 /* 0 is not allowed (div. by zero) */ in saa711x_set_size()
926 (u8) (HPSC & 0x3f)); in saa711x_set_size()
928 v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC); in saa711x_set_size()
931 (u8) (HFSC & 0xff)); in saa711x_set_size()
933 (u8) ((HFSC >> 8) & 0xff)); in saa711x_set_size()
937 (u8) ((HFSC >> 1) & 0xff)); in saa711x_set_size()
939 (u8) ((HFSC >> 9) & 0xff)); in saa711x_set_size()
942 v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY); in saa711x_set_size()
952 (u8) (VSCY & 0xff)); in saa711x_set_size()
954 (u8) ((VSCY >> 8) & 0xff)); in saa711x_set_size()
957 (u8) (VSCY & 0xff)); in saa711x_set_size()
959 (u8) ((VSCY >> 8) & 0xff)); in saa711x_set_size()
965 saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20); in saa711x_set_size()
967 return 0; in saa711x_set_size()
1010 /* Register 0E - Bits D6-D4 on NO-AUTO mode in saa711x_set_v4lstd()
1021 u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f; in saa711x_set_v4lstd()
1024 reg |= 0x30; in saa711x_set_v4lstd()
1026 reg |= 0x20; in saa711x_set_v4lstd()
1028 reg |= 0x10; in saa711x_set_v4lstd()
1030 reg |= 0x40; in saa711x_set_v4lstd()
1032 reg |= 0x50; in saa711x_set_v4lstd()
1037 int taskb = saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10; in saa711x_set_v4lstd()
1066 for (i = 0; i <= 23; i++) in saa711x_set_lcr()
1067 lcr[i] = 0xff; in saa711x_set_lcr()
1073 lcr[i] = 0xdd; in saa711x_set_lcr()
1076 lcr[i] = 0xdd; in saa711x_set_lcr()
1081 for (i = 0; i <= 5; i++) in saa711x_set_lcr()
1082 fmt->service_lines[0][i] = in saa711x_set_lcr()
1083 fmt->service_lines[1][i] = 0; in saa711x_set_lcr()
1086 for (i = 0; i <= 9; i++) in saa711x_set_lcr()
1087 fmt->service_lines[0][i] = in saa711x_set_lcr()
1088 fmt->service_lines[1][i] = 0; in saa711x_set_lcr()
1090 fmt->service_lines[0][i] = in saa711x_set_lcr()
1091 fmt->service_lines[1][i] = 0; in saa711x_set_lcr()
1096 lcr[i] = 0; in saa711x_set_lcr()
1097 for (x = 0; x <= 1; x++) { in saa711x_set_lcr()
1099 case 0: in saa711x_set_lcr()
1100 lcr[i] |= 0xf << (4 * x); in saa711x_set_lcr()
1133 0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */ in saa711x_g_sliced_fmt()
1134 0, V4L2_SLICED_CAPTION_525, /* 4 */ in saa711x_g_sliced_fmt()
1135 V4L2_SLICED_WSS_625, 0, /* 5 */ in saa711x_g_sliced_fmt()
1136 V4L2_SLICED_VPS, 0, 0, 0, 0, /* 7 */ in saa711x_g_sliced_fmt()
1137 0, 0, 0, 0 in saa711x_g_sliced_fmt()
1141 memset(sliced->service_lines, 0, sizeof(sliced->service_lines)); in saa711x_g_sliced_fmt()
1142 sliced->service_set = 0; in saa711x_g_sliced_fmt()
1144 if (saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10) in saa711x_g_sliced_fmt()
1145 return 0; in saa711x_g_sliced_fmt()
1149 sliced->service_lines[0][i] = lcr2vbi[v >> 4]; in saa711x_g_sliced_fmt()
1150 sliced->service_lines[1][i] = lcr2vbi[v & 0xf]; in saa711x_g_sliced_fmt()
1152 sliced->service_lines[0][i] | sliced->service_lines[1][i]; in saa711x_g_sliced_fmt()
1154 return 0; in saa711x_g_sliced_fmt()
1160 return 0; in saa711x_s_raw_fmt()
1166 return 0; in saa711x_s_sliced_fmt()
1180 return 0; in saa711x_set_fmt()
1194 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0 in saa711x_decode_vbi_line()
1200 vbi->type = 0; /* mark result as a failure */ in saa711x_decode_vbi_line()
1205 id1 ^= 0x40; in saa711x_decode_vbi_line()
1212 vbi->is_second_field = ((id1 & 0x40) != 0); in saa711x_decode_vbi_line()
1213 vbi->line = (id1 & 0x3f) << 3; in saa711x_decode_vbi_line()
1214 vbi->line |= (id2 & 0x70) >> 4; in saa711x_decode_vbi_line()
1217 id2 &= 0xf; in saa711x_decode_vbi_line()
1220 the payload buffer with 0xa0 bytes. */ in saa711x_decode_vbi_line()
1222 return 0; in saa711x_decode_vbi_line()
1230 if (!saa711x_odd_parity(p[0]) || !saa711x_odd_parity(p[1])) in saa711x_decode_vbi_line()
1231 return 0; in saa711x_decode_vbi_line()
1237 return 0; in saa711x_decode_vbi_line()
1238 p[0] = wss & 0xff; in saa711x_decode_vbi_line()
1243 if (saa711x_decode_vps(p, p) != 0) in saa711x_decode_vbi_line()
1244 return 0; in saa711x_decode_vbi_line()
1250 return 0; in saa711x_decode_vbi_line()
1261 return 0; in saa711x_g_tuner()
1264 v4l2_dbg(1, debug, sd, "status: 0x%02x\n", status); in saa711x_g_tuner()
1265 vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0; in saa711x_g_tuner()
1266 return 0; in saa711x_g_tuner()
1273 state->radio = 0; in saa711x_s_std()
1275 return 0; in saa711x_s_std()
1283 return 0; in saa711x_s_radio()
1290 u8 mask = (state->ident <= SAA7111A) ? 0xf8 : 0xf0; in saa711x_s_routing()
1305 return 0; in saa711x_s_routing()
1317 (saa711x_read(sd, R_10_CHROMA_CNTL_2) & 0x3f) | in saa711x_s_routing()
1318 ((output & 0xc0) ^ 0x40)); in saa711x_s_routing()
1320 (saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL) & 0xf0) | in saa711x_s_routing()
1321 ((output & 2) ? 0x0a : 0)); in saa711x_s_routing()
1331 (saa711x_read(sd, R_09_LUMA_CNTL) & 0x7f) | in saa711x_s_routing()
1332 (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0)); in saa711x_s_routing()
1338 (saa711x_read(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK) & 0xfe) | in saa711x_s_routing()
1339 (state->output & 0x01)); in saa711x_s_routing()
1343 saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x20); in saa711x_s_routing()
1345 saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x21); in saa711x_s_routing()
1347 return 0; in saa711x_s_routing()
1356 saa711x_write(sd, 0x11, (saa711x_read(sd, 0x11) & 0x7f) | in saa711x_s_gpio()
1357 (val ? 0x80 : 0)); in saa711x_s_gpio()
1358 return 0; in saa711x_s_gpio()
1369 return 0; in saa711x_s_stream()
1372 return 0; in saa711x_s_stream()
1374 return 0; in saa711x_s_stream()
1389 return 0; in saa711x_s_crystal_freq()
1396 return 0; in saa711x_reset()
1402 so data->field 0 maps to the saa7115 even field, in saa711x_g_vbi_data()
1406 if (saa711x_read(sd, 0x6b) & 0xc0) in saa711x_g_vbi_data()
1408 data->data[0] = saa711x_read(sd, 0x6c); in saa711x_g_vbi_data()
1409 data->data[1] = saa711x_read(sd, 0x6d); in saa711x_g_vbi_data()
1410 return 0; in saa711x_g_vbi_data()
1412 if (data->field == 0) { in saa711x_g_vbi_data()
1414 if (saa711x_read(sd, 0x66) & 0x30) in saa711x_g_vbi_data()
1416 data->data[0] = saa711x_read(sd, 0x69); in saa711x_g_vbi_data()
1417 data->data[1] = saa711x_read(sd, 0x6a); in saa711x_g_vbi_data()
1418 return 0; in saa711x_g_vbi_data()
1421 if (saa711x_read(sd, 0x66) & 0xc0) in saa711x_g_vbi_data()
1423 data->data[0] = saa711x_read(sd, 0x67); in saa711x_g_vbi_data()
1424 data->data[1] = saa711x_read(sd, 0x68); in saa711x_g_vbi_data()
1425 return 0; in saa711x_g_vbi_data()
1447 v4l2_dbg(1, debug, sd, "Status byte 1 (0x1e)=0x%02x\n", reg1e); in saa711x_querystd()
1449 switch (reg1e & 0x03) { in saa711x_querystd()
1472 v4l2_dbg(1, debug, sd, "Status byte 2 (0x1f)=0x%02x\n", reg1f); in saa711x_querystd()
1475 if (reg1f & 0x40) { in saa711x_querystd()
1480 if (reg1f & 0x20) in saa711x_querystd()
1488 return 0; in saa711x_querystd()
1494 int reg1e = 0x80; in saa711x_g_input_status()
1501 if ((reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80) in saa711x_g_input_status()
1502 *status = 0; in saa711x_g_input_status()
1503 return 0; in saa711x_g_input_status()
1509 reg->val = saa711x_read(sd, reg->reg & 0xff); in saa711x_g_register()
1511 return 0; in saa711x_g_register()
1516 saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff); in saa711x_s_register()
1517 return 0; in saa711x_s_register()
1532 signalOk = (reg1f & 0xc1) == 0x81; in saa711x_log_status()
1534 v4l2_info(sd, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz"); in saa711x_log_status()
1535 return 0; in saa711x_log_status()
1542 signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80; in saa711x_log_status()
1543 vcr = !(reg1f & 0x10); in saa711x_log_status()
1550 v4l2_info(sd, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz"); in saa711x_log_status()
1552 switch (reg1e & 0x03) { in saa711x_log_status()
1568 return 0; in saa711x_log_status()
1716 for (i = 0; i < CHIP_VER_SIZE; i++) { in saa711x_detect_chip()
1717 i2c_smbus_write_byte_data(client, 0, i); in saa711x_detect_chip()
1718 chip_ver[i] = i2c_smbus_read_byte_data(client, 0); in saa711x_detect_chip()
1719 name[i] = (chip_ver[i] & 0x0f) + '0'; in saa711x_detect_chip()
1723 name[i] = '\0'; in saa711x_detect_chip()
1735 if (chip_ver[0] & 0xf0) { in saa711x_detect_chip()
1758 chip_id = 0; in saa711x_detect_chip()
1759 for (i = 0; i < 4; i++) { in saa711x_detect_chip()
1761 chip_id |= (chip_ver[i] & 0x80) ? 1 : 0; in saa711x_detect_chip()
1768 * version (reg 0x00) reads. So, we need to also in saa711x_detect_chip()
1769 * accept at least version 0. For now, let's just in saa711x_detect_chip()
1780 "It seems to be a %s chip (%*ph) @ 0x%x.\n", in saa711x_detect_chip()
1794 "It seems to be a %s chip (%*ph) @ 0x%x.\n", in saa711x_detect_chip()
1802 v4l_dbg(1, debug, client, "chip %*ph @ 0x%x is unknown.\n", in saa711x_detect_chip()
1831 if (ident < 0) in saa711x_probe()
1852 if (ret < 0) in saa711x_probe()
1856 v4l_info(client, "%s found @ 0x%x (%s)\n", name, in saa711x_probe()
1862 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); in saa711x_probe()
1864 V4L2_CID_CONTRAST, 0, 127, 1, 64); in saa711x_probe()
1866 V4L2_CID_SATURATION, 0, 127, 1, 64); in saa711x_probe()
1868 V4L2_CID_HUE, -128, 127, 1, 0); in saa711x_probe()
1870 V4L2_CID_CHROMA_AGC, 0, 1, 1, 1); in saa711x_probe()
1872 V4L2_CID_CHROMA_GAIN, 0, 127, 1, 40); in saa711x_probe()
1880 v4l2_ctrl_auto_cluster(2, &state->agc, 0, true); in saa711x_probe()
1885 state->radio = 0; in saa711x_probe()
1922 v4l2_dbg(1, debug, sd, "status: (1E) 0x%02x, (1F) 0x%02x\n", in saa711x_probe()
1925 return 0; in saa711x_probe()
1940 { "saa7111", 0 },
1941 { "saa7113", 0 },
1942 { "saa7114", 0 },
1943 { "saa7115", 0 },
1944 { "saa7118", 0 },
1945 { "gm7113c", 0 },