28 #define OV8865_SW_STANDBY_REG			0x100
29 #define OV8865_SW_STANDBY_STREAM_ON		BIT(0)
31 #define OV8865_SW_RESET_REG			0x103
32 #define OV8865_SW_RESET_RESET			BIT(0)
34 #define OV8865_PLL_CTRL0_REG			0x300
35 #define OV8865_PLL_CTRL0_PRE_DIV(v)		((v) & GENMASK(2, 0))
36 #define OV8865_PLL_CTRL1_REG			0x301
38 #define OV8865_PLL_CTRL2_REG			0x302
39 #define OV8865_PLL_CTRL2_MUL_L(v)		((v) & GENMASK(7, 0))
40 #define OV8865_PLL_CTRL3_REG			0x303
41 #define OV8865_PLL_CTRL3_M_DIV(v)		(((v) - 1) & GENMASK(3, 0))
42 #define OV8865_PLL_CTRL4_REG			0x304
43 #define OV8865_PLL_CTRL4_MIPI_DIV(v)		((v) & GENMASK(1, 0))
44 #define OV8865_PLL_CTRL5_REG			0x305
45 #define OV8865_PLL_CTRL5_SYS_PRE_DIV(v)		((v) & GENMASK(1, 0))
46 #define OV8865_PLL_CTRL6_REG			0x306
47 #define OV8865_PLL_CTRL6_SYS_DIV(v)		(((v) - 1) & BIT(0))
49 #define OV8865_PLL_CTRL8_REG			0x308
50 #define OV8865_PLL_CTRL9_REG			0x309
51 #define OV8865_PLL_CTRLA_REG			0x30a
52 #define OV8865_PLL_CTRLA_PRE_DIV_HALF(v)	(((v) - 1) & BIT(0))
53 #define OV8865_PLL_CTRLB_REG			0x30b
54 #define OV8865_PLL_CTRLB_PRE_DIV(v)		((v) & GENMASK(2, 0))
55 #define OV8865_PLL_CTRLC_REG			0x30c
57 #define OV8865_PLL_CTRLD_REG			0x30d
58 #define OV8865_PLL_CTRLD_MUL_L(v)		((v) & GENMASK(7, 0))
59 #define OV8865_PLL_CTRLE_REG			0x30e
60 #define OV8865_PLL_CTRLE_SYS_DIV(v)		((v) & GENMASK(2, 0))
61 #define OV8865_PLL_CTRLF_REG			0x30f
62 #define OV8865_PLL_CTRLF_SYS_PRE_DIV(v)		(((v) - 1) & GENMASK(3, 0))
63 #define OV8865_PLL_CTRL10_REG			0x310
64 #define OV8865_PLL_CTRL11_REG			0x311
65 #define OV8865_PLL_CTRL12_REG			0x312
67 #define OV8865_PLL_CTRL12_DAC_DIV(v)		(((v) - 1) & GENMASK(3, 0))
69 #define OV8865_PLL_CTRL1B_REG			0x31b
70 #define OV8865_PLL_CTRL1C_REG			0x31c
72 #define OV8865_PLL_CTRL1E_REG			0x31e
75 #define OV8865_PAD_OEN0_REG			0x3000
77 #define OV8865_PAD_OEN2_REG			0x3002
79 #define OV8865_CLK_RST5_REG			0x3005
81 #define OV8865_CHIP_ID_HH_REG			0x300a
82 #define OV8865_CHIP_ID_HH_VALUE			0x00
83 #define OV8865_CHIP_ID_H_REG			0x300b
84 #define OV8865_CHIP_ID_H_VALUE			0x88
85 #define OV8865_CHIP_ID_L_REG			0x300c
86 #define OV8865_CHIP_ID_L_VALUE			0x65
87 #define OV8865_PAD_OUT2_REG			0x300d
89 #define OV8865_PAD_SEL2_REG			0x3010
90 #define OV8865_PAD_PK_REG			0x3011
91 #define OV8865_PAD_PK_DRIVE_STRENGTH_1X		(0 << 5)
96 #define OV8865_PUMP_CLK_DIV_REG			0x3015
98 #define OV8865_PUMP_CLK_DIV_PUMP_P(v)		((v) & GENMASK(2, 0))
100 #define OV8865_MIPI_SC_CTRL0_REG		0x3018
105 #define OV8865_MIPI_SC_CTRL0_LANES_PD_MIPI	BIT(0)
106 #define OV8865_MIPI_SC_CTRL1_REG		0x3019
107 #define OV8865_CLK_RST0_REG			0x301a
108 #define OV8865_CLK_RST1_REG			0x301b
109 #define OV8865_CLK_RST2_REG			0x301c
110 #define OV8865_CLK_RST3_REG			0x301d
111 #define OV8865_CLK_RST4_REG			0x301e
113 #define OV8865_PCLK_SEL_REG			0x3020
117 #define OV8865_MISC_CTRL_REG			0x3021
118 #define OV8865_MIPI_SC_CTRL2_REG		0x3022
120 #define OV8865_MIPI_SC_CTRL2_PD_MIPI_RST_SYNC	BIT(0)
122 #define OV8865_MIPI_BIT_SEL_REG			0x3031
123 #define OV8865_MIPI_BIT_SEL(v)			(((v) << 0) & GENMASK(4, 0))
124 #define OV8865_CLK_SEL0_REG			0x3032
126 #define OV8865_CLK_SEL1_REG			0x3033
132 #define OV8865_SCLK_CTRL_REG			0x3106
135 #define OV8865_SCLK_CTRL_UNKNOWN		BIT(0)
139 #define OV8865_EXPOSURE_CTRL_HH_REG		0x3500
141 #define OV8865_EXPOSURE_CTRL_H_REG		0x3501
143 #define OV8865_EXPOSURE_CTRL_L_REG		0x3502
144 #define OV8865_EXPOSURE_CTRL_L(v)		((v) & GENMASK(7, 0))
145 #define OV8865_EXPOSURE_GAIN_MANUAL_REG		0x3503
148 #define OV8865_GAIN_CTRL_H_REG			0x3508
150 #define OV8865_GAIN_CTRL_L_REG			0x3509
151 #define OV8865_GAIN_CTRL_L(v)			((v) & GENMASK(7, 0))
155 #define OV8865_CROP_START_X_H_REG		0x3800
157 #define OV8865_CROP_START_X_L_REG		0x3801
158 #define OV8865_CROP_START_X_L(v)		((v) & GENMASK(7, 0))
159 #define OV8865_CROP_START_Y_H_REG		0x3802
161 #define OV8865_CROP_START_Y_L_REG		0x3803
162 #define OV8865_CROP_START_Y_L(v)		((v) & GENMASK(7, 0))
163 #define OV8865_CROP_END_X_H_REG			0x3804
165 #define OV8865_CROP_END_X_L_REG			0x3805
166 #define OV8865_CROP_END_X_L(v)			((v) & GENMASK(7, 0))
167 #define OV8865_CROP_END_Y_H_REG			0x3806
169 #define OV8865_CROP_END_Y_L_REG			0x3807
170 #define OV8865_CROP_END_Y_L(v)			((v) & GENMASK(7, 0))
171 #define OV8865_OUTPUT_SIZE_X_H_REG		0x3808
173 #define OV8865_OUTPUT_SIZE_X_L_REG		0x3809
174 #define OV8865_OUTPUT_SIZE_X_L(v)		((v) & GENMASK(7, 0))
175 #define OV8865_OUTPUT_SIZE_Y_H_REG		0x380a
177 #define OV8865_OUTPUT_SIZE_Y_L_REG		0x380b
178 #define OV8865_OUTPUT_SIZE_Y_L(v)		((v) & GENMASK(7, 0))
179 #define OV8865_HTS_H_REG			0x380c
181 #define OV8865_HTS_L_REG			0x380d
182 #define OV8865_HTS_L(v)				((v) & GENMASK(7, 0))
183 #define OV8865_VTS_H_REG			0x380e
185 #define OV8865_VTS_L_REG			0x380f
186 #define OV8865_VTS_L(v)				((v) & GENMASK(7, 0))
187 #define OV8865_TIMING_MAX_VTS			0xffff
188 #define OV8865_TIMING_MIN_VTS			0x04
189 #define OV8865_OFFSET_X_H_REG			0x3810
191 #define OV8865_OFFSET_X_L_REG			0x3811
192 #define OV8865_OFFSET_X_L(v)			((v) & GENMASK(7, 0))
193 #define OV8865_OFFSET_Y_H_REG			0x3812
195 #define OV8865_OFFSET_Y_L_REG			0x3813
196 #define OV8865_OFFSET_Y_L(v)			((v) & GENMASK(7, 0))
197 #define OV8865_INC_X_ODD_REG			0x3814
198 #define OV8865_INC_X_ODD(v)			((v) & GENMASK(4, 0))
199 #define OV8865_INC_X_EVEN_REG			0x3815
200 #define OV8865_INC_X_EVEN(v)			((v) & GENMASK(4, 0))
201 #define OV8865_VSYNC_START_H_REG		0x3816
203 #define OV8865_VSYNC_START_L_REG		0x3817
204 #define OV8865_VSYNC_START_L(v)			((v) & GENMASK(7, 0))
205 #define OV8865_VSYNC_END_H_REG			0x3818
207 #define OV8865_VSYNC_END_L_REG			0x3819
208 #define OV8865_VSYNC_END_L(v)			((v) & GENMASK(7, 0))
209 #define OV8865_HSYNC_FIRST_H_REG		0x381a
211 #define OV8865_HSYNC_FIRST_L_REG		0x381b
212 #define OV8865_HSYNC_FIRST_L(v)			((v) & GENMASK(7, 0))
214 #define OV8865_FORMAT1_REG			0x3820
217 #define OV8865_FORMAT2_REG			0x3821
224 #define OV8865_FORMAT2_SYNC_HBIN_EN		BIT(0)
226 #define OV8865_INC_Y_ODD_REG			0x382a
227 #define OV8865_INC_Y_ODD(v)			((v) & GENMASK(4, 0))
228 #define OV8865_INC_Y_EVEN_REG			0x382b
229 #define OV8865_INC_Y_EVEN(v)			((v) & GENMASK(4, 0))
231 #define OV8865_ABLC_NUM_REG			0x3830
232 #define OV8865_ABLC_NUM(v)			((v) & GENMASK(4, 0))
234 #define OV8865_ZLINE_NUM_REG			0x3836
235 #define OV8865_ZLINE_NUM(v)			((v) & GENMASK(4, 0))
237 #define OV8865_AUTO_SIZE_CTRL_REG		0x3841
243 #define OV8865_AUTO_SIZE_CTRL_CROP_START_X_REG	BIT(0)
244 #define OV8865_AUTO_SIZE_X_OFFSET_H_REG		0x3842
245 #define OV8865_AUTO_SIZE_X_OFFSET_L_REG		0x3843
246 #define OV8865_AUTO_SIZE_Y_OFFSET_H_REG		0x3844
247 #define OV8865_AUTO_SIZE_Y_OFFSET_L_REG		0x3845
248 #define OV8865_AUTO_SIZE_BOUNDARIES_REG		0x3846
250 #define OV8865_AUTO_SIZE_BOUNDARIES_X(v)	((v) & GENMASK(3, 0))
254 #define OV8865_PSRAM_CTRL8_REG			0x3f08
258 #define OV8865_BLC_CTRL0_REG			0x4000
266 #define OV8865_BLC_CTRL0_FILTER_EN		BIT(0)
267 #define OV8865_BLC_CTRL1_REG			0x4001
270 #define OV8865_BLC_CTRL1_COL_SHIFT_256		(0 << 4)
276 #define OV8865_BLC_CTRL2_REG			0x4002
277 #define OV8865_BLC_CTRL3_REG			0x4003
278 #define OV8865_BLC_CTRL4_REG			0x4004
279 #define OV8865_BLC_CTRL5_REG			0x4005
280 #define OV8865_BLC_CTRL6_REG			0x4006
281 #define OV8865_BLC_CTRL7_REG			0x4007
282 #define OV8865_BLC_CTRL8_REG			0x4008
283 #define OV8865_BLC_CTRL9_REG			0x4009
284 #define OV8865_BLC_CTRLA_REG			0x400a
285 #define OV8865_BLC_CTRLB_REG			0x400b
286 #define OV8865_BLC_CTRLC_REG			0x400c
287 #define OV8865_BLC_CTRLD_REG			0x400d
288 #define OV8865_BLC_CTRLD_OFFSET_TRIGGER(v)	((v) & GENMASK(7, 0))
290 #define OV8865_BLC_CTRL1F_REG			0x401f
295 #define OV8865_BLC_ANCHOR_LEFT_START_H_REG	0x4020
297 #define OV8865_BLC_ANCHOR_LEFT_START_L_REG	0x4021
298 #define OV8865_BLC_ANCHOR_LEFT_START_L(v)	((v) & GENMASK(7, 0))
299 #define OV8865_BLC_ANCHOR_LEFT_END_H_REG	0x4022
301 #define OV8865_BLC_ANCHOR_LEFT_END_L_REG	0x4023
302 #define OV8865_BLC_ANCHOR_LEFT_END_L(v)		((v) & GENMASK(7, 0))
303 #define OV8865_BLC_ANCHOR_RIGHT_START_H_REG	0x4024
305 #define OV8865_BLC_ANCHOR_RIGHT_START_L_REG	0x4025
306 #define OV8865_BLC_ANCHOR_RIGHT_START_L(v)	((v) & GENMASK(7, 0))
307 #define OV8865_BLC_ANCHOR_RIGHT_END_H_REG	0x4026
309 #define OV8865_BLC_ANCHOR_RIGHT_END_L_REG	0x4027
310 #define OV8865_BLC_ANCHOR_RIGHT_END_L(v)	((v) & GENMASK(7, 0))
312 #define OV8865_BLC_TOP_ZLINE_START_REG		0x4028
313 #define OV8865_BLC_TOP_ZLINE_START(v)		((v) & GENMASK(5, 0))
314 #define OV8865_BLC_TOP_ZLINE_NUM_REG		0x4029
315 #define OV8865_BLC_TOP_ZLINE_NUM(v)		((v) & GENMASK(4, 0))
316 #define OV8865_BLC_TOP_BLKLINE_START_REG	0x402a
317 #define OV8865_BLC_TOP_BLKLINE_START(v)		((v) & GENMASK(5, 0))
318 #define OV8865_BLC_TOP_BLKLINE_NUM_REG		0x402b
319 #define OV8865_BLC_TOP_BLKLINE_NUM(v)		((v) & GENMASK(4, 0))
320 #define OV8865_BLC_BOT_ZLINE_START_REG		0x402c
321 #define OV8865_BLC_BOT_ZLINE_START(v)		((v) & GENMASK(5, 0))
322 #define OV8865_BLC_BOT_ZLINE_NUM_REG		0x402d
323 #define OV8865_BLC_BOT_ZLINE_NUM(v)		((v) & GENMASK(4, 0))
324 #define OV8865_BLC_BOT_BLKLINE_START_REG	0x402e
325 #define OV8865_BLC_BOT_BLKLINE_START(v)		((v) & GENMASK(5, 0))
326 #define OV8865_BLC_BOT_BLKLINE_NUM_REG		0x402f
327 #define OV8865_BLC_BOT_BLKLINE_NUM(v)		((v) & GENMASK(4, 0))
329 #define OV8865_BLC_OFFSET_LIMIT_REG		0x4034
330 #define OV8865_BLC_OFFSET_LIMIT(v)		((v) & GENMASK(7, 0))
334 #define OV8865_VFIFO_READ_START_H_REG		0x4600
336 #define OV8865_VFIFO_READ_START_L_REG		0x4601
337 #define OV8865_VFIFO_READ_START_L(v)		((v) & GENMASK(7, 0))
341 #define OV8865_MIPI_CTRL0_REG			0x4800
342 #define OV8865_MIPI_CTRL1_REG			0x4801
343 #define OV8865_MIPI_CTRL2_REG			0x4802
344 #define OV8865_MIPI_CTRL3_REG			0x4803
345 #define OV8865_MIPI_CTRL4_REG			0x4804
346 #define OV8865_MIPI_CTRL5_REG			0x4805
347 #define OV8865_MIPI_CTRL6_REG			0x4806
348 #define OV8865_MIPI_CTRL7_REG			0x4807
349 #define OV8865_MIPI_CTRL8_REG			0x4808
351 #define OV8865_MIPI_FCNT_MAX_H_REG		0x4810
352 #define OV8865_MIPI_FCNT_MAX_L_REG		0x4811
354 #define OV8865_MIPI_CTRL13_REG			0x4813
355 #define OV8865_MIPI_CTRL14_REG			0x4814
356 #define OV8865_MIPI_CTRL15_REG			0x4815
357 #define OV8865_MIPI_EMBEDDED_DT_REG		0x4816
359 #define OV8865_MIPI_HS_ZERO_MIN_H_REG		0x4818
360 #define OV8865_MIPI_HS_ZERO_MIN_L_REG		0x4819
361 #define OV8865_MIPI_HS_TRAIL_MIN_H_REG		0x481a
362 #define OV8865_MIPI_HS_TRAIL_MIN_L_REG		0x481b
363 #define OV8865_MIPI_CLK_ZERO_MIN_H_REG		0x481c
364 #define OV8865_MIPI_CLK_ZERO_MIN_L_REG		0x481d
365 #define OV8865_MIPI_CLK_PREPARE_MAX_REG		0x481e
366 #define OV8865_MIPI_CLK_PREPARE_MIN_REG		0x481f
367 #define OV8865_MIPI_CLK_POST_MIN_H_REG		0x4820
368 #define OV8865_MIPI_CLK_POST_MIN_L_REG		0x4821
369 #define OV8865_MIPI_CLK_TRAIL_MIN_H_REG		0x4822
370 #define OV8865_MIPI_CLK_TRAIL_MIN_L_REG		0x4823
371 #define OV8865_MIPI_LPX_P_MIN_H_REG		0x4824
372 #define OV8865_MIPI_LPX_P_MIN_L_REG		0x4825
373 #define OV8865_MIPI_HS_PREPARE_MIN_REG		0x4826
374 #define OV8865_MIPI_HS_PREPARE_MAX_REG		0x4827
375 #define OV8865_MIPI_HS_EXIT_MIN_H_REG		0x4828
376 #define OV8865_MIPI_HS_EXIT_MIN_L_REG		0x4829
377 #define OV8865_MIPI_UI_HS_ZERO_MIN_REG		0x482a
378 #define OV8865_MIPI_UI_HS_TRAIL_MIN_REG		0x482b
379 #define OV8865_MIPI_UI_CLK_ZERO_MIN_REG		0x482c
380 #define OV8865_MIPI_UI_CLK_PREPARE_REG		0x482d
381 #define OV8865_MIPI_UI_CLK_POST_MIN_REG		0x482e
382 #define OV8865_MIPI_UI_CLK_TRAIL_MIN_REG	0x482f
383 #define OV8865_MIPI_UI_LPX_P_MIN_REG		0x4830
384 #define OV8865_MIPI_UI_HS_PREPARE_REG		0x4831
385 #define OV8865_MIPI_UI_HS_EXIT_MIN_REG		0x4832
386 #define OV8865_MIPI_PKT_START_SIZE_REG		0x4833
388 #define OV8865_MIPI_PCLK_PERIOD_REG		0x4837
389 #define OV8865_MIPI_LP_GPIO0_REG		0x4838
390 #define OV8865_MIPI_LP_GPIO1_REG		0x4839
392 #define OV8865_MIPI_CTRL3C_REG			0x483c
393 #define OV8865_MIPI_LP_GPIO4_REG		0x483d
395 #define OV8865_MIPI_CTRL4A_REG			0x484a
396 #define OV8865_MIPI_CTRL4B_REG			0x484b
397 #define OV8865_MIPI_CTRL4C_REG			0x484c
398 #define OV8865_MIPI_LANE_TEST_PATTERN_REG	0x484d
399 #define OV8865_MIPI_FRAME_END_DELAY_REG		0x484e
400 #define OV8865_MIPI_CLOCK_TEST_PATTERN_REG	0x484f
401 #define OV8865_MIPI_LANE_SEL01_REG		0x4850
402 #define OV8865_MIPI_LANE_SEL01_LANE0(v)		(((v) << 0) & GENMASK(2, 0))
404 #define OV8865_MIPI_LANE_SEL23_REG		0x4851
405 #define OV8865_MIPI_LANE_SEL23_LANE2(v)		(((v) << 0) & GENMASK(2, 0))
410 #define OV8865_ISP_CTRL0_REG			0x5000
415 #define OV8865_ISP_CTRL1_REG			0x5001
416 #define OV8865_ISP_CTRL1_BLC_EN			BIT(0)
417 #define OV8865_ISP_CTRL2_REG			0x5002
420 #define OV8865_ISP_CTRL2_VSYNC_LATCH_EN		BIT(0)
421 #define OV8865_ISP_CTRL3_REG			0x5003
423 #define OV8865_ISP_GAIN_RED_H_REG		0x5018
425 #define OV8865_ISP_GAIN_RED_L_REG		0x5019
426 #define OV8865_ISP_GAIN_RED_L(v)		((v) & GENMASK(5, 0))
427 #define OV8865_ISP_GAIN_GREEN_H_REG		0x501a
429 #define OV8865_ISP_GAIN_GREEN_L_REG		0x501b
430 #define OV8865_ISP_GAIN_GREEN_L(v)		((v) & GENMASK(5, 0))
431 #define OV8865_ISP_GAIN_BLUE_H_REG		0x501c
433 #define OV8865_ISP_GAIN_BLUE_L_REG		0x501d
434 #define OV8865_ISP_GAIN_BLUE_L(v)		((v) & GENMASK(5, 0))
438 #define OV8865_VAP_CTRL0_REG			0x5900
439 #define OV8865_VAP_CTRL1_REG			0x5901
442 #define OV8865_VAP_CTRL1_VSUB_COEF(v)		(((v) - 1) & GENMASK(1, 0))
446 #define OV8865_PRE_CTRL0_REG			0x5e00
451 #define OV8865_PRE_CTRL0_PATTERN_COLOR_BARS	0
487  * +-+ pll_pre_div_half (0x30a [0])
489  *   +-+ pll_pre_div (0x300 [2:0], special values:
490  *     |              0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 4, 7: 8)
491  *     +-+ pll_mul (0x301 [1:0], 0x302 [7:0])
493  *       +-+ m_div (0x303 [3:0])
497  *       | +-+ mipi_div (0x304 [1:0], special values: 0: 4, 1: 5, 2: 6, 3: 8)
499  *       |   +-+ pclk_div (0x3020 [3])
503  *       +-+ sys_pre_div (0x305 [1:0], special values: 0: 3, 1: 4, 2: 5, 3: 6)
505  *         +-+ sys_div (0x306 [0])
507  *           +-+ sys_sel (0x3032 [7], 0: PLL1, 1: PLL2)
509  *             +-+ sclk_sel (0x3033 [1], 0: sys_sel, 1: PLL2 DAC_CLK)
511  *               +-+ sclk_pre_div (0x3106 [3:2], special values:
512  *                 |               0: 1, 1: 2, 2: 4, 3: 1)
514  *                 +-+ sclk_div (0x3106 [7:4], special values: 0: 1)
535  * +-+ pll_pre_div_half (0x312 [4])
537  *   +-+ pll_pre_div (0x30b [2:0], special values:
538  *     |              0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 4, 7: 8)
539  *     +-+ pll_mul (0x30c [1:0], 0x30d [7:0])
541  *       +-+ dac_div (0x312 [3:0])
545  *       +-+ sys_pre_div (0x30f [3:0])
547  *         +-+ sys_div (0x30e [2:0], special values:
548  *           |          0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 3.5, 6: 4, 7:5)
550  *           +-+ sys_sel (0x3032 [7], 0: PLL1, 1: PLL2)
552  *             +-+ sclk_sel (0x3033 [1], 0: sys_sel, 1: PLL2 DAC_CLK)
554  *               +-+ sclk_pre_div (0x3106 [3:2], special values:
555  *                 |               0: 1, 1: 2, 2: 4, 3: 1)
557  *                 +-+ sclk_div (0x3106 [7:4], special values: 0: 1)
729 		.pll_pre_div		= 0,
754 		.pll_pre_div		= 0,
758 		.sys_div		= 0,
772 	.sys_div		= 0,
777 	.pll_pre_div		= 0,
781 	.sys_div		= 0,
803 	.sclk_sel		= 0,
804 	.sclk_pre_div		= 0,
805 	.sclk_div		= 0,
811 	{ 0x3700, 0x48 },
812 	{ 0x3701, 0x18 },
813 	{ 0x3702, 0x50 },
814 	{ 0x3703, 0x32 },
815 	{ 0x3704, 0x28 },
816 	{ 0x3706, 0x70 },
817 	{ 0x3707, 0x08 },
818 	{ 0x3708, 0x48 },
819 	{ 0x3709, 0x80 },
820 	{ 0x370a, 0x01 },
821 	{ 0x370b, 0x70 },
822 	{ 0x370c, 0x07 },
823 	{ 0x3718, 0x14 },
824 	{ 0x3712, 0x44 },
825 	{ 0x371e, 0x31 },
826 	{ 0x371f, 0x7f },
827 	{ 0x3720, 0x0a },
828 	{ 0x3721, 0x0a },
829 	{ 0x3724, 0x04 },
830 	{ 0x3725, 0x04 },
831 	{ 0x3726, 0x0c },
832 	{ 0x3728, 0x0a },
833 	{ 0x3729, 0x03 },
834 	{ 0x372a, 0x06 },
835 	{ 0x372b, 0xa6 },
836 	{ 0x372c, 0xa6 },
837 	{ 0x372d, 0xa6 },
838 	{ 0x372e, 0x0c },
839 	{ 0x372f, 0x20 },
840 	{ 0x3730, 0x02 },
841 	{ 0x3731, 0x0c },
842 	{ 0x3732, 0x28 },
843 	{ 0x3736, 0x30 },
844 	{ 0x373a, 0x04 },
845 	{ 0x373b, 0x18 },
846 	{ 0x373c, 0x14 },
847 	{ 0x373e, 0x06 },
848 	{ 0x375a, 0x0c },
849 	{ 0x375b, 0x26 },
850 	{ 0x375d, 0x04 },
851 	{ 0x375f, 0x28 },
852 	{ 0x3767, 0x1e },
853 	{ 0x3772, 0x46 },
854 	{ 0x3773, 0x04 },
855 	{ 0x3774, 0x2c },
856 	{ 0x3775, 0x13 },
857 	{ 0x3776, 0x10 },
858 	{ 0x37a0, 0x88 },
859 	{ 0x37a1, 0x7a },
860 	{ 0x37a2, 0x7a },
861 	{ 0x37a3, 0x02 },
862 	{ 0x37a5, 0x09 },
863 	{ 0x37a7, 0x88 },
864 	{ 0x37a8, 0xb0 },
865 	{ 0x37a9, 0xb0 },
866 	{ 0x37aa, 0x88 },
867 	{ 0x37ab, 0x5c },
868 	{ 0x37ac, 0x5c },
869 	{ 0x37ad, 0x55 },
870 	{ 0x37ae, 0x19 },
871 	{ 0x37af, 0x19 },
872 	{ 0x37b3, 0x84 },
873 	{ 0x37b4, 0x84 },
874 	{ 0x37b5, 0x66 },
878 	{ OV8865_PSRAM_CTRL8_REG, 0x16 },
882 	{ 0x4500, 0x68 },
888 	{ 0x3700, 0x24 },
889 	{ 0x3701, 0x0c },
890 	{ 0x3702, 0x28 },
891 	{ 0x3703, 0x19 },
892 	{ 0x3704, 0x14 },
893 	{ 0x3706, 0x38 },
894 	{ 0x3707, 0x04 },
895 	{ 0x3708, 0x24 },
896 	{ 0x3709, 0x40 },
897 	{ 0x370a, 0x00 },
898 	{ 0x370b, 0xb8 },
899 	{ 0x370c, 0x04 },
900 	{ 0x3718, 0x12 },
901 	{ 0x3712, 0x42 },
902 	{ 0x371e, 0x19 },
903 	{ 0x371f, 0x40 },
904 	{ 0x3720, 0x05 },
905 	{ 0x3721, 0x05 },
906 	{ 0x3724, 0x02 },
907 	{ 0x3725, 0x02 },
908 	{ 0x3726, 0x06 },
909 	{ 0x3728, 0x05 },
910 	{ 0x3729, 0x02 },
911 	{ 0x372a, 0x03 },
912 	{ 0x372b, 0x53 },
913 	{ 0x372c, 0xa3 },
914 	{ 0x372d, 0x53 },
915 	{ 0x372e, 0x06 },
916 	{ 0x372f, 0x10 },
917 	{ 0x3730, 0x01 },
918 	{ 0x3731, 0x06 },
919 	{ 0x3732, 0x14 },
920 	{ 0x3736, 0x20 },
921 	{ 0x373a, 0x02 },
922 	{ 0x373b, 0x0c },
923 	{ 0x373c, 0x0a },
924 	{ 0x373e, 0x03 },
925 	{ 0x375a, 0x06 },
926 	{ 0x375b, 0x13 },
927 	{ 0x375d, 0x02 },
928 	{ 0x375f, 0x14 },
929 	{ 0x3767, 0x1c },
930 	{ 0x3772, 0x23 },
931 	{ 0x3773, 0x02 },
932 	{ 0x3774, 0x16 },
933 	{ 0x3775, 0x12 },
934 	{ 0x3776, 0x08 },
935 	{ 0x37a0, 0x44 },
936 	{ 0x37a1, 0x3d },
937 	{ 0x37a2, 0x3d },
938 	{ 0x37a3, 0x01 },
939 	{ 0x37a5, 0x08 },
940 	{ 0x37a7, 0x44 },
941 	{ 0x37a8, 0x58 },
942 	{ 0x37a9, 0x58 },
943 	{ 0x37aa, 0x44 },
944 	{ 0x37ab, 0x2e },
945 	{ 0x37ac, 0x2e },
946 	{ 0x37ad, 0x33 },
947 	{ 0x37ae, 0x0d },
948 	{ 0x37af, 0x0d },
949 	{ 0x37b3, 0x42 },
950 	{ 0x37b4, 0x42 },
951 	{ 0x37b5, 0x33 },
955 	{ OV8865_PSRAM_CTRL8_REG, 0x0b },
959 	{ 0x4500, 0x40 },
991 		.blc_top_zero_line_start	= 0,
1042 		.blc_top_zero_line_start	= 0,
1097 		.blc_top_zero_line_start	= 0,
1156 		.blc_top_zero_line_start	= 0,
1161 		.blc_bottom_zero_line_start	= 0,
1162 		.blc_bottom_zero_line_num	= 0,
1190 	{ 0x3604, 0x04 },
1191 	{ 0x3602, 0x30 },
1192 	{ 0x3605, 0x00 },
1193 	{ 0x3607, 0x20 },
1194 	{ 0x3608, 0x11 },
1195 	{ 0x3609, 0x68 },
1196 	{ 0x360a, 0x40 },
1197 	{ 0x360c, 0xdd },
1198 	{ 0x360e, 0x0c },
1199 	{ 0x3610, 0x07 },
1200 	{ 0x3612, 0x86 },
1201 	{ 0x3613, 0x58 },
1202 	{ 0x3614, 0x28 },
1203 	{ 0x3617, 0x40 },
1204 	{ 0x3618, 0x5a },
1205 	{ 0x3619, 0x9b },
1206 	{ 0x361c, 0x00 },
1207 	{ 0x361d, 0x60 },
1208 	{ 0x3631, 0x60 },
1209 	{ 0x3633, 0x10 },
1210 	{ 0x3634, 0x10 },
1211 	{ 0x3635, 0x10 },
1212 	{ 0x3636, 0x10 },
1213 	{ 0x3638, 0xff },
1214 	{ 0x3641, 0x55 },
1215 	{ 0x3646, 0x86 },
1216 	{ 0x3647, 0x27 },
1217 	{ 0x364a, 0x1b },
1221 	{ 0x3700, 0x24 },
1222 	{ 0x3701, 0x0c },
1223 	{ 0x3702, 0x28 },
1224 	{ 0x3703, 0x19 },
1225 	{ 0x3704, 0x14 },
1226 	{ 0x3705, 0x00 },
1227 	{ 0x3706, 0x38 },
1228 	{ 0x3707, 0x04 },
1229 	{ 0x3708, 0x24 },
1230 	{ 0x3709, 0x40 },
1231 	{ 0x370a, 0x00 },
1232 	{ 0x370b, 0xb8 },
1233 	{ 0x370c, 0x04 },
1234 	{ 0x3718, 0x12 },
1235 	{ 0x3719, 0x31 },
1236 	{ 0x3712, 0x42 },
1237 	{ 0x3714, 0x12 },
1238 	{ 0x371e, 0x19 },
1239 	{ 0x371f, 0x40 },
1240 	{ 0x3720, 0x05 },
1241 	{ 0x3721, 0x05 },
1242 	{ 0x3724, 0x02 },
1243 	{ 0x3725, 0x02 },
1244 	{ 0x3726, 0x06 },
1245 	{ 0x3728, 0x05 },
1246 	{ 0x3729, 0x02 },
1247 	{ 0x372a, 0x03 },
1248 	{ 0x372b, 0x53 },
1249 	{ 0x372c, 0xa3 },
1250 	{ 0x372d, 0x53 },
1251 	{ 0x372e, 0x06 },
1252 	{ 0x372f, 0x10 },
1253 	{ 0x3730, 0x01 },
1254 	{ 0x3731, 0x06 },
1255 	{ 0x3732, 0x14 },
1256 	{ 0x3733, 0x10 },
1257 	{ 0x3734, 0x40 },
1258 	{ 0x3736, 0x20 },
1259 	{ 0x373a, 0x02 },
1260 	{ 0x373b, 0x0c },
1261 	{ 0x373c, 0x0a },
1262 	{ 0x373e, 0x03 },
1263 	{ 0x3755, 0x40 },
1264 	{ 0x3758, 0x00 },
1265 	{ 0x3759, 0x4c },
1266 	{ 0x375a, 0x06 },
1267 	{ 0x375b, 0x13 },
1268 	{ 0x375c, 0x40 },
1269 	{ 0x375d, 0x02 },
1270 	{ 0x375e, 0x00 },
1271 	{ 0x375f, 0x14 },
1272 	{ 0x3767, 0x1c },
1273 	{ 0x3768, 0x04 },
1274 	{ 0x3769, 0x20 },
1275 	{ 0x376c, 0xc0 },
1276 	{ 0x376d, 0xc0 },
1277 	{ 0x376a, 0x08 },
1278 	{ 0x3761, 0x00 },
1279 	{ 0x3762, 0x00 },
1280 	{ 0x3763, 0x00 },
1281 	{ 0x3766, 0xff },
1282 	{ 0x376b, 0x42 },
1283 	{ 0x3772, 0x23 },
1284 	{ 0x3773, 0x02 },
1285 	{ 0x3774, 0x16 },
1286 	{ 0x3775, 0x12 },
1287 	{ 0x3776, 0x08 },
1288 	{ 0x37a0, 0x44 },
1289 	{ 0x37a1, 0x3d },
1290 	{ 0x37a2, 0x3d },
1291 	{ 0x37a3, 0x01 },
1292 	{ 0x37a4, 0x00 },
1293 	{ 0x37a5, 0x08 },
1294 	{ 0x37a6, 0x00 },
1295 	{ 0x37a7, 0x44 },
1296 	{ 0x37a8, 0x58 },
1297 	{ 0x37a9, 0x58 },
1298 	{ 0x3760, 0x00 },
1299 	{ 0x376f, 0x01 },
1300 	{ 0x37aa, 0x44 },
1301 	{ 0x37ab, 0x2e },
1302 	{ 0x37ac, 0x2e },
1303 	{ 0x37ad, 0x33 },
1304 	{ 0x37ae, 0x0d },
1305 	{ 0x37af, 0x0d },
1306 	{ 0x37b0, 0x00 },
1307 	{ 0x37b1, 0x00 },
1308 	{ 0x37b2, 0x00 },
1309 	{ 0x37b3, 0x42 },
1310 	{ 0x37b4, 0x42 },
1311 	{ 0x37b5, 0x33 },
1312 	{ 0x37b6, 0x00 },
1313 	{ 0x37b7, 0x00 },
1314 	{ 0x37b8, 0x00 },
1315 	{ 0x37b9, 0xff },
1319 	{ 0x4503, 0x10 },
1336 	0,
1350 	unsigned char data[2] = { address >> 8, address & 0xff };  in ov8865_read()
1355 	if (ret < 0) {  in ov8865_read()
1362 	if (ret < 0) {  in ov8865_read()
1368 	return 0;  in ov8865_read()
1373 	unsigned char data[3] = { address >> 8, address & 0xff, value };  in ov8865_write()
1378 	if (ret < 0) {  in ov8865_write()
1384 	return 0;  in ov8865_write()
1392 	int ret = 0;  in ov8865_write_sequence()
1394 	for (i = 0; i < sequence_count; i++) {  in ov8865_write_sequence()
1410 	u8 value = 0;  in ov8865_update_bits()
1432 	u8 value = 0;  in ov8865_sw_standby()
1450 	for (i = 0; i < ARRAY_SIZE(regs); i++) {  in ov8865_chip_id_check()
1452 		if (ret < 0)  in ov8865_chip_id_check()
1463 	return 0;  in ov8865_chip_id_check()
1493 				   OV8865_MIPI_LANE_SEL01_LANE0(0) |  in ov8865_mipi_configure()
1518 	return ov8865_write(sensor, OV8865_MIPI_PCLK_PERIOD_REG, 0x16);  in ov8865_mipi_configure()
1541 	ret = ov8865_write(sensor, OV8865_BLC_CTRL1F_REG, 0);  in ov8865_black_level_configure()
1576 	case 0:  in ov8865_mode_pll1_rate()
1745 	ret = ov8865_write(sensor, OV8865_FORMAT1_REG, 0);  in ov8865_mode_binning_configure()
1770 				 OV8865_ISP_CTRL2_VARIOPIXEL_EN : 0);  in ov8865_mode_binning_configure()
2107 	return 0;  in ov8865_mode_configure()
2199 				  enable ? bits : 0);  in ov8865_flip_vert_configure()
2208 				  enable ? bits : 0);  in ov8865_flip_horz_configure()
2256 	for (i = 0; i < ARRAY_SIZE(ov8865_link_freq_menu); i++) {  in ov8865_state_mipi_configure()
2263 	for (j = 0; j < sensor->endpoint.nr_of_link_frequencies; j++) {  in ov8865_state_mipi_configure()
2295 	return 0;  in ov8865_state_mipi_configure()
2322 	return 0;  in ov8865_state_configure()
2327 	return ov8865_state_configure(sensor, &ov8865_modes[0],  in ov8865_state_init()
2328 				      ov8865_mbus_codes[0]);  in ov8865_state_init()
2394 	return 0;  in ov8865_sensor_init()
2400 	int ret = 0;  in ov8865_sensor_power()
2433 		gpiod_set_value_cansleep(sensor->reset, 0);  in ov8865_sensor_power()
2434 		gpiod_set_value_cansleep(sensor->powerdown, 0);  in ov8865_sensor_power()
2480 		return 0;  in ov8865_s_ctrl()
2510 	return 0;  in ov8865_s_ctrl()
2522 	const struct ov8865_mode *mode = &ov8865_modes[0];  in ov8865_ctrls_init()
2553 	v4l2_ctrl_new_std(handler, ops, V4L2_CID_HFLIP, 0, 1, 1, 0);  in ov8865_ctrls_init()
2554 	v4l2_ctrl_new_std(handler, ops, V4L2_CID_VFLIP, 0, 1, 1, 0);  in ov8865_ctrls_init()
2560 				     0, 0, ov8865_test_pattern_menu);  in ov8865_ctrls_init()
2581 				       0, ov8865_link_freq_menu);  in ov8865_ctrls_init()
2606 	return 0;  in ov8865_ctrls_init()
2624 		if (ret < 0)  in ov8865_s_stream()
2640 	return 0;  in ov8865_s_stream()
2658 	return 0;  in ov8865_enum_mbus_code()
2696 	return 0;  in ov8865_get_fmt()
2706 	u32 mbus_code = 0;  in ov8865_set_fmt()
2710 	int ret = 0;  in ov8865_set_fmt()
2720 	for (index = 0; index < ARRAY_SIZE(ov8865_mbus_codes); index++) {  in ov8865_set_fmt()
2729 		mbus_code = ov8865_mbus_codes[0];  in ov8865_set_fmt()
2784 	return 0;  in ov8865_enum_frame_size()
2821 		sel->r.top = 0;  in ov8865_get_selection()
2822 		sel->r.left = 0;  in ov8865_get_selection()
2837 	return 0;  in ov8865_get_selection()
2868 	return 0;  in ov8865_get_frame_interval()
2893 	int ret = 0;  in ov8865_suspend()
2919 	int ret = 0;  in ov8865_resume()
2959 	unsigned int rate = 0;  in ov8865_probe()
3056 	for (i = 0; i < ARRAY_SIZE(supported_extclk_rates); i++) {  in ov8865_probe()
3112 	return 0;  in ov8865_probe()