Lines Matching +full:0 +full:x5981
30 #define OV5648_SW_STANDBY_REG 0x100
31 #define OV5648_SW_STANDBY_STREAM_ON BIT(0)
33 #define OV5648_SW_RESET_REG 0x103
34 #define OV5648_SW_RESET_RESET BIT(0)
36 #define OV5648_PAD_OEN0_REG 0x3000
37 #define OV5648_PAD_OEN1_REG 0x3001
38 #define OV5648_PAD_OEN2_REG 0x3002
39 #define OV5648_PAD_OUT0_REG 0x3008
40 #define OV5648_PAD_OUT1_REG 0x3009
42 #define OV5648_CHIP_ID_H_REG 0x300a
43 #define OV5648_CHIP_ID_H_VALUE 0x56
44 #define OV5648_CHIP_ID_L_REG 0x300b
45 #define OV5648_CHIP_ID_L_VALUE 0x48
47 #define OV5648_PAD_OUT2_REG 0x300d
48 #define OV5648_PAD_SEL0_REG 0x300e
49 #define OV5648_PAD_SEL1_REG 0x300f
50 #define OV5648_PAD_SEL2_REG 0x3010
51 #define OV5648_PAD_PK_REG 0x3011
53 #define OV5648_PAD_PK_DRIVE_STRENGTH_1X (0 << 5)
57 #define OV5648_A_PWC_PK_O0_REG 0x3013
59 #define OV5648_A_PWC_PK_O1_REG 0x3014
61 #define OV5648_MIPI_PHY0_REG 0x3016
62 #define OV5648_MIPI_PHY1_REG 0x3017
63 #define OV5648_MIPI_SC_CTRL0_REG 0x3018
69 #define OV5648_MIPI_SC_CTRL0_LANE_DIS_OP BIT(0)
70 #define OV5648_MIPI_SC_CTRL1_REG 0x3019
71 #define OV5648_MISC_CTRL0_REG 0x3021
72 #define OV5648_MIPI_SC_CTRL2_REG 0x3022
73 #define OV5648_SUB_ID_REG 0x302a
75 #define OV5648_PLL_CTRL0_REG 0x3034
77 #define OV5648_PLL_CTRL0_BITS(v) ((v) & GENMASK(3, 0))
78 #define OV5648_PLL_CTRL1_REG 0x3035
80 #define OV5648_PLL_CTRL1_MIPI_DIV(v) ((v) & GENMASK(3, 0))
81 #define OV5648_PLL_MUL_REG 0x3036
82 #define OV5648_PLL_MUL(v) ((v) & GENMASK(7, 0))
83 #define OV5648_PLL_DIV_REG 0x3037
85 #define OV5648_PLL_DIV_PLL_PRE_DIV(v) ((v) & GENMASK(3, 0))
86 #define OV5648_PLL_DEBUG_REG 0x3038
87 #define OV5648_PLL_BYPASS_REG 0x3039
89 #define OV5648_PLLS_BYPASS_REG 0x303a
90 #define OV5648_PLLS_MUL_REG 0x303b
91 #define OV5648_PLLS_MUL(v) ((v) & GENMASK(4, 0))
92 #define OV5648_PLLS_CTRL_REG 0x303c
94 #define OV5648_PLLS_CTRL_SYS_DIV(v) ((v) & GENMASK(3, 0))
95 #define OV5648_PLLS_DIV_REG 0x303d
98 #define OV5648_PLLS_DIV_PLLS_SEL_DIV(v) ((v) & GENMASK(1, 0))
100 #define OV5648_SRB_CTRL_REG 0x3106
103 #define OV5648_SRB_CTRL_SCLK_ARBITER_EN BIT(0)
107 #define OV5648_GROUP_ADR0_REG 0x3200
108 #define OV5648_GROUP_ADR1_REG 0x3201
109 #define OV5648_GROUP_ADR2_REG 0x3202
110 #define OV5648_GROUP_ADR3_REG 0x3203
111 #define OV5648_GROUP_LEN0_REG 0x3204
112 #define OV5648_GROUP_LEN1_REG 0x3205
113 #define OV5648_GROUP_LEN2_REG 0x3206
114 #define OV5648_GROUP_LEN3_REG 0x3207
115 #define OV5648_GROUP_ACCESS_REG 0x3208
119 #define OV5648_EXPOSURE_CTRL_HH_REG 0x3500
122 #define OV5648_EXPOSURE_CTRL_H_REG 0x3501
125 #define OV5648_EXPOSURE_CTRL_L_REG 0x3502
126 #define OV5648_EXPOSURE_CTRL_L(v) ((v) & GENMASK(7, 0))
127 #define OV5648_EXPOSURE_CTRL_L_VALUE(v) ((v) & GENMASK(7, 0))
128 #define OV5648_MANUAL_CTRL_REG 0x3503
131 #define OV5648_MANUAL_CTRL_AEC_MANUAL_EN BIT(0)
132 #define OV5648_GAIN_CTRL_H_REG 0x350a
135 #define OV5648_GAIN_CTRL_L_REG 0x350b
136 #define OV5648_GAIN_CTRL_L(v) ((v) & GENMASK(7, 0))
137 #define OV5648_GAIN_CTRL_L_VALUE(v) ((v) & GENMASK(7, 0))
139 #define OV5648_ANALOG_CTRL0_REG_BASE 0x3600
140 #define OV5648_ANALOG_CTRL1_REG_BASE 0x3700
142 #define OV5648_AEC_CTRL0_REG 0x3a00
148 #define OV5648_AEC_CTRL0_FREEZE_EN BIT(0)
149 #define OV5648_EXPOSURE_MIN_REG 0x3a01
150 #define OV5648_EXPOSURE_MAX_60_H_REG 0x3a02
151 #define OV5648_EXPOSURE_MAX_60_L_REG 0x3a03
152 #define OV5648_AEC_CTRL5_REG 0x3a05
153 #define OV5648_AEC_CTRL6_REG 0x3a06
154 #define OV5648_AEC_CTRL7_REG 0x3a07
155 #define OV5648_BANDING_STEP_50_H_REG 0x3a08
156 #define OV5648_BANDING_STEP_50_L_REG 0x3a09
157 #define OV5648_BANDING_STEP_60_H_REG 0x3a0a
158 #define OV5648_BANDING_STEP_60_L_REG 0x3a0b
159 #define OV5648_AEC_CTRLC_REG 0x3a0c
160 #define OV5648_BANDING_MAX_60_REG 0x3a0d
161 #define OV5648_BANDING_MAX_50_REG 0x3a0e
162 #define OV5648_WPT_REG 0x3a0f
163 #define OV5648_BPT_REG 0x3a10
164 #define OV5648_VPT_HIGH_REG 0x3a11
165 #define OV5648_AVG_MANUAL_REG 0x3a12
166 #define OV5648_PRE_GAIN_REG 0x3a13
167 #define OV5648_EXPOSURE_MAX_50_H_REG 0x3a14
168 #define OV5648_EXPOSURE_MAX_50_L_REG 0x3a15
169 #define OV5648_GAIN_BASE_NIGHT_REG 0x3a17
170 #define OV5648_AEC_GAIN_CEILING_H_REG 0x3a18
171 #define OV5648_AEC_GAIN_CEILING_L_REG 0x3a19
172 #define OV5648_DIFF_MAX_REG 0x3a1a
173 #define OV5648_WPT2_REG 0x3a1b
174 #define OV5648_LED_ADD_ROW_H_REG 0x3a1c
175 #define OV5648_LED_ADD_ROW_L_REG 0x3a1d
176 #define OV5648_BPT2_REG 0x3a1e
177 #define OV5648_VPT_LOW_REG 0x3a1f
178 #define OV5648_AEC_CTRL20_REG 0x3a20
179 #define OV5648_AEC_CTRL21_REG 0x3a21
181 #define OV5648_AVG_START_X_H_REG 0x5680
182 #define OV5648_AVG_START_X_L_REG 0x5681
183 #define OV5648_AVG_START_Y_H_REG 0x5682
184 #define OV5648_AVG_START_Y_L_REG 0x5683
185 #define OV5648_AVG_WINDOW_X_H_REG 0x5684
186 #define OV5648_AVG_WINDOW_X_L_REG 0x5685
187 #define OV5648_AVG_WINDOW_Y_H_REG 0x5686
188 #define OV5648_AVG_WINDOW_Y_L_REG 0x5687
189 #define OV5648_AVG_WEIGHT00_REG 0x5688
190 #define OV5648_AVG_WEIGHT01_REG 0x5689
191 #define OV5648_AVG_WEIGHT02_REG 0x568a
192 #define OV5648_AVG_WEIGHT03_REG 0x568b
193 #define OV5648_AVG_WEIGHT04_REG 0x568c
194 #define OV5648_AVG_WEIGHT05_REG 0x568d
195 #define OV5648_AVG_WEIGHT06_REG 0x568e
196 #define OV5648_AVG_WEIGHT07_REG 0x568f
197 #define OV5648_AVG_CTRL10_REG 0x5690
198 #define OV5648_AVG_WEIGHT_SUM_REG 0x5691
199 #define OV5648_AVG_READOUT_REG 0x5693
201 #define OV5648_DIG_CTRL0_REG 0x5a00
202 #define OV5648_DIG_COMP_MAN_H_REG 0x5a02
203 #define OV5648_DIG_COMP_MAN_L_REG 0x5a03
205 #define OV5648_GAINC_MAN_H_REG 0x5a20
206 #define OV5648_GAINC_MAN_L_REG 0x5a21
207 #define OV5648_GAINC_DGC_MAN_H_REG 0x5a22
208 #define OV5648_GAINC_DGC_MAN_L_REG 0x5a23
209 #define OV5648_GAINC_CTRL0_REG 0x5a24
211 #define OV5648_GAINF_ANA_NUM_REG 0x5a40
212 #define OV5648_GAINF_DIG_GAIN_REG 0x5a41
216 #define OV5648_CROP_START_X_H_REG 0x3800
218 #define OV5648_CROP_START_X_L_REG 0x3801
219 #define OV5648_CROP_START_X_L(v) ((v) & GENMASK(7, 0))
220 #define OV5648_CROP_START_Y_H_REG 0x3802
222 #define OV5648_CROP_START_Y_L_REG 0x3803
223 #define OV5648_CROP_START_Y_L(v) ((v) & GENMASK(7, 0))
224 #define OV5648_CROP_END_X_H_REG 0x3804
226 #define OV5648_CROP_END_X_L_REG 0x3805
227 #define OV5648_CROP_END_X_L(v) ((v) & GENMASK(7, 0))
228 #define OV5648_CROP_END_Y_H_REG 0x3806
230 #define OV5648_CROP_END_Y_L_REG 0x3807
231 #define OV5648_CROP_END_Y_L(v) ((v) & GENMASK(7, 0))
232 #define OV5648_OUTPUT_SIZE_X_H_REG 0x3808
234 #define OV5648_OUTPUT_SIZE_X_L_REG 0x3809
235 #define OV5648_OUTPUT_SIZE_X_L(v) ((v) & GENMASK(7, 0))
236 #define OV5648_OUTPUT_SIZE_Y_H_REG 0x380a
238 #define OV5648_OUTPUT_SIZE_Y_L_REG 0x380b
239 #define OV5648_OUTPUT_SIZE_Y_L(v) ((v) & GENMASK(7, 0))
240 #define OV5648_HTS_H_REG 0x380c
242 #define OV5648_HTS_L_REG 0x380d
243 #define OV5648_HTS_L(v) ((v) & GENMASK(7, 0))
244 #define OV5648_VTS_H_REG 0x380e
246 #define OV5648_VTS_L_REG 0x380f
247 #define OV5648_VTS_L(v) ((v) & GENMASK(7, 0))
248 #define OV5648_OFFSET_X_H_REG 0x3810
250 #define OV5648_OFFSET_X_L_REG 0x3811
251 #define OV5648_OFFSET_X_L(v) ((v) & GENMASK(7, 0))
252 #define OV5648_OFFSET_Y_H_REG 0x3812
254 #define OV5648_OFFSET_Y_L_REG 0x3813
255 #define OV5648_OFFSET_Y_L(v) ((v) & GENMASK(7, 0))
256 #define OV5648_SUB_INC_X_REG 0x3814
258 #define OV5648_SUB_INC_X_EVEN(v) ((v) & GENMASK(3, 0))
259 #define OV5648_SUB_INC_Y_REG 0x3815
261 #define OV5648_SUB_INC_Y_EVEN(v) ((v) & GENMASK(3, 0))
262 #define OV5648_HSYNCST_H_REG 0x3816
263 #define OV5648_HSYNCST_H(v) (((v) >> 8) & 0xf)
264 #define OV5648_HSYNCST_L_REG 0x3817
265 #define OV5648_HSYNCST_L(v) ((v) & GENMASK(7, 0))
266 #define OV5648_HSYNCW_H_REG 0x3818
267 #define OV5648_HSYNCW_H(v) (((v) >> 8) & 0xf)
268 #define OV5648_HSYNCW_L_REG 0x3819
269 #define OV5648_HSYNCW_L(v) ((v) & GENMASK(7, 0))
271 #define OV5648_TC20_REG 0x3820
275 #define OV5648_TC20_BINNING_VERT_EN BIT(0)
276 #define OV5648_TC21_REG 0x3821
279 #define OV5648_TC21_BINNING_HORZ_EN BIT(0)
283 #define OV5648_STROBE_REG 0x3b00
284 #define OV5648_FREX_EXP_HH_REG 0x3b01
285 #define OV5648_SHUTTER_DLY_H_REG 0x3b02
286 #define OV5648_SHUTTER_DLY_L_REG 0x3b03
287 #define OV5648_FREX_EXP_H_REG 0x3b04
288 #define OV5648_FREX_EXP_L_REG 0x3b05
289 #define OV5648_FREX_CTRL_REG 0x3b06
290 #define OV5648_FREX_MODE_SEL_REG 0x3b07
294 #define OV5648_FREX_MODE_SEL_MODE1 0x0
295 #define OV5648_FREX_MODE_SEL_MODE2 0x1
296 #define OV5648_FREX_MODE_SEL_ROLLING 0x2
297 #define OV5648_FREX_EXP_REQ_REG 0x3b08
298 #define OV5648_FREX_SHUTTER_DLY_REG 0x3b09
299 #define OV5648_FREX_RST_LEN_REG 0x3b0a
300 #define OV5648_STROBE_WIDTH_HH_REG 0x3b0b
301 #define OV5648_STROBE_WIDTH_H_REG 0x3b0c
305 #define OV5648_OTP_DATA_REG_BASE 0x3d00
306 #define OV5648_OTP_PROGRAM_CTRL_REG 0x3d80
307 #define OV5648_OTP_LOAD_CTRL_REG 0x3d81
311 #define OV5648_PSRAM_CTRL1_REG 0x3f01
312 #define OV5648_PSRAM_CTRLF_REG 0x3f0f
316 #define OV5648_BLC_CTRL0_REG 0x4000
317 #define OV5648_BLC_CTRL1_REG 0x4001
318 #define OV5648_BLC_CTRL1_START_LINE(v) ((v) & GENMASK(5, 0))
319 #define OV5648_BLC_CTRL2_REG 0x4002
321 #define OV5648_BLC_CTRL2_RESET_FRAME_NUM(v) ((v) & GENMASK(5, 0))
322 #define OV5648_BLC_CTRL3_REG 0x4003
323 #define OV5648_BLC_LINE_NUM_REG 0x4004
324 #define OV5648_BLC_LINE_NUM(v) ((v) & GENMASK(7, 0))
325 #define OV5648_BLC_CTRL5_REG 0x4005
327 #define OV5648_BLC_LEVEL_REG 0x4009
331 #define OV5648_FRAME_CTRL_REG 0x4200
332 #define OV5648_FRAME_ON_NUM_REG 0x4201
333 #define OV5648_FRAME_OFF_NUM_REG 0x4202
337 #define OV5648_MIPI_CTRL0_REG 0x4800
340 #define OV5648_MIPI_CTRL0_LANE_SELECT_LANE1 0
342 #define OV5648_MIPI_CTRL0_IDLE_LP00 0
345 #define OV5648_MIPI_CTRL1_REG 0x4801
346 #define OV5648_MIPI_CTRL2_REG 0x4802
347 #define OV5648_MIPI_CTRL3_REG 0x4803
348 #define OV5648_MIPI_CTRL4_REG 0x4804
349 #define OV5648_MIPI_CTRL5_REG 0x4805
350 #define OV5648_MIPI_MAX_FRAME_COUNT_H_REG 0x4810
351 #define OV5648_MIPI_MAX_FRAME_COUNT_L_REG 0x4811
352 #define OV5648_MIPI_CTRL14_REG 0x4814
353 #define OV5648_MIPI_DT_SPKT_REG 0x4815
354 #define OV5648_MIPI_HS_ZERO_MIN_H_REG 0x4818
355 #define OV5648_MIPI_HS_ZERO_MIN_L_REG 0x4819
356 #define OV5648_MIPI_HS_TRAIN_MIN_H_REG 0x481a
357 #define OV5648_MIPI_HS_TRAIN_MIN_L_REG 0x481b
358 #define OV5648_MIPI_CLK_ZERO_MIN_H_REG 0x481c
359 #define OV5648_MIPI_CLK_ZERO_MIN_L_REG 0x481d
360 #define OV5648_MIPI_CLK_PREPARE_MIN_H_REG 0x481e
361 #define OV5648_MIPI_CLK_PREPARE_MIN_L_REG 0x481f
362 #define OV5648_MIPI_CLK_POST_MIN_H_REG 0x4820
363 #define OV5648_MIPI_CLK_POST_MIN_L_REG 0x4821
364 #define OV5648_MIPI_CLK_TRAIL_MIN_H_REG 0x4822
365 #define OV5648_MIPI_CLK_TRAIL_MIN_L_REG 0x4823
366 #define OV5648_MIPI_LPX_P_MIN_H_REG 0x4824
367 #define OV5648_MIPI_LPX_P_MIN_L_REG 0x4825
368 #define OV5648_MIPI_HS_PREPARE_MIN_H_REG 0x4826
369 #define OV5648_MIPI_HS_PREPARE_MIN_L_REG 0x4827
370 #define OV5648_MIPI_HS_EXIT_MIN_H_REG 0x4828
371 #define OV5648_MIPI_HS_EXIT_MIN_L_REG 0x4829
372 #define OV5648_MIPI_HS_ZERO_MIN_UI_REG 0x482a
373 #define OV5648_MIPI_HS_TRAIL_MIN_UI_REG 0x482b
374 #define OV5648_MIPI_CLK_ZERO_MIN_UI_REG 0x482c
375 #define OV5648_MIPI_CLK_PREPARE_MIN_UI_REG 0x482d
376 #define OV5648_MIPI_CLK_POST_MIN_UI_REG 0x482e
377 #define OV5648_MIPI_CLK_TRAIL_MIN_UI_REG 0x482f
378 #define OV5648_MIPI_LPX_P_MIN_UI_REG 0x4830
379 #define OV5648_MIPI_HS_PREPARE_MIN_UI_REG 0x4831
380 #define OV5648_MIPI_HS_EXIT_MIN_UI_REG 0x4832
381 #define OV5648_MIPI_REG_MIN_H_REG 0x4833
382 #define OV5648_MIPI_REG_MIN_L_REG 0x4834
383 #define OV5648_MIPI_REG_MAX_H_REG 0x4835
384 #define OV5648_MIPI_REG_MAX_L_REG 0x4836
385 #define OV5648_MIPI_PCLK_PERIOD_REG 0x4837
386 #define OV5648_MIPI_WKUP_DLY_REG 0x4838
387 #define OV5648_MIPI_LP_GPIO_REG 0x483b
388 #define OV5648_MIPI_SNR_PCLK_DIV_REG 0x4843
392 #define OV5648_ISP_CTRL0_REG 0x5000
395 #define OV5648_ISP_CTRL1_REG 0x5001
396 #define OV5648_ISP_CTRL1_AWB_EN BIT(0)
397 #define OV5648_ISP_CTRL2_REG 0x5002
400 #define OV5648_ISP_CTRL2_AWB_GAIN_EN BIT(0)
401 #define OV5648_ISP_CTRL3_REG 0x5003
405 #define OV5648_ISP_CTRL4_REG 0x5004
406 #define OV5648_ISP_CTRL5_REG 0x5005
407 #define OV5648_ISP_CTRL6_REG 0x5006
408 #define OV5648_ISP_CTRL7_REG 0x5007
409 #define OV5648_ISP_MAN_OFFSET_X_H_REG 0x5008
410 #define OV5648_ISP_MAN_OFFSET_X_L_REG 0x5009
411 #define OV5648_ISP_MAN_OFFSET_Y_H_REG 0x500a
412 #define OV5648_ISP_MAN_OFFSET_Y_L_REG 0x500b
413 #define OV5648_ISP_MAN_WIN_OFFSET_X_H_REG 0x500c
414 #define OV5648_ISP_MAN_WIN_OFFSET_X_L_REG 0x500d
415 #define OV5648_ISP_MAN_WIN_OFFSET_Y_H_REG 0x500e
416 #define OV5648_ISP_MAN_WIN_OFFSET_Y_L_REG 0x500f
417 #define OV5648_ISP_MAN_WIN_OUTPUT_X_H_REG 0x5010
418 #define OV5648_ISP_MAN_WIN_OUTPUT_X_L_REG 0x5011
419 #define OV5648_ISP_MAN_WIN_OUTPUT_Y_H_REG 0x5012
420 #define OV5648_ISP_MAN_WIN_OUTPUT_Y_L_REG 0x5013
421 #define OV5648_ISP_MAN_INPUT_X_H_REG 0x5014
422 #define OV5648_ISP_MAN_INPUT_X_L_REG 0x5015
423 #define OV5648_ISP_MAN_INPUT_Y_H_REG 0x5016
424 #define OV5648_ISP_MAN_INPUT_Y_L_REG 0x5017
425 #define OV5648_ISP_CTRL18_REG 0x5018
426 #define OV5648_ISP_CTRL19_REG 0x5019
427 #define OV5648_ISP_CTRL1A_REG 0x501a
428 #define OV5648_ISP_CTRL1D_REG 0x501d
429 #define OV5648_ISP_CTRL1F_REG 0x501f
431 #define OV5648_ISP_CTRL25_REG 0x5025
433 #define OV5648_ISP_CTRL3D_REG 0x503d
438 #define OV5648_ISP_CTRL3D_PATTERN_COLOR_BARS 0
443 #define OV5648_ISP_CTRL3E_REG 0x503e
444 #define OV5648_ISP_CTRL4B_REG 0x504b
447 #define OV5648_ISP_CTRL4C_REG 0x504c
448 #define OV5648_ISP_CTRL57_REG 0x5057
449 #define OV5648_ISP_CTRL58_REG 0x5058
450 #define OV5648_ISP_CTRL59_REG 0x5059
452 #define OV5648_ISP_WINDOW_START_X_H_REG 0x5980
453 #define OV5648_ISP_WINDOW_START_X_L_REG 0x5981
454 #define OV5648_ISP_WINDOW_START_Y_H_REG 0x5982
455 #define OV5648_ISP_WINDOW_START_Y_L_REG 0x5983
456 #define OV5648_ISP_WINDOW_WIN_X_H_REG 0x5984
457 #define OV5648_ISP_WINDOW_WIN_X_L_REG 0x5985
458 #define OV5648_ISP_WINDOW_WIN_Y_H_REG 0x5986
459 #define OV5648_ISP_WINDOW_WIN_Y_L_REG 0x5987
460 #define OV5648_ISP_WINDOW_MAN_REG 0x5988
464 #define OV5648_AWB_CTRL_REG 0x5180
470 #define OV5648_AWB_DELTA_REG 0x5181
471 #define OV5648_AWB_STABLE_RANGE_REG 0x5182
472 #define OV5648_AWB_STABLE_RANGE_WIDE_REG 0x5183
473 #define OV5648_HSIZE_MAN_REG 0x5185
475 #define OV5648_GAIN_RED_MAN_H_REG 0x5186
477 #define OV5648_GAIN_RED_MAN_L_REG 0x5187
478 #define OV5648_GAIN_RED_MAN_L(v) ((v) & GENMASK(7, 0))
479 #define OV5648_GAIN_GREEN_MAN_H_REG 0x5188
481 #define OV5648_GAIN_GREEN_MAN_L_REG 0x5189
482 #define OV5648_GAIN_GREEN_MAN_L(v) ((v) & GENMASK(7, 0))
483 #define OV5648_GAIN_BLUE_MAN_H_REG 0x518a
485 #define OV5648_GAIN_BLUE_MAN_L_REG 0x518b
486 #define OV5648_GAIN_BLUE_MAN_L(v) ((v) & GENMASK(7, 0))
487 #define OV5648_GAIN_RED_LIMIT_REG 0x518c
488 #define OV5648_GAIN_GREEN_LIMIT_REG 0x518d
489 #define OV5648_GAIN_BLUE_LIMIT_REG 0x518e
490 #define OV5648_AWB_FRAME_COUNT_REG 0x518f
491 #define OV5648_AWB_BASE_MAN_REG 0x51df
515 * +-+ pll_pre_div (0x3037 [3:0], special values: 5: 1.5, 7: 2.5)
517 * +-+ pll_mul (0x3036 [7:0])
519 * +-+ sys_div (0x3035 [7:4])
521 * +-+ mipi_div (0x3035 [3:0])
529 * +-+ root_div (0x3037 [4])
531 * +-+ bit_div (0x3034 [3:0], 8 bits: 2, 10 bits: 2.5, other: 1)
533 * +-+ sclk_div (0x3106 [3:2])
537 * +-+ mipi_div (0x3035, 1: PCLK = SCLK)
556 * +-+ plls_pre_div (0x303d [5:4], special values: 0: 1, 1: 1.5)
558 * +-+ plls_div_r (0x303d [2])
560 * +-+ plls_mul (0x303b [4:0])
562 * +-+ sys_div (0x303c [3:0])
564 * +-+ sel_div (0x303d [1:0], special values: 0: 1, 3: 2.5)
711 .offset_x = 0,
718 .offset_y = 0,
746 .offset_x = 0,
753 .offset_y = 0,
781 .offset_x = 0,
788 .offset_y = 0,
891 .crop_start_x = 0,
898 .crop_start_y = 0,
935 { OV5648_PSRAM_CTRL1_REG, 0x0d },
936 { OV5648_PSRAM_CTRLF_REG, 0xf5 },
954 0,
968 unsigned char data[2] = { address >> 8, address & 0xff }; in ov5648_read()
973 if (ret < 0) { in ov5648_read()
980 if (ret < 0) { in ov5648_read()
986 return 0; in ov5648_read()
991 unsigned char data[3] = { address >> 8, address & 0xff, value }; in ov5648_write()
996 if (ret < 0) { in ov5648_write()
1002 return 0; in ov5648_write()
1010 int ret = 0; in ov5648_write_sequence()
1012 for (i = 0; i < sequence_count; i++) { in ov5648_write_sequence()
1028 u8 value = 0; in ov5648_update_bits()
1042 return 0; in ov5648_update_bits()
1054 u8 value = 0; in ov5648_sw_standby()
1070 for (i = 0; i < ARRAY_SIZE(regs); i++) { in ov5648_chip_id_check()
1072 if (ret < 0) in ov5648_chip_id_check()
1083 return 0; in ov5648_chip_id_check()
1089 on ? 0 : OV5648_A_PWC_PK_O0_BP_REGULATOR_N); in ov5648_avdd_internal_power()
1098 ret = ov5648_write(sensor, OV5648_PAD_OEN1_REG, 0); in ov5648_pad_configure()
1102 ret = ov5648_write(sensor, OV5648_PAD_OEN2_REG, 0); in ov5648_pad_configure()
1193 ret = ov5648_write(sensor, OV5648_ISP_CTRL4_REG, 0); in ov5648_isp_configure()
1258 config = mode->pll1_config[0]; in ov5648_mode_pll1_configure()
1449 0); in ov5648_mode_configure()
1456 0); in ov5648_mode_configure()
1491 return 0; in ov5648_mode_configure()
1503 config = mode->pll1_config[0]; in ov5648_mode_mipi_clk_rate()
1509 return 0; in ov5648_mode_mipi_clk_rate()
1524 enable ? 0 : OV5648_MANUAL_CTRL_AEC_MANUAL_EN); in ov5648_exposure_auto_configure()
1552 u8 exposure_hh = 0, exposure_h = 0, exposure_l = 0; in ov5648_exposure_value()
1571 return 0; in ov5648_exposure_value()
1580 enable ? 0 : OV5648_MANUAL_CTRL_AGC_MANUAL_EN); in ov5648_gain_auto_configure()
1602 u8 gain_h = 0, gain_l = 0; in ov5648_gain_value()
1616 return 0; in ov5648_gain_value()
1625 enable ? 0 : OV5648_AWB_CTRL_GAIN_MANUAL_EN); in ov5648_white_balance_auto_configure()
1664 enable ? bits : 0); in ov5648_flip_vert_configure()
1673 enable ? bits : 0); in ov5648_flip_horz_configure()
1707 for (i = 0; i < ARRAY_SIZE(ov5648_link_freq_menu); i++) { in ov5648_state_mipi_configure()
1714 for (j = 0; j < sensor->endpoint.nr_of_link_frequencies; j++) { in ov5648_state_mipi_configure()
1749 return 0; in ov5648_state_mipi_configure()
1776 return 0; in ov5648_state_configure()
1784 ret = ov5648_state_configure(sensor, &ov5648_modes[0], in ov5648_state_init()
1785 ov5648_mbus_codes[0]); in ov5648_state_init()
1860 return 0; in ov5648_sensor_init()
1866 int ret = 0; in ov5648_sensor_power()
1913 gpiod_set_value_cansleep(sensor->reset, 0); in ov5648_sensor_power()
1914 gpiod_set_value_cansleep(sensor->powerdown, 0); in ov5648_sensor_power()
1959 return 0; in ov5648_g_volatile_ctrl()
1973 return 0; in ov5648_s_ctrl()
2031 return 0; in ov5648_s_ctrl()
2055 V4L2_EXPOSURE_MANUAL, 0, in ov5648_ctrls_init()
2066 v4l2_ctrl_new_std(handler, ops, V4L2_CID_AUTOGAIN, 0, 1, 1, 1); in ov5648_ctrls_init()
2071 v4l2_ctrl_auto_cluster(2, &ctrls->gain_auto, 0, true); in ov5648_ctrls_init()
2076 v4l2_ctrl_new_std(handler, ops, V4L2_CID_AUTO_WHITE_BALANCE, 0, in ov5648_ctrls_init()
2080 V4L2_CID_RED_BALANCE, 0, 4095, in ov5648_ctrls_init()
2084 V4L2_CID_BLUE_BALANCE, 0, 4095, in ov5648_ctrls_init()
2087 v4l2_ctrl_auto_cluster(3, &ctrls->white_balance_auto, 0, false); in ov5648_ctrls_init()
2091 v4l2_ctrl_new_std(handler, ops, V4L2_CID_HFLIP, 0, 1, 1, 0); in ov5648_ctrls_init()
2092 v4l2_ctrl_new_std(handler, ops, V4L2_CID_VFLIP, 0, 1, 1, 0); in ov5648_ctrls_init()
2098 0, 0, ov5648_test_pattern_menu); in ov5648_ctrls_init()
2105 0, ov5648_link_freq_menu); in ov5648_ctrls_init()
2124 return 0; in ov5648_ctrls_init()
2142 if (ret < 0) in ov5648_s_stream()
2158 return 0; in ov5648_s_stream()
2176 return 0; in ov5648_enum_mbus_code()
2214 return 0; in ov5648_get_fmt()
2224 u32 mbus_code = 0; in ov5648_set_fmt()
2226 int ret = 0; in ov5648_set_fmt()
2236 for (index = 0; index < ARRAY_SIZE(ov5648_mbus_codes); index++) { in ov5648_set_fmt()
2245 mbus_code = ov5648_mbus_codes[0]; in ov5648_set_fmt()
2277 int ret = 0; in ov5648_get_frame_interval()
2292 interval->interval = mode->frame_interval[0]; in ov5648_get_frame_interval()
2320 return 0; in ov5648_enum_frame_size()
2331 if (interval_enum->index > 0) in ov5648_enum_frame_interval()
2338 for (mode_index = 0, interval_index = 0; in ov5648_enum_frame_interval()
2356 interval_enum->interval = mode->frame_interval[0]; in ov5648_enum_frame_interval()
2365 return 0; in ov5648_enum_frame_interval()
2389 int ret = 0; in ov5648_suspend()
2415 int ret = 0; in ov5648_resume()
2578 return 0; in ov5648_probe()