Lines Matching +full:lane +full:- +full:polarities
1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
13 #include <linux/i2c-mux.h>
18 #include <media/v4l2-cci.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
93 #define MAX96717_MIPI_RX4 CCI_REG8(0x334) /* phy1 lane polarities */
95 #define MAX96717_MIPI_RX5 CCI_REG8(0x335) /* phy2 lane polarities */
154 priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev,
157 if (!priv->mux)
158 return -ENOMEM;
160 return i2c_mux_add_adapter(priv->mux, 0, 0);
165 return cci_update_bits(priv->regmap, MAX96717_FRONTOP0,
175 const u32 h_active = fmt->width;
180 const u32 v_active = fmt->height;
191 cci_update_bits(priv->regmap, MAX96717_VTX1,
194 dev_info(&priv->client->dev, "height: %d width: %d\n", fmt->height,
195 fmt->width);
197 cci_write(priv->regmap, MAX96717_VTX_VS_DLY, 0, &ret);
198 cci_write(priv->regmap, MAX96717_VTX_VS_HIGH, v_sw * h_tot, &ret);
199 cci_write(priv->regmap, MAX96717_VTX_VS_LOW,
201 cci_write(priv->regmap, MAX96717_VTX_HS_HIGH, h_sw, &ret);
202 cci_write(priv->regmap, MAX96717_VTX_HS_LOW, h_active + h_fp + h_bp,
204 cci_write(priv->regmap, MAX96717_VTX_V2D,
206 cci_write(priv->regmap, MAX96717_VTX_HS_CNT, v_tot, &ret);
207 cci_write(priv->regmap, MAX96717_VTX_DE_HIGH, h_active, &ret);
208 cci_write(priv->regmap, MAX96717_VTX_DE_LOW, h_fp + h_sw + h_bp,
210 cci_write(priv->regmap, MAX96717_VTX_DE_CNT, v_active, &ret);
212 cci_write(priv->regmap, MAX96717_VTX_CHKB_COLOR_A, 0xfecc00, &ret);
214 cci_write(priv->regmap, MAX96717_VTX_CHKB_COLOR_B, 0x006aa7, &ret);
215 cci_write(priv->regmap, MAX96717_VTX_CHKB_RPT_CNT_A, 0x3c, &ret);
216 cci_write(priv->regmap, MAX96717_VTX_CHKB_RPT_CNT_B, 0x3c, &ret);
217 cci_write(priv->regmap, MAX96717_VTX_CHKB_ALT, 0x3c, &ret);
218 cci_write(priv->regmap, MAX96717_VTX_GRAD_INC, 0x10, &ret);
229 if (priv->pattern)
232 cci_write(priv->regmap, MAX96717_VTX0, priv->pattern ? 0xfb : 0,
235 val = FIELD_PREP(MAX96717_VTX_MODE, priv->pattern);
236 cci_update_bits(priv->regmap, MAX96717_VTX29, MAX96717_VTX_MODE,
244 container_of(ctrl->handler, struct max96717_priv, ctrl_handler);
247 switch (ctrl->id) {
249 if (priv->enabled_source_streams)
250 return -EBUSY;
251 priv->pattern = ctrl->val;
254 return -EINVAL;
258 ret = cci_update_bits(priv->regmap, MAX96717_VIDEO_TX0,
260 priv->pattern ? 0 : MAX96717_VIDEO_AUTO_BPP,
267 return cci_update_bits(priv->regmap, MAX96717_MIPI_RX_EXT11,
269 priv->pattern ? 0 : MAX96717_TUN_MODE, &ret);
289 ret = cci_read(priv->regmap, MAX96717_GPIO_REG_A(offset),
305 cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(offset),
316 ret = cci_read(priv->regmap, MAX96717_GPIO_REG_A(offset), &val, NULL);
328 return cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(offset),
338 return cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(offset),
345 struct device *dev = &priv->client->dev;
346 struct gpio_chip *gc = &priv->gpio_chip;
349 gc->label = dev_name(dev);
350 gc->parent = dev;
351 gc->owner = THIS_MODULE;
352 gc->ngpio = MAX96717_NUM_GPIO;
353 gc->base = -1;
354 gc->can_sleep = true;
355 gc->get_direction = max96717_gpio_get_direction;
356 gc->direction_input = max96717_gpio_direction_in;
357 gc->direction_output = max96717_gpio_direction_out;
358 gc->set = max96717_gpiochip_set;
359 gc->get = max96717_gpiochip_get;
360 gc->of_gpio_n_cells = 2;
363 for (i = 0; i < gc->ngpio; i++)
364 cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(i),
411 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams)
412 return -EBUSY;
425 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE &&
426 priv->enabled_source_streams)
427 return -EBUSY;
430 if (format->pad == MAX96717_PAD_SOURCE)
434 fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream);
436 return -EINVAL;
438 *fmt = format->format;
441 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad,
442 format->stream);
444 return -EINVAL;
445 *fmt = format->format;
447 stream_source_mask = BIT(format->stream);
478 cci_read(priv->regmap, MAX96717_VIDEO_TX2, &val, NULL);
486 struct device *dev = &priv->client->dev;
502 if (!priv->enabled_source_streams)
509 if (!priv->pattern) {
516 ret = v4l2_subdev_enable_streams(priv->source_sd,
517 priv->source_sd_pad,
523 priv->enabled_source_streams |= streams_mask;
528 if (!priv->enabled_source_streams)
546 priv->enabled_source_streams &= ~streams_mask;
547 if (!priv->enabled_source_streams)
550 if (!priv->pattern) {
559 ret = v4l2_subdev_disable_streams(priv->source_sd,
560 priv->source_sd_pad,
598 struct max96717_priv *priv = sd_to_max96717(notifier->sd);
599 struct device *dev = &priv->client->dev;
602 ret = media_entity_get_fwnode_pad(&source_subdev->entity,
603 source_subdev->fwnode,
607 source_subdev->name);
611 priv->source_sd = source_subdev;
612 priv->source_sd_pad = ret;
614 ret = media_create_pad_link(&source_subdev->entity, priv->source_sd_pad,
615 &priv->sd.entity, 0,
619 dev_err(dev, "Unable to link %s:%u -> %s:0\n",
620 source_subdev->name, priv->source_sd_pad,
621 priv->sd.name);
634 struct device *dev = &priv->client->dev;
643 return -ENODEV;
646 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd);
648 asd = v4l2_async_nf_add_fwnode_remote(&priv->notifier, ep_fwnode,
655 v4l2_async_nf_cleanup(&priv->notifier);
659 priv->notifier.ops = &max96717_notify_ops;
661 ret = v4l2_async_nf_register(&priv->notifier);
664 v4l2_async_nf_cleanup(&priv->notifier);
673 struct device *dev = &priv->client->dev;
676 v4l2_i2c_subdev_init(&priv->sd, priv->client, &max96717_subdev_ops);
677 priv->sd.internal_ops = &max96717_internal_ops;
679 v4l2_ctrl_handler_init(&priv->ctrl_handler, 1);
680 priv->sd.ctrl_handler = &priv->ctrl_handler;
682 v4l2_ctrl_new_std_menu_items(&priv->ctrl_handler,
685 ARRAY_SIZE(max96717_test_pattern) - 1,
687 if (priv->ctrl_handler.error) {
688 ret = priv->ctrl_handler.error;
692 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS;
693 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
694 priv->sd.entity.ops = &max96717_entity_ops;
696 priv->pads[MAX96717_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
697 priv->pads[MAX96717_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
699 ret = media_entity_pads_init(&priv->sd.entity, 2, priv->pads);
705 ret = v4l2_subdev_init_finalize(&priv->sd);
718 ret = v4l2_async_register_subdev(&priv->sd);
727 v4l2_async_nf_unregister(&priv->notifier);
728 v4l2_async_nf_cleanup(&priv->notifier);
730 v4l2_subdev_cleanup(&priv->sd);
732 media_entity_cleanup(&priv->sd.entity);
734 v4l2_ctrl_handler_free(&priv->ctrl_handler);
741 v4l2_async_unregister_subdev(&priv->sd);
742 v4l2_async_nf_unregister(&priv->notifier);
743 v4l2_async_nf_cleanup(&priv->notifier);
744 v4l2_subdev_cleanup(&priv->sd);
745 media_entity_cleanup(&priv->sd.entity);
746 v4l2_ctrl_handler_free(&priv->ctrl_handler);
766 return max96717_predef_freqs[priv->pll_predef_index].freq;
776 diff_new = abs(rate - max96717_predef_freqs[i].freq);
790 struct device *dev = &priv->client->dev;
820 cci_write(priv->regmap, REF_VTG0, val, &ret);
821 cci_update_bits(priv->regmap, REF_VTG0, REFGEN_RST | REFGEN_EN,
826 priv->pll_predef_index = idx;
835 return cci_update_bits(priv->regmap, MAX96717_REG6, RCLKEN,
843 cci_update_bits(priv->regmap, MAX96717_REG6, RCLKEN, 0, NULL);
856 struct device *dev = &priv->client->dev;
862 return -ENOMEM;
865 ret = cci_update_bits(priv->regmap, MAX96717_REG3, MAX96717_RCLKSEL,
868 cci_update_bits(priv->regmap, PIO_SLEW_1, BIT(5) | BIT(4), 0, &ret);
872 priv->clk_hw.init = &init;
875 ret = max96717_clk_set_rate(&priv->clk_hw,
880 ret = devm_clk_hw_register(dev, &priv->clk_hw);
886 &priv->clk_hw);
900 struct v4l2_mbus_config_mipi_csi2 *mipi = &priv->mipi_csi2;
902 unsigned int nlanes, lane, val = 0;
905 nlanes = mipi->num_data_lanes;
907 ret = cci_update_bits(priv->regmap, MAX96717_MIPI_RX1,
910 nlanes - 1), NULL);
913 for (lane = 0; lane < nlanes + 1; lane++) {
914 if (!mipi->lane_polarities[lane])
916 /* Clock lane */
917 if (lane == 0)
919 else if (lane < 3)
920 val |= BIT(lane - 1);
922 val |= BIT(lane);
925 cci_update_bits(priv->regmap, MAX96717_MIPI_RX5,
929 cci_update_bits(priv->regmap, MAX96717_MIPI_RX4,
934 for (lane = 0, val = 0; lane < nlanes; lane++) {
935 val |= (mipi->data_lanes[lane] - 1) << (lane * 2);
936 lanes_used |= BIT(mipi->data_lanes[lane] - 1);
943 for (; lane < MAX96717_CSI_NLANES; lane++) {
947 val |= idx << (lane * 2);
951 cci_update_bits(priv->regmap, MAX96717_MIPI_RX3,
955 return cci_update_bits(priv->regmap, MAX96717_MIPI_RX2,
963 struct device *dev = &priv->client->dev;
967 ret = cci_read(priv->regmap, MAX96717_DEV_ID, &dev_id, NULL);
973 return dev_err_probe(dev, -EOPNOTSUPP,
976 ret = cci_read(priv->regmap, MAX96717_DEV_REV, &val, NULL);
984 ret = cci_read(priv->regmap, MAX96717_MIPI_RX_EXT11, &val, NULL);
990 return dev_err_probe(dev, -EOPNOTSUPP,
998 struct device *dev = &priv->client->dev;
1007 return dev_err_probe(dev, -ENOENT, "no endpoint found\n");
1018 return dev_err_probe(dev, -EINVAL,
1021 priv->mipi_csi2 = vep.bus.mipi_csi2;
1028 struct device *dev = &client->dev;
1034 return -ENOMEM;
1036 priv->client = client;
1037 priv->regmap = devm_cci_regmap_init_i2c(client, 16);
1038 if (IS_ERR(priv->regmap)) {
1039 ret = PTR_ERR(priv->regmap);
1054 return dev_err_probe(&client->dev, ret,
1081 i2c_mux_del_adapters(priv->mux);