24 #define IMX415_PIXEL_ARRAY_TOP	  0
25 #define IMX415_PIXEL_ARRAY_LEFT	  0
32 #define IMX415_MODE		  CCI_REG8(0x3000)
33 #define IMX415_MODE_OPERATING	  (0)
34 #define IMX415_MODE_STANDBY	  BIT(0)
35 #define IMX415_REGHOLD		  CCI_REG8(0x3001)
36 #define IMX415_REGHOLD_INVALID	  (0)
37 #define IMX415_REGHOLD_VALID	  BIT(0)
38 #define IMX415_XMSTA		  CCI_REG8(0x3002)
39 #define IMX415_XMSTA_START	  (0)
40 #define IMX415_XMSTA_STOP	  BIT(0)
41 #define IMX415_BCWAIT_TIME	  CCI_REG16_LE(0x3008)
42 #define IMX415_CPWAIT_TIME	  CCI_REG16_LE(0x300a)
43 #define IMX415_WINMODE		  CCI_REG8(0x301c)
44 #define IMX415_ADDMODE		  CCI_REG8(0x3022)
45 #define IMX415_REVERSE		  CCI_REG8(0x3030)
46 #define IMX415_HREVERSE_SHIFT	  (0)
47 #define IMX415_VREVERSE_SHIFT	  BIT(0)
48 #define IMX415_ADBIT		  CCI_REG8(0x3031)
49 #define IMX415_MDBIT		  CCI_REG8(0x3032)
50 #define IMX415_SYS_MODE		  CCI_REG8(0x3033)
51 #define IMX415_OUTSEL		  CCI_REG8(0x30c0)
52 #define IMX415_DRV		  CCI_REG8(0x30c1)
53 #define IMX415_VMAX		  CCI_REG24_LE(0x3024)
54 #define IMX415_HMAX		  CCI_REG16_LE(0x3028)
55 #define IMX415_SHR0		  CCI_REG24_LE(0x3050)
56 #define IMX415_GAIN_PCG_0	  CCI_REG16_LE(0x3090)
57 #define IMX415_AGAIN_MIN	  0
60 #define IMX415_BLKLEVEL		  CCI_REG16_LE(0x30e2)
62 #define IMX415_TPG_EN_DUOUT	  CCI_REG8(0x30e4)
63 #define IMX415_TPG_PATSEL_DUOUT	  CCI_REG8(0x30e6)
64 #define IMX415_TPG_COLORWIDTH	  CCI_REG8(0x30e8)
65 #define IMX415_TESTCLKEN_MIPI	  CCI_REG8(0x3110)
66 #define IMX415_INCKSEL1		  CCI_REG8(0x3115)
67 #define IMX415_INCKSEL2		  CCI_REG8(0x3116)
68 #define IMX415_INCKSEL3		  CCI_REG16_LE(0x3118)
69 #define IMX415_INCKSEL4		  CCI_REG16_LE(0x311a)
70 #define IMX415_INCKSEL5		  CCI_REG8(0x311e)
71 #define IMX415_DIG_CLP_MODE	  CCI_REG8(0x32c8)
72 #define IMX415_WRJ_OPEN		  CCI_REG8(0x3390)
73 #define IMX415_SENSOR_INFO	  CCI_REG16_LE(0x3f12)
74 #define IMX415_SENSOR_INFO_MASK	  0xfff
75 #define IMX415_CHIP_ID		  0x514
76 #define IMX415_LANEMODE		  CCI_REG16_LE(0x4001)
79 #define IMX415_TXCLKESC_FREQ	  CCI_REG16_LE(0x4004)
80 #define IMX415_INCKSEL6		  CCI_REG8(0x400c)
81 #define IMX415_TCLKPOST		  CCI_REG16_LE(0x4018)
82 #define IMX415_TCLKPREPARE	  CCI_REG16_LE(0x401a)
83 #define IMX415_TCLKTRAIL	  CCI_REG16_LE(0x401c)
84 #define IMX415_TCLKZERO		  CCI_REG16_LE(0x401e)
85 #define IMX415_THSPREPARE	  CCI_REG16_LE(0x4020)
86 #define IMX415_THSZERO		  CCI_REG16_LE(0x4022)
87 #define IMX415_THSTRAIL		  CCI_REG16_LE(0x4024)
88 #define IMX415_THSEXIT		  CCI_REG16_LE(0x4026)
89 #define IMX415_TLPX		  CCI_REG16_LE(0x4028)
90 #define IMX415_INCKSEL7		  CCI_REG8(0x4074)
119 		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
120 		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
121 		.regs[2] = { IMX415_SYS_MODE, 0x7 },
122 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
123 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
124 		.regs[5] = { IMX415_INCKSEL3, 0x084 },
125 		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
126 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
127 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
128 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
129 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
134 		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
135 		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
136 		.regs[2] = { IMX415_SYS_MODE, 0x7 },
137 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
138 		.regs[4] = { IMX415_INCKSEL2, 0x24 },
139 		.regs[5] = { IMX415_INCKSEL3, 0x080 },
140 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
141 		.regs[7] = { IMX415_INCKSEL5, 0x24 },
142 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
143 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
144 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0984 },
149 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
150 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
151 		.regs[2] = { IMX415_SYS_MODE, 0x7 },
152 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
153 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
154 		.regs[5] = { IMX415_INCKSEL3, 0x080 },
155 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
156 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
157 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
158 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
159 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
164 		.regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
165 		.regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
166 		.regs[2] = { IMX415_SYS_MODE, 0x9 },
167 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
168 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
169 		.regs[5] = { IMX415_INCKSEL3, 0x0B4 },
170 		.regs[6] = { IMX415_INCKSEL4, 0x0FC },
171 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
172 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
173 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
174 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
179 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },
180 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },
181 		.regs[2] = { IMX415_SYS_MODE, 0x9 },
182 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
183 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
184 		.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
185 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
186 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
187 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
188 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
189 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },
194 		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
195 		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
196 		.regs[2] = { IMX415_SYS_MODE, 0x5 },
197 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
198 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
199 		.regs[5] = { IMX415_INCKSEL3, 0x0C6 },
200 		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
201 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
202 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
203 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
204 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
209 		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
210 		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
211 		.regs[2] = { IMX415_SYS_MODE, 0x5 },
212 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
213 		.regs[4] = { IMX415_INCKSEL2, 0x24 },
214 		.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
215 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
216 		.regs[7] = { IMX415_INCKSEL5, 0x24 },
217 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
218 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
219 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
224 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
225 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
226 		.regs[2] = { IMX415_SYS_MODE, 0x5 },
227 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
228 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
229 		.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
230 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
231 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
232 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
233 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
234 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
239 		.regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
240 		.regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
241 		.regs[2] = { IMX415_SYS_MODE, 0x8 },
242 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
243 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
244 		.regs[5] = { IMX415_INCKSEL3, 0x0B4 },
245 		.regs[6] = { IMX415_INCKSEL4, 0x0FC },
246 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
247 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
248 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
249 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
254 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },
255 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },
256 		.regs[2] = { IMX415_SYS_MODE, 0x8 },
257 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
258 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
259 		.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
260 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
261 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
262 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
263 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
264 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },
269 		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
270 		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
271 		.regs[2] = { IMX415_SYS_MODE, 0x8 },
272 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
273 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
274 		.regs[5] = { IMX415_INCKSEL3, 0x0A5 },
275 		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
276 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
277 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
278 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
279 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
284 		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
285 		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
286 		.regs[2] = { IMX415_SYS_MODE, 0x8 },
287 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
288 		.regs[4] = { IMX415_INCKSEL2, 0x24 },
289 		.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
290 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
291 		.regs[7] = { IMX415_INCKSEL5, 0x24 },
292 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
293 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
294 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
299 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
300 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
301 		.regs[2] = { IMX415_SYS_MODE, 0x8 },
302 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
303 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
304 		.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
305 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
306 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
307 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
308 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
309 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
314 		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
315 		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
316 		.regs[2] = { IMX415_SYS_MODE, 0x4 },
317 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
318 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
319 		.regs[5] = { IMX415_INCKSEL3, 0x0C6 },
320 		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
321 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
322 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
323 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
324 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
329 		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
330 		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
331 		.regs[2] = { IMX415_SYS_MODE, 0x4 },
332 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
333 		.regs[4] = { IMX415_INCKSEL2, 0x24 },
334 		.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
335 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
336 		.regs[7] = { IMX415_INCKSEL5, 0x24 },
337 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
338 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
339 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
344 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
345 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
346 		.regs[2] = { IMX415_SYS_MODE, 0x4 },
347 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
348 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
349 		.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
350 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
351 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
352 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
353 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
354 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
359 		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
360 		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
361 		.regs[2] = { IMX415_SYS_MODE, 0x2 },
362 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
363 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
364 		.regs[5] = { IMX415_INCKSEL3, 0x0E7 },
365 		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
366 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
367 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
368 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
369 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
374 		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
375 		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
376 		.regs[2] = { IMX415_SYS_MODE, 0x2 },
377 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
378 		.regs[4] = { IMX415_INCKSEL2, 0x24 },
379 		.regs[5] = { IMX415_INCKSEL3, 0x0E0 },
380 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
381 		.regs[7] = { IMX415_INCKSEL5, 0x24 },
382 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
383 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
384 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
389 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
390 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
391 		.regs[2] = { IMX415_SYS_MODE, 0x2 },
392 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
393 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
394 		.regs[5] = { IMX415_INCKSEL3, 0x0E0 },
395 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
396 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
397 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
398 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
399 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
404 		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
405 		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
406 		.regs[2] = { IMX415_SYS_MODE, 0x0 },
407 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
408 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
409 		.regs[5] = { IMX415_INCKSEL3, 0x108 },
410 		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
411 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
412 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
413 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
414 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
419 		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
420 		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
421 		.regs[2] = { IMX415_SYS_MODE, 0x0 },
422 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
423 		.regs[4] = { IMX415_INCKSEL2, 0x24 },
424 		.regs[5] = { IMX415_INCKSEL3, 0x100 },
425 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
426 		.regs[7] = { IMX415_INCKSEL5, 0x24 },
427 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
428 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
429 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
434 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
435 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
436 		.regs[2] = { IMX415_SYS_MODE, 0x0 },
437 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
438 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
439 		.regs[5] = { IMX415_INCKSEL3, 0x100 },
440 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
441 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
442 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
443 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
444 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
450 	{ IMX415_VMAX, 0x08CA },
451 	{ IMX415_HMAX, 0x07F0 },
453 	{ IMX415_TCLKPOST, 0x006F },
454 	{ IMX415_TCLKPREPARE, 0x002F },
455 	{ IMX415_TCLKTRAIL, 0x002F },
456 	{ IMX415_TCLKZERO, 0x00BF },
457 	{ IMX415_THSPREPARE, 0x002F },
458 	{ IMX415_THSZERO, 0x0057 },
459 	{ IMX415_THSTRAIL, 0x002F },
460 	{ IMX415_THSEXIT, 0x004F },
461 	{ IMX415_TLPX, 0x0027 },
466 	{ IMX415_VMAX, 0x08CA },
467 	{ IMX415_HMAX, 0x042A },
469 	{ IMX415_TCLKPOST, 0x009F },
470 	{ IMX415_TCLKPREPARE, 0x0057 },
471 	{ IMX415_TCLKTRAIL, 0x0057 },
472 	{ IMX415_TCLKZERO, 0x0187 },
473 	{ IMX415_THSPREPARE, 0x005F },
474 	{ IMX415_THSZERO, 0x00A7 },
475 	{ IMX415_THSTRAIL, 0x005F },
476 	{ IMX415_THSEXIT, 0x0097 },
477 	{ IMX415_TLPX, 0x004F },
482 	{ IMX415_VMAX, 0x08CA },
483 	{ IMX415_HMAX, 0x044C },
485 	{ IMX415_TCLKPOST, 0x007F },
486 	{ IMX415_TCLKPREPARE, 0x0037 },
487 	{ IMX415_TCLKTRAIL, 0x0037 },
488 	{ IMX415_TCLKZERO, 0x00F7 },
489 	{ IMX415_THSPREPARE, 0x003F },
490 	{ IMX415_THSZERO, 0x006F },
491 	{ IMX415_THSTRAIL, 0x003F },
492 	{ IMX415_THSEXIT, 0x005F },
493 	{ IMX415_TLPX, 0x002F },
614 	{ IMX415_WINMODE, 0x00 },
615 	{ IMX415_ADDMODE, 0x00 },
616 	{ IMX415_REVERSE, 0x00 },
618 	{ IMX415_ADBIT, 0x00 },
619 	{ IMX415_MDBIT, 0x00 },
621 	{ IMX415_OUTSEL, 0x22 },
622 	{ IMX415_DRV, 0x00 },
625 	{ CCI_REG8(0x32D4), 0x21 },
626 	{ CCI_REG8(0x32EC), 0xA1 },
627 	{ CCI_REG8(0x3452), 0x7F },
628 	{ CCI_REG8(0x3453), 0x03 },
629 	{ CCI_REG8(0x358A), 0x04 },
630 	{ CCI_REG8(0x35A1), 0x02 },
631 	{ CCI_REG8(0x36BC), 0x0C },
632 	{ CCI_REG8(0x36CC), 0x53 },
633 	{ CCI_REG8(0x36CD), 0x00 },
634 	{ CCI_REG8(0x36CE), 0x3C },
635 	{ CCI_REG8(0x36D0), 0x8C },
636 	{ CCI_REG8(0x36D1), 0x00 },
637 	{ CCI_REG8(0x36D2), 0x71 },
638 	{ CCI_REG8(0x36D4), 0x3C },
639 	{ CCI_REG8(0x36D6), 0x53 },
640 	{ CCI_REG8(0x36D7), 0x00 },
641 	{ CCI_REG8(0x36D8), 0x71 },
642 	{ CCI_REG8(0x36DA), 0x8C },
643 	{ CCI_REG8(0x36DB), 0x00 },
644 	{ CCI_REG8(0x3724), 0x02 },
645 	{ CCI_REG8(0x3726), 0x02 },
646 	{ CCI_REG8(0x3732), 0x02 },
647 	{ CCI_REG8(0x3734), 0x03 },
648 	{ CCI_REG8(0x3736), 0x03 },
649 	{ CCI_REG8(0x3742), 0x03 },
650 	{ CCI_REG8(0x3862), 0xE0 },
651 	{ CCI_REG8(0x38CC), 0x30 },
652 	{ CCI_REG8(0x38CD), 0x2F },
653 	{ CCI_REG8(0x395C), 0x0C },
654 	{ CCI_REG8(0x3A42), 0xD1 },
655 	{ CCI_REG8(0x3A4C), 0x77 },
656 	{ CCI_REG8(0x3AE0), 0x02 },
657 	{ CCI_REG8(0x3AEC), 0x0C },
658 	{ CCI_REG8(0x3B00), 0x2E },
659 	{ CCI_REG8(0x3B06), 0x29 },
660 	{ CCI_REG8(0x3B98), 0x25 },
661 	{ CCI_REG8(0x3B99), 0x21 },
662 	{ CCI_REG8(0x3B9B), 0x13 },
663 	{ CCI_REG8(0x3B9C), 0x13 },
664 	{ CCI_REG8(0x3B9D), 0x13 },
665 	{ CCI_REG8(0x3B9E), 0x13 },
666 	{ CCI_REG8(0x3BA1), 0x00 },
667 	{ CCI_REG8(0x3BA2), 0x06 },
668 	{ CCI_REG8(0x3BA3), 0x0B },
669 	{ CCI_REG8(0x3BA4), 0x10 },
670 	{ CCI_REG8(0x3BA5), 0x14 },
671 	{ CCI_REG8(0x3BA6), 0x18 },
672 	{ CCI_REG8(0x3BA7), 0x1A },
673 	{ CCI_REG8(0x3BA8), 0x1A },
674 	{ CCI_REG8(0x3BA9), 0x1A },
675 	{ CCI_REG8(0x3BAC), 0xED },
676 	{ CCI_REG8(0x3BAD), 0x01 },
677 	{ CCI_REG8(0x3BAE), 0xF6 },
678 	{ CCI_REG8(0x3BAF), 0x02 },
679 	{ CCI_REG8(0x3BB0), 0xA2 },
680 	{ CCI_REG8(0x3BB1), 0x03 },
681 	{ CCI_REG8(0x3BB2), 0xE0 },
682 	{ CCI_REG8(0x3BB3), 0x03 },
683 	{ CCI_REG8(0x3BB4), 0xE0 },
684 	{ CCI_REG8(0x3BB5), 0x03 },
685 	{ CCI_REG8(0x3BB6), 0xE0 },
686 	{ CCI_REG8(0x3BB7), 0x03 },
687 	{ CCI_REG8(0x3BB8), 0xE0 },
688 	{ CCI_REG8(0x3BBA), 0xE0 },
689 	{ CCI_REG8(0x3BBC), 0xDA },
690 	{ CCI_REG8(0x3BBE), 0x88 },
691 	{ CCI_REG8(0x3BC0), 0x44 },
692 	{ CCI_REG8(0x3BC2), 0x7B },
693 	{ CCI_REG8(0x3BC4), 0xA2 },
694 	{ CCI_REG8(0x3BC8), 0xBD },
695 	{ CCI_REG8(0x3BCA), 0xBD },
705 	int ret = 0;  in imx415_set_testpattern()
708 		cci_write(sensor->regmap, IMX415_BLKLEVEL, 0x00, &ret);  in imx415_set_testpattern()
709 		cci_write(sensor->regmap, IMX415_TPG_EN_DUOUT, 0x01, &ret);  in imx415_set_testpattern()
712 		cci_write(sensor->regmap, IMX415_TPG_COLORWIDTH, 0x01, &ret);  in imx415_set_testpattern()
713 		cci_write(sensor->regmap, IMX415_TESTCLKEN_MIPI, 0x20, &ret);  in imx415_set_testpattern()
714 		cci_write(sensor->regmap, IMX415_DIG_CLP_MODE, 0x00, &ret);  in imx415_set_testpattern()
715 		cci_write(sensor->regmap, IMX415_WRJ_OPEN, 0x00, &ret);  in imx415_set_testpattern()
719 		cci_write(sensor->regmap, IMX415_TPG_EN_DUOUT, 0x00, &ret);  in imx415_set_testpattern()
720 		cci_write(sensor->regmap, IMX415_TESTCLKEN_MIPI, 0x00, &ret);  in imx415_set_testpattern()
721 		cci_write(sensor->regmap, IMX415_DIG_CLP_MODE, 0x01, &ret);  in imx415_set_testpattern()
722 		cci_write(sensor->regmap, IMX415_WRJ_OPEN, 0x01, &ret);  in imx415_set_testpattern()
724 	return 0;  in imx415_set_testpattern()
738 		return 0;  in imx415_s_ctrl()
741 	format = v4l2_subdev_state_get_format(state, 0);  in imx415_s_ctrl()
796 	if (ret < 0)  in imx415_ctrls_init()
801 	for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); ++i) {  in imx415_ctrls_init()
851 					  V4L2_CID_HFLIP, 0, 1, 1, 0);  in imx415_ctrls_init()
853 					  V4L2_CID_VFLIP, 0, 1, 1, 0);  in imx415_ctrls_init()
858 				     0, 0, imx415_test_pattern_menu);  in imx415_ctrls_init()
871 	return 0;  in imx415_ctrls_init()
876 	int ret = 0;  in imx415_set_mode()
893 	return 0;  in imx415_set_mode()
926 	return 0;  in imx415_wakeup()
966 	if (ret < 0)  in imx415_s_stream()
974 	if (ret < 0)  in imx415_s_stream()
981 	ret = 0;  in imx415_s_stream()
1002 	if (code->index != 0)  in imx415_enum_mbus_code()
1007 	return 0;  in imx415_enum_mbus_code()
1018 	if (fse->index > 0 || fse->code != format->code)  in imx415_enum_frame_size()
1025 	return 0;  in imx415_enum_frame_size()
1046 	return 0;  in imx415_set_format()
1062 		return 0;  in imx415_get_selection()
1080 	return 0;  in imx415_init_state()
1121 	if (ret < 0) {  in imx415_subdev_init()
1129 	return 0;  in imx415_subdev_init()
1144 	if (ret < 0)  in imx415_power_on()
1147 	gpiod_set_value_cansleep(sensor->reset, 0);  in imx415_power_on()
1152 	if (ret < 0)  in imx415_power_on()
1162 	return 0;  in imx415_power_on()
1192 	if (ret < 0) {  in imx415_identify_model()
1206 				    "invalid device model 0x%04x\n", model);  in imx415_identify_model()
1210 	ret = 0;  in imx415_identify_model()
1221 	for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) {  in imx415_check_inck()
1230 		return 0;  in imx415_check_inck()
1244 	for (i = 0; i < ARRAY_SIZE(sensor->supplies); ++i)  in imx415_parse_hw_config()
1296 	for (i = 0; i < bus_cfg.nr_of_link_frequencies; ++i) {  in imx415_parse_hw_config()
1304 		for (j = 0; j < ARRAY_SIZE(supported_modes); ++j) {  in imx415_parse_hw_config()
1323 	for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) {  in imx415_parse_hw_config()
1337 	ret = 0;  in imx415_parse_hw_config()
1392 	if (ret < 0)  in imx415_probe()
1404 	return 0;  in imx415_probe()
1451 	return 0;  in imx415_runtime_suspend()