Lines Matching +full:0 +full:x3a00
21 #define IMX334_REG_MODE_SELECT CCI_REG8(0x3000)
22 #define IMX334_MODE_STANDBY 0x01
23 #define IMX334_MODE_STREAMING 0x00
26 #define IMX334_REG_VMAX CCI_REG24_LE(0x3030)
28 #define IMX334_REG_HMAX CCI_REG16_LE(0x3034)
30 #define IMX334_REG_OPB_SIZE_V CCI_REG8(0x304c)
31 #define IMX334_REG_ADBIT CCI_REG8(0x3050)
32 #define IMX334_REG_MDBIT CCI_REG8(0x319d)
33 #define IMX334_REG_ADBIT1 CCI_REG16_LE(0x341c)
34 #define IMX334_REG_Y_OUT_SIZE CCI_REG16_LE(0x3308)
35 #define IMX334_REG_XVS_XHS_OUTSEL CCI_REG8(0x31a0)
36 #define IMX334_REG_XVS_XHS_DRV CCI_REG8(0x31a1)
39 #define IMX334_REG_ID CCI_REG8(0x3044)
40 #define IMX334_ID 0x1e
43 #define IMX334_REG_SHUTTER CCI_REG24_LE(0x3058)
47 #define IMX334_EXPOSURE_DEFAULT 0x0648
49 #define IMX334_REG_LANEMODE CCI_REG8(0x3a01)
54 #define IMX334_REG_AREA3_ST_ADR_1 CCI_REG16_LE(0x3074)
55 #define IMX334_REG_AREA3_ST_ADR_2 CCI_REG16_LE(0x308e)
56 #define IMX334_REG_UNREAD_PARAM5 CCI_REG16_LE(0x30b6)
57 #define IMX334_REG_AREA3_WIDTH_1 CCI_REG16_LE(0x3076)
58 #define IMX334_REG_AREA3_WIDTH_2 CCI_REG16_LE(0x3090)
59 #define IMX334_REG_BLACK_OFSET_ADR CCI_REG16_LE(0x30c6)
60 #define IMX334_REG_UNRD_LINE_MAX CCI_REG16_LE(0x30ce)
61 #define IMX334_REG_UNREAD_ED_ADR CCI_REG16_LE(0x30d8)
62 #define IMX334_REG_UNREAD_PARAM6 CCI_REG16_LE(0x3116)
64 #define IMX334_REG_VREVERSE CCI_REG8(0x304f)
65 #define IMX334_REG_HREVERSE CCI_REG8(0x304e)
68 #define IMX334_REG_HADD_VADD CCI_REG8(0x3199)
69 #define IMX334_REG_VALID_EXPAND CCI_REG8(0x31dd)
70 #define IMX334_REG_TCYCLE CCI_REG8(0x3300)
73 #define IMX334_REG_AGAIN CCI_REG16_LE(0x30e8)
74 #define IMX334_AGAIN_MIN 0
77 #define IMX334_AGAIN_DEFAULT 0
80 #define IMX334_REG_HOLD CCI_REG8(0x3001)
82 #define IMX334_REG_MASTER_MODE CCI_REG8(0x3002)
83 #define IMX334_REG_WINMODE CCI_REG8(0x3018)
84 #define IMX334_REG_HTRIMMING_START CCI_REG16_LE(0x302c)
85 #define IMX334_REG_HNUM CCI_REG16_LE(0x302e)
91 #define IMX334_REG_BCWAIT_TIME CCI_REG8(0x300c)
92 #define IMX334_REG_CPWAIT_TIME CCI_REG8(0x300d)
93 #define IMX334_REG_INCKSEL1 CCI_REG16_LE(0x314c)
94 #define IMX334_REG_INCKSEL2 CCI_REG8(0x315a)
95 #define IMX334_REG_INCKSEL3 CCI_REG8(0x3168)
96 #define IMX334_REG_INCKSEL4 CCI_REG8(0x316a)
97 #define IMX334_REG_SYS_MODE CCI_REG8(0x319e)
99 #define IMX334_REG_TCLKPOST CCI_REG16_LE(0x3a18)
100 #define IMX334_REG_TCLKPREPARE CCI_REG16_LE(0x3a1a)
101 #define IMX334_REG_TCLKTRAIL CCI_REG16_LE(0x3a1c)
102 #define IMX334_REG_TCLKZERO CCI_REG16_LE(0x3a1e)
103 #define IMX334_REG_THSPREPARE CCI_REG16_LE(0x3a20)
104 #define IMX334_REG_THSZERO CCI_REG16_LE(0x3a22)
105 #define IMX334_REG_THSTRAIL CCI_REG16_LE(0x3a24)
106 #define IMX334_REG_THSEXIT CCI_REG16_LE(0x3a26)
107 #define IMX334_REG_TPLX CCI_REG16_LE(0x3a28)
114 #define IMX334_REG_MIN 0x00
115 #define IMX334_REG_MAX 0xfffff
118 #define IMX334_REG_TP CCI_REG8(0x329e)
119 #define IMX334_TP_COLOR_HBARS 0xa
120 #define IMX334_TP_COLOR_VBARS 0xb
122 #define IMX334_TPG_EN_DOUT CCI_REG8(0x329c)
123 #define IMX334_TP_ENABLE 0x1
124 #define IMX334_TP_DISABLE 0x0
126 #define IMX334_TPG_COLORW CCI_REG8(0x32a0)
127 #define IMX334_TPG_COLORW_120P 0x13
129 #define IMX334_TP_CLK_EN CCI_REG8(0x3148)
130 #define IMX334_TP_CLK_EN_VAL 0x10
131 #define IMX334_TP_CLK_DIS_VAL 0x0
133 #define IMX334_DIG_CLP_MODE CCI_REG8(0x3280)
221 { IMX334_REG_WINMODE, 0x04 },
222 { IMX334_REG_VMAX, 0x0008ca },
223 { IMX334_REG_HMAX, 0x044c },
224 { IMX334_REG_BLACK_OFSET_ADR, 0x0000 },
225 { IMX334_REG_UNRD_LINE_MAX, 0x0000 },
226 { IMX334_REG_OPB_SIZE_V, 0x00 },
227 { IMX334_REG_HREVERSE, 0x00 },
228 { IMX334_REG_VREVERSE, 0x00 },
229 { IMX334_REG_UNREAD_PARAM5, 0x0000 },
230 { IMX334_REG_UNREAD_PARAM6, 0x0008 },
231 { IMX334_REG_XVS_XHS_OUTSEL, 0x20 },
232 { IMX334_REG_XVS_XHS_DRV, 0x0f },
233 { IMX334_REG_BCWAIT_TIME, 0x3b },
234 { IMX334_REG_CPWAIT_TIME, 0x2a },
235 { IMX334_REG_INCKSEL1, 0x0129 },
236 { IMX334_REG_INCKSEL2, 0x06 },
237 { IMX334_REG_INCKSEL3, 0xa0 },
238 { IMX334_REG_INCKSEL4, 0x7e },
239 { IMX334_REG_SYS_MODE, 0x02 },
240 { IMX334_REG_HADD_VADD, 0x00 },
241 { IMX334_REG_VALID_EXPAND, 0x03 },
242 { IMX334_REG_TCYCLE, 0x00 },
243 { IMX334_REG_TCLKPOST, 0x007f },
244 { IMX334_REG_TCLKPREPARE, 0x0037 },
245 { IMX334_REG_TCLKTRAIL, 0x0037 },
246 { IMX334_REG_TCLKZERO, 0xf7 },
247 { IMX334_REG_THSPREPARE, 0x002f },
248 { CCI_REG8(0x3078), 0x02 },
249 { CCI_REG8(0x3079), 0x00 },
250 { CCI_REG8(0x307a), 0x00 },
251 { CCI_REG8(0x307b), 0x00 },
252 { CCI_REG8(0x3080), 0x02 },
253 { CCI_REG8(0x3081), 0x00 },
254 { CCI_REG8(0x3082), 0x00 },
255 { CCI_REG8(0x3083), 0x00 },
256 { CCI_REG8(0x3088), 0x02 },
257 { CCI_REG8(0x3094), 0x00 },
258 { CCI_REG8(0x3095), 0x00 },
259 { CCI_REG8(0x3096), 0x00 },
260 { CCI_REG8(0x309b), 0x02 },
261 { CCI_REG8(0x309c), 0x00 },
262 { CCI_REG8(0x309d), 0x00 },
263 { CCI_REG8(0x309e), 0x00 },
264 { CCI_REG8(0x30a4), 0x00 },
265 { CCI_REG8(0x30a5), 0x00 },
266 { CCI_REG8(0x3288), 0x21 },
267 { CCI_REG8(0x328a), 0x02 },
268 { CCI_REG8(0x3414), 0x05 },
269 { CCI_REG8(0x3416), 0x18 },
270 { CCI_REG8(0x35Ac), 0x0e },
271 { CCI_REG8(0x3648), 0x01 },
272 { CCI_REG8(0x364a), 0x04 },
273 { CCI_REG8(0x364c), 0x04 },
274 { CCI_REG8(0x3678), 0x01 },
275 { CCI_REG8(0x367c), 0x31 },
276 { CCI_REG8(0x367e), 0x31 },
277 { CCI_REG8(0x3708), 0x02 },
278 { CCI_REG8(0x3714), 0x01 },
279 { CCI_REG8(0x3715), 0x02 },
280 { CCI_REG8(0x3716), 0x02 },
281 { CCI_REG8(0x3717), 0x02 },
282 { CCI_REG8(0x371c), 0x3d },
283 { CCI_REG8(0x371d), 0x3f },
284 { CCI_REG8(0x372c), 0x00 },
285 { CCI_REG8(0x372d), 0x00 },
286 { CCI_REG8(0x372e), 0x46 },
287 { CCI_REG8(0x372f), 0x00 },
288 { CCI_REG8(0x3730), 0x89 },
289 { CCI_REG8(0x3731), 0x00 },
290 { CCI_REG8(0x3732), 0x08 },
291 { CCI_REG8(0x3733), 0x01 },
292 { CCI_REG8(0x3734), 0xfe },
293 { CCI_REG8(0x3735), 0x05 },
294 { CCI_REG8(0x375d), 0x00 },
295 { CCI_REG8(0x375e), 0x00 },
296 { CCI_REG8(0x375f), 0x61 },
297 { CCI_REG8(0x3760), 0x06 },
298 { CCI_REG8(0x3768), 0x1b },
299 { CCI_REG8(0x3769), 0x1b },
300 { CCI_REG8(0x376a), 0x1a },
301 { CCI_REG8(0x376b), 0x19 },
302 { CCI_REG8(0x376c), 0x18 },
303 { CCI_REG8(0x376d), 0x14 },
304 { CCI_REG8(0x376e), 0x0f },
305 { CCI_REG8(0x3776), 0x00 },
306 { CCI_REG8(0x3777), 0x00 },
307 { CCI_REG8(0x3778), 0x46 },
308 { CCI_REG8(0x3779), 0x00 },
309 { CCI_REG8(0x377a), 0x08 },
310 { CCI_REG8(0x377b), 0x01 },
311 { CCI_REG8(0x377c), 0x45 },
312 { CCI_REG8(0x377d), 0x01 },
313 { CCI_REG8(0x377e), 0x23 },
314 { CCI_REG8(0x377f), 0x02 },
315 { CCI_REG8(0x3780), 0xd9 },
316 { CCI_REG8(0x3781), 0x03 },
317 { CCI_REG8(0x3782), 0xf5 },
318 { CCI_REG8(0x3783), 0x06 },
319 { CCI_REG8(0x3784), 0xa5 },
320 { CCI_REG8(0x3788), 0x0f },
321 { CCI_REG8(0x378a), 0xd9 },
322 { CCI_REG8(0x378b), 0x03 },
323 { CCI_REG8(0x378c), 0xeb },
324 { CCI_REG8(0x378d), 0x05 },
325 { CCI_REG8(0x378e), 0x87 },
326 { CCI_REG8(0x378f), 0x06 },
327 { CCI_REG8(0x3790), 0xf5 },
328 { CCI_REG8(0x3792), 0x43 },
329 { CCI_REG8(0x3794), 0x7a },
330 { CCI_REG8(0x3796), 0xa1 },
331 { CCI_REG8(0x37b0), 0x37 },
332 { CCI_REG8(0x3e04), 0x0e },
333 { IMX334_REG_AGAIN, 0x0050 },
334 { IMX334_REG_MASTER_MODE, 0x00 },
339 { IMX334_REG_HTRIMMING_START, 0x0670 },
340 { IMX334_REG_HNUM, 0x0280 },
341 { IMX334_REG_AREA3_ST_ADR_1, 0x0748 },
342 { IMX334_REG_AREA3_ST_ADR_2, 0x0749 },
343 { IMX334_REG_AREA3_WIDTH_1, 0x01e0 },
344 { IMX334_REG_AREA3_WIDTH_2, 0x01e0 },
345 { IMX334_REG_Y_OUT_SIZE, 0x01e0 },
346 { IMX334_REG_UNREAD_ED_ADR, 0x0b30 },
351 { IMX334_REG_HTRIMMING_START, 0x0530 },
352 { IMX334_REG_HNUM, 0x0500 },
353 { IMX334_REG_AREA3_ST_ADR_1, 0x0384 },
354 { IMX334_REG_AREA3_ST_ADR_2, 0x0385 },
355 { IMX334_REG_AREA3_WIDTH_1, 0x02d0 },
356 { IMX334_REG_AREA3_WIDTH_2, 0x02d0 },
357 { IMX334_REG_Y_OUT_SIZE, 0x02d0 },
358 { IMX334_REG_UNREAD_ED_ADR, 0x0b30 },
363 { IMX334_REG_HTRIMMING_START, 0x03f0 },
364 { IMX334_REG_HNUM, 0x0780 },
365 { IMX334_REG_AREA3_ST_ADR_1, 0x02cc },
366 { IMX334_REG_AREA3_ST_ADR_2, 0x02cd },
367 { IMX334_REG_AREA3_WIDTH_1, 0x0438 },
368 { IMX334_REG_AREA3_WIDTH_2, 0x0438 },
369 { IMX334_REG_Y_OUT_SIZE, 0x0438 },
370 { IMX334_REG_UNREAD_ED_ADR, 0x0a18 },
375 { IMX334_REG_HMAX, 0x0226 },
376 { IMX334_REG_INCKSEL2, 0x02 },
377 { IMX334_REG_HTRIMMING_START, 0x003c },
378 { IMX334_REG_HNUM, 0x0f00 },
379 { IMX334_REG_AREA3_ST_ADR_1, 0x00b0 },
380 { IMX334_REG_AREA3_ST_ADR_2, 0x00b1 },
381 { IMX334_REG_UNREAD_ED_ADR, 0x1220 },
382 { IMX334_REG_AREA3_WIDTH_1, 0x0870 },
383 { IMX334_REG_AREA3_WIDTH_2, 0x0870 },
384 { IMX334_REG_Y_OUT_SIZE, 0x0870 },
385 { IMX334_REG_SYS_MODE, 0x0100 },
386 { IMX334_REG_TCLKPOST, 0x00bf },
387 { IMX334_REG_TCLKPREPARE, 0x0067 },
388 { IMX334_REG_TCLKTRAIL, 0x006f },
389 { IMX334_REG_TCLKZERO, 0x1d7 },
390 { IMX334_REG_THSPREPARE, 0x006f },
391 { IMX334_REG_THSZERO, 0x00cf },
392 { IMX334_REG_THSTRAIL, 0x006f },
393 { IMX334_REG_THSEXIT, 0x00b7 },
394 { IMX334_REG_TPLX, 0x005f },
410 { IMX334_REG_ADBIT, 0x00 },
411 { IMX334_REG_MDBIT, 0x00 },
412 { IMX334_REG_ADBIT1, 0x01ff },
416 { IMX334_REG_ADBIT, 0x01 },
417 { IMX334_REG_MDBIT, 0x01 },
418 { IMX334_REG_ADBIT1, 0x0047 },
436 .link_freq_idx = 0,
499 * Return: 0 if successful, error code otherwise.
534 * Return: 0 if successful, error code otherwise.
540 int ret = 0;
553 ret_hold = cci_write(imx334->cci, IMX334_REG_HOLD, 0, NULL);
570 * Return: 0 if successful, error code otherwise.
599 return 0;
623 ret = 0;
629 cci_write(imx334->cci, IMX334_DIG_CLP_MODE, 0x0, NULL);
637 cci_write(imx334->cci, IMX334_DIG_CLP_MODE, 0x1, NULL);
643 ret = 0;
664 for (i = 0; i < ARRAY_SIZE(imx334_mbus_codes); i++) {
669 return imx334_mbus_codes[0];
678 * Return: 0 if successful, error code otherwise.
689 return 0;
698 * Return: 0 if successful, error code otherwise.
720 return 0;
749 * Return: 0 if successful, error code otherwise.
767 return 0;
776 * Return: 0 if successful, error code otherwise.
784 int ret = 0;
814 * Return: 0 if successful, error code otherwise.
820 struct v4l2_subdev_format fmt = { 0 };
826 __v4l2_ctrl_modify_range(imx334->link_freq_ctrl, 0,
857 * Return: 0 if successful, error code otherwise.
868 if (ret < 0)
916 return 0;
930 * Return: 0 if successful, error code otherwise.
953 * Return: 0 if successful, -EIO if sensor id does not match
970 return 0;
977 * Return: 0 if successful, error code otherwise.
1065 * Return: 0 if successful, error code otherwise.
1083 return 0;
1086 gpiod_set_value_cansleep(imx334->reset_gpio, 0);
1095 * Return: 0 if successful, error code otherwise.
1102 gpiod_set_value_cansleep(imx334->reset_gpio, 0);
1106 return 0;
1113 * Return: 0 if successful, error code otherwise.
1182 0, 0, imx334_test_pattern_menu);
1193 return 0;
1200 * Return: 0 if successful, error code otherwise.
1242 imx334->cur_code = imx334_mbus_codes[0];
1265 if (ret < 0) {
1274 if (ret < 0) {
1282 return 0;
1305 * Return: 0 if successful, error code otherwise.