30 #define GC08A3_REG_TEST_PATTERN_EN CCI_REG8(0x008c)
31 #define GC08A3_REG_TEST_PATTERN_IDX CCI_REG8(0x008d)
32 #define GC08A3_TEST_PATTERN_EN 0x01
34 #define GC08A3_STREAMING_REG CCI_REG8(0x0100)
36 #define GC08A3_FLIP_REG CCI_REG8(0x0101)
37 #define GC08A3_FLIP_H_MASK BIT(0)
40 #define GC08A3_EXP_REG CCI_REG16(0x0202)
45 #define GC08A3_AGAIN_REG CCI_REG16(0x0204)
50 #define GC08A3_FRAME_LENGTH_REG CCI_REG16(0x0340)
51 #define GC08A3_VTS_MAX 0xfff0
53 #define GC08A3_REG_CHIP_ID CCI_REG16(0x03f0)
54 #define GC08A3_CHIP_ID 0x08a3
113 	{ CCI_REG8(0x0336), 0x70 },
114 	{ CCI_REG8(0x0383), 0xbb },
115 	{ CCI_REG8(0x0344), 0x00 },
116 	{ CCI_REG8(0x0345), 0x06 },
117 	{ CCI_REG8(0x0346), 0x00 },
118 	{ CCI_REG8(0x0347), 0x04 },
119 	{ CCI_REG8(0x0348), 0x0c },
120 	{ CCI_REG8(0x0349), 0xd0 },
121 	{ CCI_REG8(0x034a), 0x09 },
122 	{ CCI_REG8(0x034b), 0x9c },
123 	{ CCI_REG8(0x0202), 0x09 },
124 	{ CCI_REG8(0x0203), 0x04 },
125 	{ CCI_REG8(0x0340), 0x09 },
126 	{ CCI_REG8(0x0341), 0xf4 },
127 	{ CCI_REG8(0x0342), 0x07 },
128 	{ CCI_REG8(0x0343), 0x1c },
130 	{ CCI_REG8(0x0226), 0x00 },
131 	{ CCI_REG8(0x0227), 0x28 },
132 	{ CCI_REG8(0x0e38), 0x49 },
133 	{ CCI_REG8(0x0210), 0x13 },
134 	{ CCI_REG8(0x0218), 0x00 },
135 	{ CCI_REG8(0x0241), 0x88 },
136 	{ CCI_REG8(0x0392), 0x60 },
139 	{ CCI_REG8(0x00a2), 0x00 },
140 	{ CCI_REG8(0x00a3), 0x00 },
141 	{ CCI_REG8(0x00ab), 0x00 },
142 	{ CCI_REG8(0x00ac), 0x00 },
145 	{ CCI_REG8(0x0204), 0x04 },
146 	{ CCI_REG8(0x0205), 0x00 },
147 	{ CCI_REG8(0x0050), 0x5c },
148 	{ CCI_REG8(0x0051), 0x44 },
151 	{ CCI_REG8(0x009a), 0x66 },
152 	{ CCI_REG8(0x0351), 0x00 },
153 	{ CCI_REG8(0x0352), 0x06 },
154 	{ CCI_REG8(0x0353), 0x00 },
155 	{ CCI_REG8(0x0354), 0x08 },
156 	{ CCI_REG8(0x034c), 0x0c },
157 	{ CCI_REG8(0x034d), 0xc0 },
158 	{ CCI_REG8(0x034e), 0x09 },
159 	{ CCI_REG8(0x034f), 0x90 },
162 	{ CCI_REG8(0x0114), 0x03 },
163 	{ CCI_REG8(0x0180), 0x65 },
164 	{ CCI_REG8(0x0181), 0xf0 },
165 	{ CCI_REG8(0x0185), 0x01 },
166 	{ CCI_REG8(0x0115), 0x30 },
167 	{ CCI_REG8(0x011b), 0x12 },
168 	{ CCI_REG8(0x011c), 0x12 },
169 	{ CCI_REG8(0x0121), 0x06 },
170 	{ CCI_REG8(0x0122), 0x06 },
171 	{ CCI_REG8(0x0123), 0x15 },
172 	{ CCI_REG8(0x0124), 0x01 },
173 	{ CCI_REG8(0x0125), 0x0b },
174 	{ CCI_REG8(0x0126), 0x08 },
175 	{ CCI_REG8(0x0129), 0x06 },
176 	{ CCI_REG8(0x012a), 0x08 },
177 	{ CCI_REG8(0x012b), 0x08 },
179 	{ CCI_REG8(0x0a73), 0x60 },
180 	{ CCI_REG8(0x0a70), 0x11 },
181 	{ CCI_REG8(0x0313), 0x80 },
182 	{ CCI_REG8(0x0aff), 0x00 },
183 	{ CCI_REG8(0x0a70), 0x00 },
184 	{ CCI_REG8(0x00a4), 0x80 },
185 	{ CCI_REG8(0x0316), 0x01 },
186 	{ CCI_REG8(0x0a67), 0x00 },
187 	{ CCI_REG8(0x0084), 0x10 },
188 	{ CCI_REG8(0x0102), 0x09 },
193 	{ CCI_REG8(0x0336), 0x45 },
194 	{ CCI_REG8(0x0383), 0x8b },
195 	{ CCI_REG8(0x0344), 0x02 },
196 	{ CCI_REG8(0x0345), 0xa6 },
197 	{ CCI_REG8(0x0346), 0x02 },
198 	{ CCI_REG8(0x0347), 0xb0 },
199 	{ CCI_REG8(0x0348), 0x07 },
200 	{ CCI_REG8(0x0349), 0x90 },
201 	{ CCI_REG8(0x034a), 0x04 },
202 	{ CCI_REG8(0x034b), 0x44 },
203 	{ CCI_REG8(0x0202), 0x03 },
204 	{ CCI_REG8(0x0203), 0x00 },
205 	{ CCI_REG8(0x0340), 0x04 },
206 	{ CCI_REG8(0x0341), 0xfc },
207 	{ CCI_REG8(0x0342), 0x07 },
208 	{ CCI_REG8(0x0343), 0x1c },
209 	{ CCI_REG8(0x0226), 0x00 },
210 	{ CCI_REG8(0x0227), 0x88 },
211 	{ CCI_REG8(0x0e38), 0x49 },
212 	{ CCI_REG8(0x0210), 0x13 },
213 	{ CCI_REG8(0x0218), 0x00 },
214 	{ CCI_REG8(0x0241), 0x88 },
215 	{ CCI_REG8(0x0392), 0x60 },
218 	{ CCI_REG8(0x00a2), 0xac },
219 	{ CCI_REG8(0x00a3), 0x02 },
220 	{ CCI_REG8(0x00ab), 0xa0 },
221 	{ CCI_REG8(0x00ac), 0x02 },
224 	{ CCI_REG8(0x0204), 0x04 },
225 	{ CCI_REG8(0x0205), 0x00 },
226 	{ CCI_REG8(0x0050), 0x38 },
227 	{ CCI_REG8(0x0051), 0x20 },
230 	{ CCI_REG8(0x009a), 0x66 },
231 	{ CCI_REG8(0x0351), 0x00 },
232 	{ CCI_REG8(0x0352), 0x06 },
233 	{ CCI_REG8(0x0353), 0x00 },
234 	{ CCI_REG8(0x0354), 0x08 },
235 	{ CCI_REG8(0x034c), 0x07 },
236 	{ CCI_REG8(0x034d), 0x80 },
237 	{ CCI_REG8(0x034e), 0x04 },
238 	{ CCI_REG8(0x034f), 0x38 },
241 	{ CCI_REG8(0x0114), 0x03 },
242 	{ CCI_REG8(0x0180), 0x65 },
243 	{ CCI_REG8(0x0181), 0xf0 },
244 	{ CCI_REG8(0x0185), 0x01 },
245 	{ CCI_REG8(0x0115), 0x30 },
246 	{ CCI_REG8(0x011b), 0x12 },
247 	{ CCI_REG8(0x011c), 0x12 },
248 	{ CCI_REG8(0x0121), 0x02 },
249 	{ CCI_REG8(0x0122), 0x03 },
250 	{ CCI_REG8(0x0123), 0x0c },
251 	{ CCI_REG8(0x0124), 0x00 },
252 	{ CCI_REG8(0x0125), 0x09 },
253 	{ CCI_REG8(0x0126), 0x06 },
254 	{ CCI_REG8(0x0129), 0x04 },
255 	{ CCI_REG8(0x012a), 0x03 },
256 	{ CCI_REG8(0x012b), 0x06 },
258 	{ CCI_REG8(0x0a73), 0x60 },
259 	{ CCI_REG8(0x0a70), 0x11 },
260 	{ CCI_REG8(0x0313), 0x80 },
261 	{ CCI_REG8(0x0aff), 0x00 },
262 	{ CCI_REG8(0x0a70), 0x00 },
263 	{ CCI_REG8(0x00a4), 0x80 },
264 	{ CCI_REG8(0x0316), 0x01 },
265 	{ CCI_REG8(0x0a67), 0x00 },
266 	{ CCI_REG8(0x0084), 0x10 },
267 	{ CCI_REG8(0x0102), 0x09 },
271 	{ GC08A3_STREAMING_REG, 0x00 },
273 	{ CCI_REG8(0x031c), 0x60 },
274 	{ CCI_REG8(0x0337), 0x04 },
275 	{ CCI_REG8(0x0335), 0x51 },
276 	{ CCI_REG8(0x0336), 0x70 },
277 	{ CCI_REG8(0x0383), 0xbb },
278 	{ CCI_REG8(0x031a), 0x00 },
279 	{ CCI_REG8(0x0321), 0x10 },
280 	{ CCI_REG8(0x0327), 0x03 },
281 	{ CCI_REG8(0x0325), 0x40 },
282 	{ CCI_REG8(0x0326), 0x23 },
283 	{ CCI_REG8(0x0314), 0x11 },
284 	{ CCI_REG8(0x0315), 0xd6 },
285 	{ CCI_REG8(0x0316), 0x01 },
286 	{ CCI_REG8(0x0334), 0x40 },
287 	{ CCI_REG8(0x0324), 0x42 },
288 	{ CCI_REG8(0x031c), 0x00 },
289 	{ CCI_REG8(0x031c), 0x9f },
290 	{ CCI_REG8(0x039a), 0x13 },
291 	{ CCI_REG8(0x0084), 0x30 },
292 	{ CCI_REG8(0x02b3), 0x08 },
293 	{ CCI_REG8(0x0057), 0x0c },
294 	{ CCI_REG8(0x05c3), 0x50 },
295 	{ CCI_REG8(0x0311), 0x90 },
296 	{ CCI_REG8(0x05a0), 0x02 },
297 	{ CCI_REG8(0x0074), 0x0a },
298 	{ CCI_REG8(0x0059), 0x11 },
299 	{ CCI_REG8(0x0070), 0x05 },
300 	{ CCI_REG8(0x0101), 0x00 },
303 	{ CCI_REG8(0x0344), 0x00 },
304 	{ CCI_REG8(0x0345), 0x06 },
305 	{ CCI_REG8(0x0346), 0x00 },
306 	{ CCI_REG8(0x0347), 0x04 },
307 	{ CCI_REG8(0x0348), 0x0c },
308 	{ CCI_REG8(0x0349), 0xd0 },
309 	{ CCI_REG8(0x034a), 0x09 },
310 	{ CCI_REG8(0x034b), 0x9c },
311 	{ CCI_REG8(0x0202), 0x09 },
312 	{ CCI_REG8(0x0203), 0x04 },
314 	{ CCI_REG8(0x0219), 0x05 },
315 	{ CCI_REG8(0x0226), 0x00 },
316 	{ CCI_REG8(0x0227), 0x28 },
317 	{ CCI_REG8(0x0e0a), 0x00 },
318 	{ CCI_REG8(0x0e0b), 0x00 },
319 	{ CCI_REG8(0x0e24), 0x04 },
320 	{ CCI_REG8(0x0e25), 0x04 },
321 	{ CCI_REG8(0x0e26), 0x00 },
322 	{ CCI_REG8(0x0e27), 0x10 },
323 	{ CCI_REG8(0x0e01), 0x74 },
324 	{ CCI_REG8(0x0e03), 0x47 },
325 	{ CCI_REG8(0x0e04), 0x33 },
326 	{ CCI_REG8(0x0e05), 0x44 },
327 	{ CCI_REG8(0x0e06), 0x44 },
328 	{ CCI_REG8(0x0e0c), 0x1e },
329 	{ CCI_REG8(0x0e17), 0x3a },
330 	{ CCI_REG8(0x0e18), 0x3c },
331 	{ CCI_REG8(0x0e19), 0x40 },
332 	{ CCI_REG8(0x0e1a), 0x42 },
333 	{ CCI_REG8(0x0e28), 0x21 },
334 	{ CCI_REG8(0x0e2b), 0x68 },
335 	{ CCI_REG8(0x0e2c), 0x0d },
336 	{ CCI_REG8(0x0e2d), 0x08 },
337 	{ CCI_REG8(0x0e34), 0xf4 },
338 	{ CCI_REG8(0x0e35), 0x44 },
339 	{ CCI_REG8(0x0e36), 0x07 },
340 	{ CCI_REG8(0x0e38), 0x49 },
341 	{ CCI_REG8(0x0210), 0x13 },
342 	{ CCI_REG8(0x0218), 0x00 },
343 	{ CCI_REG8(0x0241), 0x88 },
344 	{ CCI_REG8(0x0e32), 0x00 },
345 	{ CCI_REG8(0x0e33), 0x18 },
346 	{ CCI_REG8(0x0e42), 0x03 },
347 	{ CCI_REG8(0x0e43), 0x80 },
348 	{ CCI_REG8(0x0e44), 0x04 },
349 	{ CCI_REG8(0x0e45), 0x00 },
350 	{ CCI_REG8(0x0e4f), 0x04 },
351 	{ CCI_REG8(0x057a), 0x20 },
352 	{ CCI_REG8(0x0381), 0x7c },
353 	{ CCI_REG8(0x0382), 0x9b },
354 	{ CCI_REG8(0x0384), 0xfb },
355 	{ CCI_REG8(0x0389), 0x38 },
356 	{ CCI_REG8(0x038a), 0x03 },
357 	{ CCI_REG8(0x0390), 0x6a },
358 	{ CCI_REG8(0x0391), 0x0b },
359 	{ CCI_REG8(0x0392), 0x60 },
360 	{ CCI_REG8(0x0393), 0xc1 },
361 	{ CCI_REG8(0x0396), 0xff },
362 	{ CCI_REG8(0x0398), 0x62 },
365 	{ CCI_REG8(0x031c), 0x80 },
366 	{ CCI_REG8(0x03fe), 0x10 },
367 	{ CCI_REG8(0x03fe), 0x00 },
368 	{ CCI_REG8(0x031c), 0x9f },
369 	{ CCI_REG8(0x03fe), 0x00 },
370 	{ CCI_REG8(0x03fe), 0x00 },
371 	{ CCI_REG8(0x03fe), 0x00 },
372 	{ CCI_REG8(0x03fe), 0x00 },
373 	{ CCI_REG8(0x031c), 0x80 },
374 	{ CCI_REG8(0x03fe), 0x10 },
375 	{ CCI_REG8(0x03fe), 0x00 },
376 	{ CCI_REG8(0x031c), 0x9f },
377 	{ CCI_REG8(0x0360), 0x01 },
378 	{ CCI_REG8(0x0360), 0x00 },
379 	{ CCI_REG8(0x0316), 0x09 },
380 	{ CCI_REG8(0x0a67), 0x80 },
381 	{ CCI_REG8(0x0313), 0x00 },
382 	{ CCI_REG8(0x0a53), 0x0e },
383 	{ CCI_REG8(0x0a65), 0x17 },
384 	{ CCI_REG8(0x0a68), 0xa1 },
385 	{ CCI_REG8(0x0a58), 0x00 },
386 	{ CCI_REG8(0x0ace), 0x0c },
387 	{ CCI_REG8(0x00a4), 0x00 },
388 	{ CCI_REG8(0x00a5), 0x01 },
389 	{ CCI_REG8(0x00a7), 0x09 },
390 	{ CCI_REG8(0x00a8), 0x9c },
391 	{ CCI_REG8(0x00a9), 0x0c },
392 	{ CCI_REG8(0x00aa), 0xd0 },
393 	{ CCI_REG8(0x0a8a), 0x00 },
394 	{ CCI_REG8(0x0a8b), 0xe0 },
395 	{ CCI_REG8(0x0a8c), 0x13 },
396 	{ CCI_REG8(0x0a8d), 0xe8 },
397 	{ CCI_REG8(0x0a90), 0x0a },
398 	{ CCI_REG8(0x0a91), 0x10 },
399 	{ CCI_REG8(0x0a92), 0xf8 },
400 	{ CCI_REG8(0x0a71), 0xf2 },
401 	{ CCI_REG8(0x0a72), 0x12 },
402 	{ CCI_REG8(0x0a73), 0x64 },
403 	{ CCI_REG8(0x0a75), 0x41 },
404 	{ CCI_REG8(0x0a70), 0x07 },
405 	{ CCI_REG8(0x0313), 0x80 },
408 	{ CCI_REG8(0x00a0), 0x01 },
409 	{ CCI_REG8(0x0080), 0xd2 },
410 	{ CCI_REG8(0x0081), 0x3f },
411 	{ CCI_REG8(0x0087), 0x51 },
412 	{ CCI_REG8(0x0089), 0x03 },
413 	{ CCI_REG8(0x009b), 0x40 },
414 	{ CCI_REG8(0x05a0), 0x82 },
415 	{ CCI_REG8(0x05ac), 0x00 },
416 	{ CCI_REG8(0x05ad), 0x01 },
417 	{ CCI_REG8(0x05ae), 0x00 },
418 	{ CCI_REG8(0x0800), 0x0a },
419 	{ CCI_REG8(0x0801), 0x14 },
420 	{ CCI_REG8(0x0802), 0x28 },
421 	{ CCI_REG8(0x0803), 0x34 },
422 	{ CCI_REG8(0x0804), 0x0e },
423 	{ CCI_REG8(0x0805), 0x33 },
424 	{ CCI_REG8(0x0806), 0x03 },
425 	{ CCI_REG8(0x0807), 0x8a },
426 	{ CCI_REG8(0x0808), 0x50 },
427 	{ CCI_REG8(0x0809), 0x00 },
428 	{ CCI_REG8(0x080a), 0x34 },
429 	{ CCI_REG8(0x080b), 0x03 },
430 	{ CCI_REG8(0x080c), 0x26 },
431 	{ CCI_REG8(0x080d), 0x03 },
432 	{ CCI_REG8(0x080e), 0x18 },
433 	{ CCI_REG8(0x080f), 0x03 },
434 	{ CCI_REG8(0x0810), 0x10 },
435 	{ CCI_REG8(0x0811), 0x03 },
436 	{ CCI_REG8(0x0812), 0x00 },
437 	{ CCI_REG8(0x0813), 0x00 },
438 	{ CCI_REG8(0x0814), 0x01 },
439 	{ CCI_REG8(0x0815), 0x00 },
440 	{ CCI_REG8(0x0816), 0x01 },
441 	{ CCI_REG8(0x0817), 0x00 },
442 	{ CCI_REG8(0x0818), 0x00 },
443 	{ CCI_REG8(0x0819), 0x0a },
444 	{ CCI_REG8(0x081a), 0x01 },
445 	{ CCI_REG8(0x081b), 0x6c },
446 	{ CCI_REG8(0x081c), 0x00 },
447 	{ CCI_REG8(0x081d), 0x0b },
448 	{ CCI_REG8(0x081e), 0x02 },
449 	{ CCI_REG8(0x081f), 0x00 },
450 	{ CCI_REG8(0x0820), 0x00 },
451 	{ CCI_REG8(0x0821), 0x0c },
452 	{ CCI_REG8(0x0822), 0x02 },
453 	{ CCI_REG8(0x0823), 0xd9 },
454 	{ CCI_REG8(0x0824), 0x00 },
455 	{ CCI_REG8(0x0825), 0x0d },
456 	{ CCI_REG8(0x0826), 0x03 },
457 	{ CCI_REG8(0x0827), 0xf0 },
458 	{ CCI_REG8(0x0828), 0x00 },
459 	{ CCI_REG8(0x0829), 0x0e },
460 	{ CCI_REG8(0x082a), 0x05 },
461 	{ CCI_REG8(0x082b), 0x94 },
462 	{ CCI_REG8(0x082c), 0x09 },
463 	{ CCI_REG8(0x082d), 0x6e },
464 	{ CCI_REG8(0x082e), 0x07 },
465 	{ CCI_REG8(0x082f), 0xe6 },
466 	{ CCI_REG8(0x0830), 0x10 },
467 	{ CCI_REG8(0x0831), 0x0e },
468 	{ CCI_REG8(0x0832), 0x0b },
469 	{ CCI_REG8(0x0833), 0x2c },
470 	{ CCI_REG8(0x0834), 0x14 },
471 	{ CCI_REG8(0x0835), 0xae },
472 	{ CCI_REG8(0x0836), 0x0f },
473 	{ CCI_REG8(0x0837), 0xc4 },
474 	{ CCI_REG8(0x0838), 0x18 },
475 	{ CCI_REG8(0x0839), 0x0e },
476 	{ CCI_REG8(0x05ac), 0x01 },
477 	{ CCI_REG8(0x059a), 0x00 },
478 	{ CCI_REG8(0x059b), 0x00 },
479 	{ CCI_REG8(0x059c), 0x01 },
480 	{ CCI_REG8(0x0598), 0x00 },
481 	{ CCI_REG8(0x0597), 0x14 },
482 	{ CCI_REG8(0x05ab), 0x09 },
483 	{ CCI_REG8(0x05a4), 0x02 },
484 	{ CCI_REG8(0x05a3), 0x05 },
485 	{ CCI_REG8(0x05a0), 0xc2 },
486 	{ CCI_REG8(0x0207), 0xc4 },
489 	{ CCI_REG8(0x0208), 0x01 },
490 	{ CCI_REG8(0x0209), 0x72 },
491 	{ CCI_REG8(0x0204), 0x04 },
492 	{ CCI_REG8(0x0205), 0x00 },
494 	{ CCI_REG8(0x0040), 0x22 },
495 	{ CCI_REG8(0x0041), 0x20 },
496 	{ CCI_REG8(0x0043), 0x10 },
497 	{ CCI_REG8(0x0044), 0x00 },
498 	{ CCI_REG8(0x0046), 0x08 },
499 	{ CCI_REG8(0x0047), 0xf0 },
500 	{ CCI_REG8(0x0048), 0x0f },
501 	{ CCI_REG8(0x004b), 0x0f },
502 	{ CCI_REG8(0x004c), 0x00 },
503 	{ CCI_REG8(0x0050), 0x5c },
504 	{ CCI_REG8(0x0051), 0x44 },
505 	{ CCI_REG8(0x005b), 0x03 },
506 	{ CCI_REG8(0x00c0), 0x00 },
507 	{ CCI_REG8(0x00c1), 0x80 },
508 	{ CCI_REG8(0x00c2), 0x31 },
509 	{ CCI_REG8(0x00c3), 0x00 },
510 	{ CCI_REG8(0x0460), 0x04 },
511 	{ CCI_REG8(0x0462), 0x08 },
512 	{ CCI_REG8(0x0464), 0x0e },
513 	{ CCI_REG8(0x0466), 0x0a },
514 	{ CCI_REG8(0x0468), 0x12 },
515 	{ CCI_REG8(0x046a), 0x12 },
516 	{ CCI_REG8(0x046c), 0x10 },
517 	{ CCI_REG8(0x046e), 0x0c },
518 	{ CCI_REG8(0x0461), 0x03 },
519 	{ CCI_REG8(0x0463), 0x03 },
520 	{ CCI_REG8(0x0465), 0x03 },
521 	{ CCI_REG8(0x0467), 0x03 },
522 	{ CCI_REG8(0x0469), 0x04 },
523 	{ CCI_REG8(0x046b), 0x04 },
524 	{ CCI_REG8(0x046d), 0x04 },
525 	{ CCI_REG8(0x046f), 0x04 },
526 	{ CCI_REG8(0x0470), 0x04 },
527 	{ CCI_REG8(0x0472), 0x10 },
528 	{ CCI_REG8(0x0474), 0x26 },
529 	{ CCI_REG8(0x0476), 0x38 },
530 	{ CCI_REG8(0x0478), 0x20 },
531 	{ CCI_REG8(0x047a), 0x30 },
532 	{ CCI_REG8(0x047c), 0x38 },
533 	{ CCI_REG8(0x047e), 0x60 },
534 	{ CCI_REG8(0x0471), 0x05 },
535 	{ CCI_REG8(0x0473), 0x05 },
536 	{ CCI_REG8(0x0475), 0x05 },
537 	{ CCI_REG8(0x0477), 0x05 },
538 	{ CCI_REG8(0x0479), 0x04 },
539 	{ CCI_REG8(0x047b), 0x04 },
540 	{ CCI_REG8(0x047d), 0x04 },
541 	{ CCI_REG8(0x047f), 0x04 },
595 	if (ret < 0) {  in gc08a3_power_on()
601 	if (ret < 0) {  in gc08a3_power_on()
610 	gpiod_set_value_cansleep(gc08a3->reset_gpio, 0);  in gc08a3_power_on()
613 	return 0;  in gc08a3_power_on()
626 	return 0;  in gc08a3_power_off()
633 	if (code->index > 0)  in gc08a3_enum_mbus_code()
638 	return 0;  in gc08a3_enum_mbus_code()
656 	return 0;  in gc08a3_enum_frame_size()
691 	return 0;  in gc08a3_update_cur_mode_controls()
722 	crop = v4l2_subdev_state_get_crop(state, 0);  in gc08a3_set_format()
728 	mbus_fmt = v4l2_subdev_state_get_format(state, 0);  in gc08a3_set_format()
732 		return 0;  in gc08a3_set_format()
737 	return 0;  in gc08a3_set_format()
747 		sel->r = *v4l2_subdev_state_get_crop(state, 0);  in gc08a3_get_selection()
750 		sel->r.top = 0;  in gc08a3_get_selection()
751 		sel->r.left = 0;  in gc08a3_get_selection()
759 	return 0;  in gc08a3_get_selection()
767 		.pad = 0,  in gc08a3_init_state()
770 			.width = gc08a3_modes[0].width,  in gc08a3_init_state()
771 			.height = gc08a3_modes[0].height,  in gc08a3_init_state()
777 	return 0;  in gc08a3_init_state()
793 			       ctrl_val ? GC08A3_FLIP_H_MASK : 0, NULL);  in gc08a3_set_ctrl_hflip()
809 			       ctrl_val ? GC08A3_FLIP_V_MASK : 0, NULL);  in gc08a3_set_ctrl_vflip()
820 			pattern = 0x00;  in gc08a3_test_pattern()
823 			pattern = 0x10;  in gc08a3_test_pattern()
833 			pattern = 0x00;  in gc08a3_test_pattern()
846 				 0x00, NULL);  in gc08a3_test_pattern()
854 	int ret = 0;  in gc08a3_set_ctrl()
860 	format = v4l2_subdev_state_get_format(state, 0);  in gc08a3_set_ctrl()
876 		return 0;  in gc08a3_set_ctrl()
926 	if (ret < 0)  in gc08a3_start_streaming()
939 	if (ret < 0)  in gc08a3_start_streaming()
943 	if (ret < 0) {  in gc08a3_start_streaming()
949 	if (ret < 0) {  in gc08a3_start_streaming()
954 	return 0;  in gc08a3_start_streaming()
965 	ret = cci_write(gc08a3->regmap, GC08A3_STREAMING_REG, 0, NULL);  in gc08a3_stop_streaming()
966 	if (ret < 0)  in gc08a3_stop_streaming()
1016 	for (i = 0; i < ARRAY_SIZE(gc08a3_supply_name); i++)  in gc08a3_get_regulators()
1033 		fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0,  in gc08a3_parse_fwnode()
1071 	const struct gc08a3_mode *mode = &gc08a3_modes[0];  in gc08a3_init_controls()
1084 					  V4L2_CID_HFLIP, 0, 1, 1, 0);  in gc08a3_init_controls()
1086 					  V4L2_CID_VFLIP, 0, 1, 1, 0);  in gc08a3_init_controls()
1094 			       0,  in gc08a3_init_controls()
1102 				  V4L2_CID_PIXEL_RATE, 0,  in gc08a3_init_controls()
1103 				  gc08a3_to_pixel_rate(0),  in gc08a3_init_controls()
1105 				  gc08a3_to_pixel_rate(0));  in gc08a3_init_controls()
1135 				     0, 0, gc08a3_test_pattern_menu);  in gc08a3_init_controls()
1153 	return 0;  in gc08a3_init_controls()
1173 		dev_err(gc08a3->dev, "chip id mismatch: 0x%x!=0x%llx",  in gc08a3_identify_module()
1178 	return 0;  in gc08a3_identify_module()
1213 	if (ret < 0)  in gc08a3_probe()
1224 	gc08a3->cur_mode = &gc08a3_modes[0];  in gc08a3_probe()
1249 	if (ret < 0) {  in gc08a3_probe()
1256 	if (ret < 0) {  in gc08a3_probe()
1268 	if (ret < 0) {  in gc08a3_probe()
1273 	return 0;  in gc08a3_probe()