Lines Matching refs:ub960_rxport_write
886 static int ub960_rxport_write(struct ub960_data *priv, u8 nport, u8 reg,
1293 ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ID(reg_idx),
1295 ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ALIAS(reg_idx),
1331 ret = ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ALIAS(reg_idx),
1651 ret = ub960_rxport_write(priv, nport, UB960_RR_AEQ_BYPASS, v, NULL);
1663 ub960_rxport_write(priv, nport, UB960_RR_AEQ_MIN_MAX,
2455 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_HI, 0x07, &ret);
2456 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_LO, 0x7f, &ret);
2464 ub960_rxport_write(priv, nport, UB960_RR_SER_ALIAS_ID,
2547 ub960_rxport_write(priv, nport, UB9702_RR_RX_CTL_2, 0x1b, &ret);
2554 ub960_rxport_write(priv, nport, UB9702_RR_RX_CTL_1, 0x15, &ret);
2622 ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x0, &ret);
2660 ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x1, &ret);
2699 ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x2, &ret);
2729 ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x5, &ret);
3072 ub960_rxport_write(priv, it.nport, UB960_RR_SER_ID,
3079 ub960_rxport_write(priv, it.nport, UB960_RR_SER_ALIAS_ID,
3098 ub960_rxport_write(priv, it.nport, UB9702_RR_RX_SM_SEL_2, 0x10,
3133 ret = ub960_rxport_write(priv, it.nport,
3174 ret = ub960_rxport_write(priv, it.nport,
3187 ret = ub960_rxport_write(priv, it.nport,
3226 ub960_rxport_write(priv, it.nport, UB960_RR_PORT_ICR_HI, 0x07,
3228 ub960_rxport_write(priv, it.nport, UB960_RR_PORT_ICR_LO, 0x7f,
3609 ub960_rxport_write(priv, nport, UB960_RR_RAW10_ID,
3613 ub960_rxport_write(priv, nport,
3629 ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP,
3640 ub960_rxport_write(priv, nport,