Lines Matching refs:nport
482 u8 nport; /* RX port number, and index in priv->rxport[] */
542 u8 nport; /* TX port number, and index in priv->txport[] */
664 unsigned int nport;
677 for (; it.nport < priv->hw_data->num_rxports; it.nport++) {
678 it.rxport = priv->rxports[it.nport];
699 it.nport < (priv)->hw_data->num_rxports; \
700 it.nport++, it = ub960_iter_rxport(priv, it, 0))
706 it.nport < (priv)->hw_data->num_rxports; \
707 it.nport++, it = ub960_iter_rxport(priv, it, \
715 it.nport < (priv)->hw_data->num_rxports; \
716 it.nport++, it = ub960_iter_rxport(priv, it, \
829 static int ub960_rxport_select(struct ub960_data *priv, u8 nport)
836 if (priv->reg_current.rxport == nport)
840 (nport << 4) | BIT(nport));
843 nport, ret);
847 priv->reg_current.rxport = nport;
852 static int ub960_rxport_read(struct ub960_data *priv, u8 nport, u8 reg,
864 ret = ub960_rxport_select(priv, nport);
886 static int ub960_rxport_write(struct ub960_data *priv, u8 nport, u8 reg,
897 ret = ub960_rxport_select(priv, nport);
915 static int ub960_rxport_update_bits(struct ub960_data *priv, u8 nport, u8 reg,
926 ret = ub960_rxport_select(priv, nport);
944 static int ub960_rxport_read16(struct ub960_data *priv, u8 nport, u8 reg,
956 ret = ub960_rxport_select(priv, nport);
978 static int ub960_txport_select(struct ub960_data *priv, u8 nport)
985 if (priv->reg_current.txport == nport)
989 (nport << 4) | BIT(nport));
992 nport, ret);
996 priv->reg_current.txport = nport;
1001 static int ub960_txport_read(struct ub960_data *priv, u8 nport, u8 reg,
1013 ret = ub960_txport_select(priv, nport);
1035 static int ub960_txport_write(struct ub960_data *priv, u8 nport, u8 reg,
1046 ret = ub960_txport_select(priv, nport);
1064 static int ub960_txport_update_bits(struct ub960_data *priv, u8 nport, u8 reg,
1075 ret = ub960_txport_select(priv, nport);
1287 dev_err(dev, "rx%u: alias pool exhausted\n", rxport->nport);
1302 rxport->nport, addr, alias, reg_idx);
1325 rxport->nport, addr);
1335 rxport->nport, addr, ret);
1339 dev_dbg(dev, "rx%u: client 0x%02x released at slot %u\n", rxport->nport,
1375 u8 nport)
1387 txport->nport = nport;
1392 dev_err(dev, "tx%u: failed to parse endpoint data\n", nport);
1413 dev_err(dev, "tx%u: invalid 'link-frequencies' value\n", nport);
1420 priv->txports[nport] = txport;
1432 static int ub960_csi_handle_events(struct ub960_data *priv, u8 nport)
1438 ret = ub960_txport_read(priv, nport, UB960_TR_CSI_TX_ISR, &csi_tx_isr,
1444 dev_warn(dev, "TX%u: CSI_SYNC_ERROR\n", nport);
1447 dev_warn(dev, "TX%u: CSI_PASS_ERROR\n", nport);
1467 failed_nport = it.nport;
1498 unsigned int nport)
1503 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v, &ret);
1504 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v, &ret);
1505 ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &v, &ret);
1506 ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &v, &ret);
1508 ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_HI, &v, &ret);
1509 ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_LO, &v, &ret);
1511 ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, &v, &ret);
1521 ret = ub960_rxport_clear_errors(priv, it.nport);
1530 unsigned int nport, s8 *strobe_pos)
1536 ret = ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1544 ret = ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1552 ret = ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_0, &v, NULL);
1558 ret = ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_1, &v, NULL);
1570 unsigned int nport, s8 strobe_pos)
1587 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1590 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1610 unsigned int nport, u8 *eq_level)
1615 ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_STATUS, &v, NULL);
1626 unsigned int nport, u8 eq_level)
1641 ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v, NULL);
1651 ret = ub960_rxport_write(priv, nport, UB960_RR_AEQ_BYPASS, v, NULL);
1659 unsigned int nport, u8 eq_min, u8 eq_max)
1663 ub960_rxport_write(priv, nport, UB960_RR_AEQ_MIN_MAX,
1669 ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_CTL2,
1676 static int ub960_rxport_config_eq(struct ub960_data *priv, unsigned int nport)
1678 struct ub960_rxport *rxport = priv->rxports[nport];
1710 ret = ub960_rxport_set_strobe_pos(priv, nport,
1713 ret = ub960_rxport_set_strobe_pos(priv, nport, 0);
1719 ret = ub960_rxport_set_eq_level(priv, nport,
1725 ret = ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_BYPASS,
1732 ret = ub960_rxport_set_eq_range(priv, nport,
1739 ret = ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_BYPASS,
1749 static int ub960_rxport_link_ok(struct ub960_data *priv, unsigned int nport,
1760 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1,
1770 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2,
1775 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &csi_rx_sts,
1780 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER,
1785 ret = ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &bcc_sts,
1790 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI,
1836 u8 nport;
1856 for_each_set_bit(nport, &port_mask,
1858 struct ub960_rxport *rxport = priv->rxports[nport];
1864 ret = ub960_rxport_link_ok(priv, nport, &ok);
1876 if (!ok || !(link_ok_mask & BIT(nport)))
1880 link_ok_mask |= BIT(nport);
1882 link_ok_mask &= ~BIT(nport);
1908 for_each_set_bit(nport, &port_mask, priv->hw_data->num_rxports) {
1909 struct ub960_rxport *rxport = priv->rxports[nport];
1916 if (!(link_ok_mask & BIT(nport))) {
1917 dev_dbg(dev, "\trx%u: not locked\n", nport);
1921 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH,
1929 nport, ((u64)v * HZ_PER_MHZ) >> 8);
1931 ret = ub960_rxport_get_strobe_pos(priv, nport,
1936 ret = ub960_rxport_get_eq_level(priv, nport, &eq_level);
1942 nport, strobe_pos, eq_level,
2019 rxport->nport, reg, ret);
2044 rxport->nport, reg, ret);
2059 u8 nport = rxport->nport;
2068 ub960_rxport_read(priv, nport, UB960_RR_SENSOR_STS_2, &ser_temp_code,
2072 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2106 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2123 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2135 u8 nport = rxport->nport;
2142 nport);
2153 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2169 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2177 static int ub960_rxport_add_serializer(struct ub960_data *priv, u8 nport)
2179 struct ub960_rxport *rxport = priv->rxports[nport];
2187 ser_pdata->port = nport;
2203 dev_err(dev, "rx%u: cannot add %s i2c device", nport,
2209 nport, rxport->ser.client->addr,
2215 static void ub960_rxport_remove_serializer(struct ub960_data *priv, u8 nport)
2217 struct ub960_rxport *rxport = priv->rxports[nport];
2230 ret = ub960_rxport_add_serializer(priv, it.nport);
2232 failed_nport = it.nport;
2255 ub960_rxport_remove_serializer(priv, it.nport);
2261 unsigned int nport = txport->nport;
2276 return ub960_txport_write(priv, nport, UB960_TR_CSI_CTL, csi_ctl, NULL);
2363 for (unsigned int nport = 0; nport < priv->hw_data->num_txports;
2364 nport++) {
2365 struct ub960_txport *txport = priv->txports[nport];
2381 unsigned int nport = rxport->nport;
2415 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2422 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG,
2429 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2,
2444 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG, 0x3,
2451 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3,
2455 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_HI, 0x07, &ret);
2456 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_LO, 0x7f, &ret);
2459 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2464 ub960_rxport_write(priv, nport, UB960_RR_SER_ALIAS_ID,
2468 ub960_rxport_config_eq(priv, nport);
2471 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport),
2497 port_mask |= BIT(it.nport);
2515 ub960_rxport_update_bits(priv, it.nport, UB960_RR_BCC_CONFIG,
2539 unsigned int nport)
2544 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), 0, &ret);
2547 ub960_rxport_write(priv, nport, UB9702_RR_RX_CTL_2, 0x1b, &ret);
2550 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, BIT(4), 0,
2554 ub960_rxport_write(priv, nport, UB9702_RR_RX_CTL_1, 0x15, &ret);
2557 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2561 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2565 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2569 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2573 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2580 unsigned int nport)
2587 if (priv->rxports[nport]->cdr_mode == RXPORT_CDR_FPD4) {
2601 ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport),
2605 ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport),
2609 ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport),
2617 unsigned int nport)
2622 ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x0, &ret);
2625 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2631 ret = ub960_set_bc_drv_config_ub9702(priv, nport);
2636 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2644 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport),
2655 unsigned int nport)
2660 ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x1, &ret);
2664 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2670 ret = ub960_set_bc_drv_config_ub9702(priv, nport);
2675 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2683 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport),
2694 unsigned int nport)
2699 ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x2, &ret);
2702 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2706 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2712 ret = ub960_set_bc_drv_config_ub9702(priv, nport);
2717 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport),
2724 unsigned int nport)
2729 ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x5, &ret);
2731 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2735 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2742 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3 << 6,
2746 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3,
2747 priv->rxports[nport]->lv_fv_pol, &ret);
2752 ret = ub960_set_bc_drv_config_ub9702(priv, nport);
2757 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport),
2764 unsigned int nport)
2767 struct ub960_rxport *rxport = priv->rxports[nport];
2771 ret = ub960_turn_off_rxport_ub9702(priv, nport);
2775 dev_dbg(dev, "rx%u: disabled\n", nport);
2783 ret = ub960_set_fpd4_sync_mode_ub9702(priv, nport);
2787 dev_dbg(dev, "rx%u: FPD-Link IV SYNC mode\n", nport);
2790 ret = ub960_set_fpd4_async_mode_ub9702(priv, nport);
2794 dev_dbg(dev, "rx%u: FPD-Link IV ASYNC mode\n", nport);
2797 dev_err(dev, "rx%u: unsupported FPD4 mode %u\n", nport,
2806 ret = ub960_set_fpd3_sync_mode_ub9702(priv, nport);
2810 dev_dbg(dev, "rx%u: FPD-Link III SYNC mode\n", nport);
2813 ret = ub960_set_raw10_dvp_mode_ub9702(priv, nport);
2818 nport);
2822 "rx%u: unsupported FPD3 mode %u\n", nport,
2830 nport, rxport->cdr_mode);
2838 unsigned int nport)
2851 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1,
2865 UB960_IND_TARGET_RX_ANA(nport),
2875 UB960_IND_TARGET_RX_ANA(nport),
2883 dev_dbg(dev, "rx%u: no lock, retry = %u\n", nport,
2889 ret = ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2898 nport);
2909 UB960_IND_TARGET_RX_ANA(nport),
2919 UB960_IND_TARGET_RX_ANA(nport),
2929 nport, retry);
2935 nport, rx_aeq, rx_aeq_limit, retry);
2938 nport);
2943 dev_err(dev, "rx%u: max number of retries: %s\n", nport,
2950 unsigned int nport)
2956 ret = ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2962 dev_dbg(dev, "rx%u: initial AEQ = %#x\n", nport, read_aeq_init);
2965 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2968 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2971 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2975 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2978 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2981 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2984 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2987 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2990 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2994 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
2997 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
3000 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
3003 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
3009 dev_dbg(dev, "rx%u: enable FPD-Link IV AEQ LMS\n", nport);
3015 unsigned int nport)
3021 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
3024 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
3033 ret = ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
3038 dev_dbg(dev, "rx%u: enabled FPD-Link IV DFE LMS", nport);
3052 ret = ub960_rxport_update_bits(priv, it.nport,
3072 ub960_rxport_write(priv, it.nport, UB960_RR_SER_ID,
3079 ub960_rxport_write(priv, it.nport, UB960_RR_SER_ALIAS_ID,
3098 ub960_rxport_write(priv, it.nport, UB9702_RR_RX_SM_SEL_2, 0x10,
3102 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(it.nport),
3110 it.nport);
3114 port_mask |= BIT(it.nport);
3121 ret = ub960_configure_rx_port_ub9702(priv, it.nport);
3133 ret = ub960_rxport_write(priv, it.nport,
3140 it.nport);
3148 UB960_IND_TARGET_RX_ANA(it.nport),
3154 dev_dbg(dev, "rx%u: AEQ restart\n", it.nport);
3161 ret = ub960_lock_recovery_ub9702(priv, it.nport);
3167 ret = ub960_enable_aeq_lms_ub9702(priv, it.nport);
3174 ret = ub960_rxport_write(priv, it.nport,
3187 ret = ub960_rxport_write(priv, it.nport,
3206 ret = ub960_enable_dfe_lms_ub9702(priv, it.nport);
3226 ub960_rxport_write(priv, it.nport, UB960_RR_PORT_ICR_HI, 0x07,
3228 ub960_rxport_write(priv, it.nport, UB960_RR_PORT_ICR_LO, 0x7f,
3232 ub960_rxport_update_bits(priv, it.nport, UB960_RR_SER_ALIAS_ID,
3237 ub960_rxport_update_bits(priv, it.nport, UB960_RR_BCC_CONFIG,
3254 ret = ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(it.nport),
3260 dev_dbg(dev, "rx%u: final AEQ = %#x\n", it.nport, final_aeq);
3275 static int ub960_rxport_handle_events(struct ub960_data *priv, u8 nport)
3285 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &rx_port_sts1,
3287 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &rx_port_sts2,
3289 ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &csi_rx_sts, &ret);
3290 ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &bcc_sts, &ret);
3298 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI,
3301 dev_err(dev, "rx%u parity errors: %u\n", nport, v);
3305 dev_err(dev, "rx%u BCC CRC error\n", nport);
3308 dev_err(dev, "rx%u BCC SEQ error\n", nport);
3311 dev_err(dev, "rx%u line length unstable\n", nport);
3314 dev_err(dev, "rx%u FPD3 encode error\n", nport);
3317 dev_err(dev, "rx%u buffer error\n", nport);
3320 dev_err(dev, "rx%u CSI error: %#02x\n", nport, csi_rx_sts);
3323 dev_err(dev, "rx%u CSI ECC1 error\n", nport);
3326 dev_err(dev, "rx%u CSI ECC2 error\n", nport);
3329 dev_err(dev, "rx%u CSI checksum error\n", nport);
3332 dev_err(dev, "rx%u CSI length error\n", nport);
3335 dev_err(dev, "rx%u BCC error: %#02x\n", nport, bcc_sts);
3338 dev_err(dev, "rx%u BCC response error", nport);
3341 dev_err(dev, "rx%u BCC slave timeout", nport);
3344 dev_err(dev, "rx%u BCC slave error", nport);
3347 dev_err(dev, "rx%u BCC master timeout", nport);
3350 dev_err(dev, "rx%u BCC master error", nport);
3353 dev_err(dev, "rx%u BCC sequence error", nport);
3358 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_LEN_1,
3361 dev_dbg(dev, "rx%u line len changed: %u\n", nport, v);
3367 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_COUNT_HI,
3370 dev_dbg(dev, "rx%u line count changed: %u\n", nport, v);
3374 dev_dbg(dev, "rx%u: %s, %s, %s, %s\n", nport,
3434 static int ub960_enable_tx_port(struct ub960_data *priv, unsigned int nport)
3438 dev_dbg(dev, "enable TX port %u\n", nport);
3440 return ub960_txport_update_bits(priv, nport, UB960_TR_CSI_CTL,
3445 static int ub960_disable_tx_port(struct ub960_data *priv, unsigned int nport)
3449 dev_dbg(dev, "disable TX port %u\n", nport);
3451 return ub960_txport_update_bits(priv, nport, UB960_TR_CSI_CTL,
3455 static int ub960_enable_rx_port(struct ub960_data *priv, unsigned int nport)
3459 dev_dbg(dev, "enable RX port %u\n", nport);
3463 UB960_SR_FWD_CTL1_PORT_DIS(nport), 0, NULL);
3466 static int ub960_disable_rx_port(struct ub960_data *priv, unsigned int nport)
3470 dev_dbg(dev, "disable RX port %u\n", nport);
3474 UB960_SR_FWD_CTL1_PORT_DIS(nport),
3475 UB960_SR_FWD_CTL1_PORT_DIS(nport), NULL);
3509 it.nport);
3543 unsigned int nport;
3545 nport = ub960_pad_to_port(priv, route->sink_pad);
3547 rxport = priv->rxports[nport];
3555 rx_data[nport].tx_port = ub960_pad_to_port(priv, route->source_pad);
3557 rx_data[nport].num_streams++;
3564 if (rx_data[nport].num_streams > 2)
3580 nport, fmt->height);
3584 rx_data[nport].meta_dt = ub960_fmt->datatype;
3585 rx_data[nport].meta_lines = fmt->height;
3587 rx_data[nport].pixel_dt = ub960_fmt->datatype;
3600 unsigned long nport = it.nport;
3602 u8 vc = vc_map[nport];
3604 if (rx_data[nport].num_streams == 0)
3609 ub960_rxport_write(priv, nport, UB960_RR_RAW10_ID,
3610 rx_data[nport].pixel_dt | (vc << UB960_RR_RAW10_ID_VC_SHIFT),
3613 ub960_rxport_write(priv, nport,
3615 (rx_data[nport].meta_lines << UB960_RR_RAW_EMBED_DTYPE_LINES_SHIFT) |
3616 rx_data[nport].meta_dt, &ret);
3629 ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP,
3638 /* Map all VCs from this port to VC(nport) */
3640 ub960_rxport_write(priv, nport,
3642 (nport << 4) | nport,
3649 if (rx_data[nport].tx_port == 1)
3650 fwd_ctl |= BIT(nport); /* forward to TX1 */
3652 fwd_ctl &= ~BIT(nport); /* forward to TX0 */
3702 unsigned int nport;
3710 nport = ub960_pad_to_port(priv, route->sink_pad);
3712 sink_streams[nport] |= BIT_ULL(route->sink_stream);
3716 unsigned int nport = it.nport;
3718 if (!sink_streams[nport])
3722 if (!priv->stream_enable_mask[nport]) {
3723 ret = ub960_enable_rx_port(priv, nport);
3725 failed_port = nport;
3730 priv->stream_enable_mask[nport] |= sink_streams[nport];
3732 dev_dbg(dev, "enable RX port %u streams %#llx\n", nport,
3733 sink_streams[nport]);
3736 priv->rxports[nport]->source.sd,
3737 priv->rxports[nport]->source.pad,
3738 sink_streams[nport]);
3740 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
3742 if (!priv->stream_enable_mask[nport])
3743 ub960_disable_rx_port(priv, nport);
3745 failed_port = nport;
3755 for (unsigned int nport = 0; nport < failed_port; nport++) {
3756 if (!sink_streams[nport])
3759 dev_dbg(dev, "disable RX port %u streams %#llx\n", nport,
3760 sink_streams[nport]);
3763 priv->rxports[nport]->source.sd,
3764 priv->rxports[nport]->source.pad,
3765 sink_streams[nport]);
3769 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
3772 if (!priv->stream_enable_mask[nport])
3773 ub960_disable_rx_port(priv, nport);
3799 unsigned int nport;
3807 nport = ub960_pad_to_port(priv, route->sink_pad);
3809 sink_streams[nport] |= BIT_ULL(route->sink_stream);
3813 unsigned int nport = it.nport;
3815 if (!sink_streams[nport])
3818 dev_dbg(dev, "disable RX port %u streams %#llx\n", nport,
3819 sink_streams[nport]);
3822 priv->rxports[nport]->source.sd,
3823 priv->rxports[nport]->source.pad,
3824 sink_streams[nport]);
3828 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
3831 if (!priv->stream_enable_mask[nport])
3832 ub960_disable_rx_port(priv, nport);
3912 unsigned int nport;
3918 nport = ub960_pad_to_port(priv, route->sink_pad);
3920 ret = v4l2_subdev_call(priv->rxports[nport]->source.sd, pad,
3922 priv->rxports[nport]->source.pad,
3950 fd->entry[fd->num_entries].bus.csi2.vc = vc_map[nport];
4059 unsigned int nport)
4087 ret = ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos);
4095 ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v, NULL);
4104 ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_MIN_MAX, &v,
4114 ret = ub960_rxport_get_eq_level(priv, nport, &eq_level);
4143 for (unsigned int nport = 0; nport < priv->hw_data->num_txports;
4144 nport++) {
4145 struct ub960_txport *txport = priv->txports[nport];
4147 dev_info(dev, "TX %u\n", nport);
4154 ret = ub960_txport_read(priv, nport, UB960_TR_CSI_STS, &v, NULL);
4161 ret = ub960_read16(priv, UB960_SR_CSI_FRAME_COUNT_HI(nport),
4168 ret = ub960_read16(priv, UB960_SR_CSI_FRAME_ERR_COUNT_HI(nport),
4175 ret = ub960_read16(priv, UB960_SR_CSI_LINE_COUNT_HI(nport),
4182 ret = ub960_read16(priv, UB960_SR_CSI_LINE_ERR_COUNT_HI(nport),
4191 unsigned int nport = it.nport;
4193 dev_info(dev, "RX %u\n", nport);
4200 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v,
4211 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v,
4218 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH,
4225 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI,
4232 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_COUNT_HI,
4239 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_LEN_1,
4246 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER,
4254 ret = ub960_log_status_ub960_sp_eq(priv, nport);
4267 ret = ub960_rxport_read(priv, nport, ctl_reg, &v, NULL);
4332 if (int_sts & UB960_SR_INTERRUPT_STS_IS_RX(it.nport)) {
4333 ret = ub960_rxport_handle_events(priv, it.nport);
4356 unsigned int nport;
4358 for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
4359 struct ub960_txport *txport = priv->txports[nport];
4365 priv->txports[nport] = NULL;
4378 priv->rxports[it.nport] = NULL;
4388 unsigned int nport = rxport->nport;
4401 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
4407 dev_err(dev, "rx%u: bad 'ti,cdr-mode' %u\n", nport, cdr_mode);
4412 dev_err(dev, "rx%u: FPD-Link 4 CDR not supported\n", nport);
4420 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
4426 dev_err(dev, "rx%u: bad 'ti,rx-mode' %u\n", nport, rx_mode);
4433 dev_err(dev, "rx%u: unsupported 'ti,rx-mode' %u\n", nport,
4453 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
4461 nport, strobe_pos);
4470 nport);
4476 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
4483 nport, eq_level);
4494 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
4502 dev_err(dev, "rx%u: missing 'serializer' node\n", nport);
4522 unsigned int nport = rxport->nport;
4529 dev_err(dev, "rx%u: no remote endpoint\n", nport);
4547 dev_err(dev, "rx%u: failed to parse endpoint data\n", nport);
4565 static int ub960_parse_dt_rxport(struct ub960_data *priv, unsigned int nport,
4580 priv->rxports[nport] = rxport;
4582 rxport->nport = nport;
4589 rxport->vpoc = devm_regulator_get_optional(dev, vpoc_names[nport]);
4596 nport, ret);
4612 priv->rxports[nport] = NULL;
4619 unsigned int nport)
4636 if (nport == link_num)
4664 unsigned int nport = it.nport;
4666 link_fwnode = ub960_fwnode_get_link_by_regs(links_fwnode, nport);
4671 nport, 0, 0);
4677 ret = ub960_parse_dt_rxport(priv, nport, link_fwnode,
4684 dev_err(dev, "rx%u: failed to parse RX port\n", nport);
4702 u32 nport;
4705 for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
4706 unsigned int port = nport + priv->hw_data->num_rxports;
4714 ret = ub960_parse_dt_txport(priv, ep_fwnode, nport);
4752 u8 nport = rxport->nport;
4767 rxport->source.pad, &priv->sd.entity, nport,
4773 priv->sd.name, nport);
4816 it.nport, asd);
5133 ub960_write(priv, UB960_SR_I2C_RX_ID(it.nport),
5134 (UB960_DEBUG_I2C_RX_ID + it.nport) << 1, NULL);