Lines Matching +full:0 +full:x1c01
20 #define CCS_R_MODULE_MODEL_ID CCI_REG16(0x0000)
21 #define CCS_R_MODULE_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
22 #define CCS_R_FRAME_COUNT CCI_REG8(0x0005)
23 #define CCS_R_PIXEL_ORDER CCI_REG8(0x0006)
24 #define CCS_PIXEL_ORDER_GRBG 0U
28 #define CCS_R_MIPI_CCS_VERSION CCI_REG8(0x0007)
29 #define CCS_MIPI_CCS_VERSION_V1_0 0x10
30 #define CCS_MIPI_CCS_VERSION_V1_1 0x11
32 #define CCS_MIPI_CCS_VERSION_MAJOR_MASK 0xf0
33 #define CCS_MIPI_CCS_VERSION_MINOR_SHIFT 0U
34 #define CCS_MIPI_CCS_VERSION_MINOR_MASK 0xf
35 #define CCS_R_DATA_PEDESTAL CCI_REG16(0x0008)
36 #define CCS_R_MODULE_MANUFACTURER_ID CCI_REG16(0x000e)
37 #define CCS_R_MODULE_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
38 #define CCS_R_MODULE_DATE_YEAR CCI_REG8(0x0012)
39 #define CCS_R_MODULE_DATE_MONTH CCI_REG8(0x0013)
40 #define CCS_R_MODULE_DATE_DAY CCI_REG8(0x0014)
41 #define CCS_R_MODULE_DATE_PHASE CCI_REG8(0x0015)
42 #define CCS_MODULE_DATE_PHASE_SHIFT 0U
43 #define CCS_MODULE_DATE_PHASE_MASK 0x7
44 #define CCS_MODULE_DATE_PHASE_TS 0U
48 #define CCS_R_SENSOR_MODEL_ID CCI_REG16(0x0016)
49 #define CCS_R_SENSOR_REVISION_NUMBER CCI_REG8(0x0018)
50 #define CCS_R_SENSOR_FIRMWARE_VERSION CCI_REG8(0x001a)
51 #define CCS_R_SERIAL_NUMBER CCI_REG32(0x001c)
52 #define CCS_R_SENSOR_MANUFACTURER_ID CCI_REG16(0x0020)
53 #define CCS_R_SENSOR_REVISION_NUMBER_16 CCI_REG16(0x0022)
54 #define CCS_R_FRAME_FORMAT_MODEL_TYPE CCI_REG8(0x0040)
57 #define CCS_R_FRAME_FORMAT_MODEL_SUBTYPE CCI_REG8(0x0041)
58 #define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
59 #define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf
61 #define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0
62 #define CCS_R_FRAME_FORMAT_DESCRIPTOR(n) CCI_REG16(0x0042 + (n) * 2)
63 #define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MIN_N 0U
65 #define CCS_R_FRAME_FORMAT_DESCRIPTOR_4(n) CCI_REG32(0x0060 + (n) * 4)
66 #define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_SHIFT 0U
67 #define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK 0xfff
69 #define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK 0xf000
82 #define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MIN_N 0U
84 #define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_SHIFT 0U
85 #define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK 0xffff
87 #define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK 0xf0000000
100 #define CCS_R_ANALOG_GAIN_CAPABILITY CCI_REG16(0x0080)
101 #define CCS_ANALOG_GAIN_CAPABILITY_GLOBAL 0U
103 #define CCS_R_ANALOG_GAIN_CODE_MIN CCI_REG16(0x0084)
104 #define CCS_R_ANALOG_GAIN_CODE_MAX CCI_REG16(0x0086)
105 #define CCS_R_ANALOG_GAIN_CODE_STEP CCI_REG16(0x0088)
106 #define CCS_R_ANALOG_GAIN_TYPE CCI_REG16(0x008a)
107 #define CCS_R_ANALOG_GAIN_M0 CCI_REG16(0x008c)
108 #define CCS_R_ANALOG_GAIN_C0 CCI_REG16(0x008e)
109 #define CCS_R_ANALOG_GAIN_M1 CCI_REG16(0x0090)
110 #define CCS_R_ANALOG_GAIN_C1 CCI_REG16(0x0092)
111 #define CCS_R_ANALOG_LINEAR_GAIN_MIN CCI_REG16(0x0094)
112 #define CCS_R_ANALOG_LINEAR_GAIN_MAX CCI_REG16(0x0096)
113 #define CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE CCI_REG16(0x0098)
114 #define CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN CCI_REG16(0x009a)
115 #define CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX CCI_REG16(0x009c)
116 #define CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE CCI_REG16(0x009e)
117 #define CCS_R_DATA_FORMAT_MODEL_TYPE CCI_REG8(0x00c0)
120 #define CCS_R_DATA_FORMAT_MODEL_SUBTYPE CCI_REG8(0x00c1)
121 #define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
122 #define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf
124 #define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0
125 #define CCS_R_DATA_FORMAT_DESCRIPTOR(n) CCI_REG16(0x00c2 + (n) * 2)
126 #define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MIN_N 0U
128 #define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_SHIFT 0U
129 #define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK 0xff
131 #define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_MASK 0xff00
132 #define CCS_R_MODE_SELECT CCI_REG8(0x0100)
133 #define CCS_MODE_SELECT_SOFTWARE_STANDBY 0U
135 #define CCS_R_IMAGE_ORIENTATION CCI_REG8(0x0101)
136 #define CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR BIT(0)
138 #define CCS_R_SOFTWARE_RESET CCI_REG8(0x0103)
139 #define CCS_SOFTWARE_RESET_OFF 0U
141 #define CCS_R_GROUPED_PARAMETER_HOLD CCI_REG8(0x0104)
142 #define CCS_R_MASK_CORRUPTED_FRAMES CCI_REG8(0x0105)
143 #define CCS_MASK_CORRUPTED_FRAMES_ALLOW 0U
145 #define CCS_R_FAST_STANDBY_CTRL CCI_REG8(0x0106)
146 #define CCS_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0U
148 #define CCS_R_CCI_ADDRESS_CTRL CCI_REG8(0x0107)
149 #define CCS_R_2ND_CCI_IF_CTRL CCI_REG8(0x0108)
150 #define CCS_2ND_CCI_IF_CTRL_ENABLE BIT(0)
152 #define CCS_R_2ND_CCI_ADDRESS_CTRL CCI_REG8(0x0109)
153 #define CCS_R_CSI_CHANNEL_IDENTIFIER CCI_REG8(0x0110)
154 #define CCS_R_CSI_SIGNALING_MODE CCI_REG8(0x0111)
157 #define CCS_R_CSI_DATA_FORMAT CCI_REG16(0x0112)
158 #define CCS_R_CSI_LANE_MODE CCI_REG8(0x0114)
159 #define CCS_R_DPCM_FRAME_DT CCI_REG8(0x011d)
160 #define CCS_R_BOTTOM_EMBEDDED_DATA_DT CCI_REG8(0x011e)
161 #define CCS_R_BOTTOM_EMBEDDED_DATA_VC CCI_REG8(0x011f)
162 #define CCS_R_GAIN_MODE CCI_REG8(0x0120)
163 #define CCS_GAIN_MODE_GLOBAL 0U
165 #define CCS_R_ADC_BIT_DEPTH CCI_REG8(0x0121)
166 #define CCS_R_EMB_DATA_CTRL CCI_REG8(0x0122)
167 #define CCS_EMB_DATA_CTRL_RAW8_PACKING_FOR_RAW16 BIT(0)
170 #define CCS_R_GPIO_TRIG_MODE CCI_REG8(0x0130)
171 #define CCS_R_EXTCLK_FREQUENCY_MHZ (CCI_REG16(0x0136) | CCS_FL_IREAL)
172 #define CCS_R_TEMP_SENSOR_CTRL CCI_REG8(0x0138)
173 #define CCS_TEMP_SENSOR_CTRL_ENABLE BIT(0)
174 #define CCS_R_TEMP_SENSOR_MODE CCI_REG8(0x0139)
175 #define CCS_R_TEMP_SENSOR_OUTPUT CCI_REG8(0x013a)
176 #define CCS_R_FINE_INTEGRATION_TIME CCI_REG16(0x0200)
177 #define CCS_R_COARSE_INTEGRATION_TIME CCI_REG16(0x0202)
178 #define CCS_R_ANALOG_GAIN_CODE_GLOBAL CCI_REG16(0x0204)
179 #define CCS_R_ANALOG_LINEAR_GAIN_GLOBAL CCI_REG16(0x0206)
180 #define CCS_R_ANALOG_EXPONENTIAL_GAIN_GLOBAL CCI_REG16(0x0208)
181 #define CCS_R_DIGITAL_GAIN_GLOBAL CCI_REG16(0x020e)
182 #define CCS_R_SHORT_ANALOG_GAIN_GLOBAL CCI_REG16(0x0216)
183 #define CCS_R_SHORT_DIGITAL_GAIN_GLOBAL CCI_REG16(0x0218)
184 #define CCS_R_HDR_MODE CCI_REG8(0x0220)
185 #define CCS_HDR_MODE_ENABLED BIT(0)
192 #define CCS_R_HDR_RESOLUTION_REDUCTION CCI_REG8(0x0221)
193 #define CCS_HDR_RESOLUTION_REDUCTION_ROW_SHIFT 0U
194 #define CCS_HDR_RESOLUTION_REDUCTION_ROW_MASK 0xf
196 #define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_MASK 0xf0
197 #define CCS_R_EXPOSURE_RATIO CCI_REG8(0x0222)
198 #define CCS_R_HDR_INTERNAL_BIT_DEPTH CCI_REG8(0x0223)
199 #define CCS_R_DIRECT_SHORT_INTEGRATION_TIME CCI_REG16(0x0224)
200 #define CCS_R_SHORT_ANALOG_LINEAR_GAIN_GLOBAL CCI_REG16(0x0226)
201 #define CCS_R_SHORT_ANALOG_EXPONENTIAL_GAIN_GLOBAL CCI_REG16(0x0228)
202 #define CCS_R_VT_PIX_CLK_DIV CCI_REG16(0x0300)
203 #define CCS_R_VT_SYS_CLK_DIV CCI_REG16(0x0302)
204 #define CCS_R_PRE_PLL_CLK_DIV CCI_REG16(0x0304)
205 #define CCS_R_PLL_MULTIPLIER CCI_REG16(0x0306)
206 #define CCS_R_OP_PIX_CLK_DIV CCI_REG16(0x0308)
207 #define CCS_R_OP_SYS_CLK_DIV CCI_REG16(0x030a)
208 #define CCS_R_OP_PRE_PLL_CLK_DIV CCI_REG16(0x030c)
209 #define CCS_R_OP_PLL_MULTIPLIER CCI_REG16(0x030e)
210 #define CCS_R_PLL_MODE CCI_REG8(0x0310)
211 #define CCS_PLL_MODE_SHIFT 0U
212 #define CCS_PLL_MODE_MASK 0x1
213 #define CCS_PLL_MODE_SINGLE 0U
215 #define CCS_R_OP_PIX_CLK_DIV_REV CCI_REG16(0x0312)
216 #define CCS_R_OP_SYS_CLK_DIV_REV CCI_REG16(0x0314)
217 #define CCS_R_FRAME_LENGTH_LINES CCI_REG16(0x0340)
218 #define CCS_R_LINE_LENGTH_PCK CCI_REG16(0x0342)
219 #define CCS_R_X_ADDR_START CCI_REG16(0x0344)
220 #define CCS_R_Y_ADDR_START CCI_REG16(0x0346)
221 #define CCS_R_X_ADDR_END CCI_REG16(0x0348)
222 #define CCS_R_Y_ADDR_END CCI_REG16(0x034a)
223 #define CCS_R_X_OUTPUT_SIZE CCI_REG16(0x034c)
224 #define CCS_R_Y_OUTPUT_SIZE CCI_REG16(0x034e)
225 #define CCS_R_FRAME_LENGTH_CTRL CCI_REG8(0x0350)
226 #define CCS_FRAME_LENGTH_CTRL_AUTOMATIC BIT(0)
227 #define CCS_R_TIMING_MODE_CTRL CCI_REG8(0x0352)
228 #define CCS_TIMING_MODE_CTRL_MANUAL_READOUT BIT(0)
230 #define CCS_R_START_READOUT_RS CCI_REG8(0x0353)
231 #define CCS_START_READOUT_RS_MANUAL_READOUT_START BIT(0)
232 #define CCS_R_FRAME_MARGIN CCI_REG16(0x0354)
233 #define CCS_R_X_EVEN_INC CCI_REG16(0x0380)
234 #define CCS_R_X_ODD_INC CCI_REG16(0x0382)
235 #define CCS_R_Y_EVEN_INC CCI_REG16(0x0384)
236 #define CCS_R_Y_ODD_INC CCI_REG16(0x0386)
237 #define CCS_R_MONOCHROME_EN CCI_REG8(0x0390)
238 #define CCS_MONOCHROME_EN_ENABLED 0U
239 #define CCS_R_SCALING_MODE CCI_REG16(0x0400)
240 #define CCS_SCALING_MODE_NO_SCALING 0U
242 #define CCS_R_SCALE_M CCI_REG16(0x0404)
243 #define CCS_R_SCALE_N CCI_REG16(0x0406)
244 #define CCS_R_DIGITAL_CROP_X_OFFSET CCI_REG16(0x0408)
245 #define CCS_R_DIGITAL_CROP_Y_OFFSET CCI_REG16(0x040a)
246 #define CCS_R_DIGITAL_CROP_IMAGE_WIDTH CCI_REG16(0x040c)
247 #define CCS_R_DIGITAL_CROP_IMAGE_HEIGHT CCI_REG16(0x040e)
248 #define CCS_R_COMPRESSION_MODE CCI_REG16(0x0500)
249 #define CCS_COMPRESSION_MODE_NONE 0U
251 #define CCS_R_TEST_PATTERN_MODE CCI_REG16(0x0600)
252 #define CCS_TEST_PATTERN_MODE_NONE 0U
258 #define CCS_R_TEST_DATA_RED CCI_REG16(0x0602)
259 #define CCS_R_TEST_DATA_GREENR CCI_REG16(0x0604)
260 #define CCS_R_TEST_DATA_BLUE CCI_REG16(0x0606)
261 #define CCS_R_TEST_DATA_GREENB CCI_REG16(0x0608)
262 #define CCS_R_VALUE_STEP_SIZE_SMOOTH CCI_REG8(0x060a)
263 #define CCS_R_VALUE_STEP_SIZE_QUANTISED CCI_REG8(0x060b)
264 #define CCS_R_TCLK_POST CCI_REG8(0x0800)
265 #define CCS_R_THS_PREPARE CCI_REG8(0x0801)
266 #define CCS_R_THS_ZERO_MIN CCI_REG8(0x0802)
267 #define CCS_R_THS_TRAIL CCI_REG8(0x0803)
268 #define CCS_R_TCLK_TRAIL_MIN CCI_REG8(0x0804)
269 #define CCS_R_TCLK_PREPARE CCI_REG8(0x0805)
270 #define CCS_R_TCLK_ZERO CCI_REG8(0x0806)
271 #define CCS_R_TLPX CCI_REG8(0x0807)
272 #define CCS_R_PHY_CTRL CCI_REG8(0x0808)
273 #define CCS_PHY_CTRL_AUTO 0U
276 #define CCS_R_TCLK_POST_EX CCI_REG16(0x080a)
277 #define CCS_R_THS_PREPARE_EX CCI_REG16(0x080c)
278 #define CCS_R_THS_ZERO_MIN_EX CCI_REG16(0x080e)
279 #define CCS_R_THS_TRAIL_EX CCI_REG16(0x0810)
280 #define CCS_R_TCLK_TRAIL_MIN_EX CCI_REG16(0x0812)
281 #define CCS_R_TCLK_PREPARE_EX CCI_REG16(0x0814)
282 #define CCS_R_TCLK_ZERO_EX CCI_REG16(0x0816)
283 #define CCS_R_TLPX_EX CCI_REG16(0x0818)
284 #define CCS_R_REQUESTED_LINK_RATE CCI_REG32(0x0820)
285 #define CCS_R_DPHY_EQUALIZATION_MODE CCI_REG8(0x0824)
286 #define CCS_DPHY_EQUALIZATION_MODE_EQ2 BIT(0)
287 #define CCS_R_PHY_EQUALIZATION_CTRL CCI_REG8(0x0825)
288 #define CCS_PHY_EQUALIZATION_CTRL_ENABLE BIT(0)
289 #define CCS_R_DPHY_PREAMBLE_CTRL CCI_REG8(0x0826)
290 #define CCS_DPHY_PREAMBLE_CTRL_ENABLE BIT(0)
291 #define CCS_R_DPHY_PREAMBLE_LENGTH CCI_REG8(0x0826)
292 #define CCS_R_PHY_SSC_CTRL CCI_REG8(0x0828)
293 #define CCS_PHY_SSC_CTRL_ENABLE BIT(0)
294 #define CCS_R_MANUAL_LP_CTRL CCI_REG8(0x0829)
295 #define CCS_MANUAL_LP_CTRL_ENABLE BIT(0)
296 #define CCS_R_TWAKEUP CCI_REG8(0x082a)
297 #define CCS_R_TINIT CCI_REG8(0x082b)
298 #define CCS_R_THS_EXIT CCI_REG8(0x082c)
299 #define CCS_R_THS_EXIT_EX CCI_REG16(0x082e)
300 #define CCS_R_PHY_PERIODIC_CALIBRATION_CTRL CCI_REG8(0x0830)
301 #define CCS_PHY_PERIODIC_CALIBRATION_CTRL_FRAME_BLANKING BIT(0)
302 #define CCS_R_PHY_PERIODIC_CALIBRATION_INTERVAL CCI_REG8(0x0831)
303 #define CCS_R_PHY_INIT_CALIBRATION_CTRL CCI_REG8(0x0832)
304 #define CCS_PHY_INIT_CALIBRATION_CTRL_STREAM_START BIT(0)
305 #define CCS_R_DPHY_CALIBRATION_MODE CCI_REG8(0x0833)
306 #define CCS_DPHY_CALIBRATION_MODE_ALSO_ALTERNATE BIT(0)
307 #define CCS_R_CPHY_CALIBRATION_MODE CCI_REG8(0x0834)
308 #define CCS_CPHY_CALIBRATION_MODE_FORMAT_1 0U
311 #define CCS_R_T3_CALPREAMBLE_LENGTH CCI_REG8(0x0835)
312 #define CCS_R_T3_CALPREAMBLE_LENGTH_PER CCI_REG8(0x0836)
313 #define CCS_R_T3_CALALTSEQ_LENGTH CCI_REG8(0x0837)
314 #define CCS_R_T3_CALALTSEQ_LENGTH_PER CCI_REG8(0x0838)
315 #define CCS_R_FM2_INIT_SEED CCI_REG16(0x083a)
316 #define CCS_R_T3_CALUDEFSEQ_LENGTH CCI_REG16(0x083c)
317 #define CCS_R_T3_CALUDEFSEQ_LENGTH_PER CCI_REG16(0x083e)
318 #define CCS_R_TGR_PREAMBLE_LENGTH CCI_REG8(0x0841)
320 #define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_SHIFT 0U
321 #define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_MASK 0x3f
322 #define CCS_R_TGR_POST_LENGTH CCI_REG8(0x0842)
323 #define CCS_TGR_POST_LENGTH_POST_LENGTH_SHIFT 0U
324 #define CCS_TGR_POST_LENGTH_POST_LENGTH_MASK 0x1f
325 #define CCS_R_TGR_PREAMBLE_PROG_SEQUENCE(n2) CCI_REG8(0x0843 + (n2))
326 #define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MIN_N2 0U
329 #define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_MASK 0x38
330 #define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_SHIFT 0U
331 #define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_MASK 0x7
332 #define CCS_R_T3_PREPARE CCI_REG16(0x084e)
333 #define CCS_R_T3_LPX CCI_REG16(0x0850)
334 #define CCS_R_ALPS_CTRL CCI_REG8(0x085a)
335 #define CCS_ALPS_CTRL_LVLP_DPHY BIT(0)
338 #define CCS_R_TX_REG_CSI_EPD_EN_SSP_CPHY CCI_REG16(0x0860)
339 #define CCS_R_TX_REG_CSI_EPD_OP_SLP_CPHY CCI_REG16(0x0862)
340 #define CCS_R_TX_REG_CSI_EPD_EN_SSP_DPHY CCI_REG16(0x0864)
341 #define CCS_R_TX_REG_CSI_EPD_OP_SLP_DPHY CCI_REG16(0x0866)
342 #define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_CPHY CCI_REG8(0x0868)
343 #define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_DPHY CCI_REG8(0x0869)
344 #define CCS_R_SCRAMBLING_CTRL CCI_REG8(0x0870)
345 #define CCS_SCRAMBLING_CTRL_ENABLED BIT(0)
347 #define CCS_SCRAMBLING_CTRL_MASK 0xc
348 #define CCS_SCRAMBLING_CTRL_1_SEED_CPHY 0U
350 #define CCS_R_LANE_SEED_VALUE(seed, lane) CCI_REG16(0x0872 + (seed) * 16 + (lane) * 2)
351 #define CCS_LIM_LANE_SEED_VALUE_MIN_SEED 0U
353 #define CCS_LIM_LANE_SEED_VALUE_MIN_LANE 0U
355 #define CCS_R_TX_USL_REV_ENTRY CCI_REG16(0x08c0)
356 #define CCS_R_TX_USL_REV_CLOCK_COUNTER CCI_REG16(0x08c2)
357 #define CCS_R_TX_USL_REV_LP_COUNTER CCI_REG16(0x08c4)
358 #define CCS_R_TX_USL_REV_FRAME_COUNTER CCI_REG16(0x08c6)
359 #define CCS_R_TX_USL_REV_CHRONOLOGICAL_TIMER CCI_REG16(0x08c8)
360 #define CCS_R_TX_USL_FWD_ENTRY CCI_REG16(0x08ca)
361 #define CCS_R_TX_USL_GPIO CCI_REG16(0x08cc)
362 #define CCS_R_TX_USL_OPERATION CCI_REG16(0x08ce)
363 #define CCS_TX_USL_OPERATION_RESET BIT(0)
364 #define CCS_R_TX_USL_ALP_CTRL CCI_REG16(0x08d0)
365 #define CCS_TX_USL_ALP_CTRL_CLOCK_PAUSE BIT(0)
366 #define CCS_R_TX_USL_APP_BTA_ACK_TIMEOUT CCI_REG16(0x08d2)
367 #define CCS_R_TX_USL_SNS_BTA_ACK_TIMEOUT CCI_REG16(0x08d2)
368 #define CCS_R_USL_CLOCK_MODE_D_CTRL CCI_REG8(0x08d2)
369 #define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_STANDBY BIT(0)
372 #define CCS_R_BINNING_MODE CCI_REG8(0x0900)
373 #define CCS_R_BINNING_TYPE CCI_REG8(0x0901)
374 #define CCS_R_BINNING_WEIGHTING CCI_REG8(0x0902)
375 #define CCS_R_DATA_TRANSFER_IF_1_CTRL CCI_REG8(0x0a00)
376 #define CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE BIT(0)
379 #define CCS_R_DATA_TRANSFER_IF_1_STATUS CCI_REG8(0x0a01)
380 #define CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY BIT(0)
384 #define CCS_R_DATA_TRANSFER_IF_1_PAGE_SELECT CCI_REG8(0x0a02)
385 #define CCS_R_DATA_TRANSFER_IF_1_DATA(p) CCI_REG8(0x0a04 + (p))
386 #define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MIN_P 0U
388 #define CCS_R_SHADING_CORRECTION_EN CCI_REG8(0x0b00)
389 #define CCS_SHADING_CORRECTION_EN_ENABLE BIT(0)
390 #define CCS_R_LUMINANCE_CORRECTION_LEVEL CCI_REG8(0x0b01)
391 #define CCS_R_GREEN_IMBALANCE_FILTER_EN CCI_REG8(0x0b02)
392 #define CCS_GREEN_IMBALANCE_FILTER_EN_ENABLE BIT(0)
393 #define CCS_R_MAPPED_DEFECT_CORRECT_EN CCI_REG8(0x0b05)
394 #define CCS_MAPPED_DEFECT_CORRECT_EN_ENABLE BIT(0)
395 #define CCS_R_SINGLE_DEFECT_CORRECT_EN CCI_REG8(0x0b06)
396 #define CCS_SINGLE_DEFECT_CORRECT_EN_ENABLE BIT(0)
397 #define CCS_R_DYNAMIC_COUPLET_CORRECT_EN CCI_REG8(0x0b08)
398 #define CCS_DYNAMIC_COUPLET_CORRECT_EN_ENABLE BIT(0)
399 #define CCS_R_COMBINED_DEFECT_CORRECT_EN CCI_REG8(0x0b0a)
400 #define CCS_COMBINED_DEFECT_CORRECT_EN_ENABLE BIT(0)
401 #define CCS_R_MODULE_SPECIFIC_CORRECTION_EN CCI_REG8(0x0b0c)
402 #define CCS_MODULE_SPECIFIC_CORRECTION_EN_ENABLE BIT(0)
403 #define CCS_R_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN CCI_REG8(0x0b13)
404 #define CCS_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN_ENABLE BIT(0)
405 #define CCS_R_NF_CTRL CCI_REG8(0x0b15)
406 #define CCS_NF_CTRL_LUMA BIT(0)
409 #define CCS_R_OB_READOUT_CONTROL CCI_REG8(0x0b30)
410 #define CCS_OB_READOUT_CONTROL_ENABLE BIT(0)
412 #define CCS_R_OB_VIRTUAL_CHANNEL CCI_REG8(0x0b31)
413 #define CCS_R_OB_DT CCI_REG8(0x0b32)
414 #define CCS_R_OB_DATA_FORMAT CCI_REG8(0x0b33)
415 #define CCS_R_COLOR_TEMPERATURE CCI_REG16(0x0b8c)
416 #define CCS_R_ABSOLUTE_GAIN_GREENR CCI_REG16(0x0b8e)
417 #define CCS_R_ABSOLUTE_GAIN_RED CCI_REG16(0x0b90)
418 #define CCS_R_ABSOLUTE_GAIN_BLUE CCI_REG16(0x0b92)
419 #define CCS_R_ABSOLUTE_GAIN_GREENB CCI_REG16(0x0b94)
420 #define CCS_R_CFA_CONVERSION_CTRL CCI_REG8(0x0ba0)
421 #define CCS_CFA_CONVERSION_CTRL_BAYER_CONVERSION_ENABLE BIT(0)
422 #define CCS_R_FLASH_STROBE_ADJUSTMENT CCI_REG8(0x0c12)
423 #define CCS_R_FLASH_STROBE_START_POINT CCI_REG16(0x0c14)
424 #define CCS_R_TFLASH_STROBE_DELAY_RS_CTRL CCI_REG16(0x0c16)
425 #define CCS_R_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL CCI_REG16(0x0c18)
426 #define CCS_R_FLASH_MODE_RS CCI_REG8(0x0c1a)
427 #define CCS_FLASH_MODE_RS_CONTINUOUS BIT(0)
430 #define CCS_R_FLASH_TRIGGER_RS CCI_REG8(0x0c1b)
431 #define CCS_R_FLASH_STATUS CCI_REG8(0x0c1c)
432 #define CCS_FLASH_STATUS_RETIMED BIT(0)
433 #define CCS_R_SA_STROBE_MODE CCI_REG8(0x0c1d)
434 #define CCS_SA_STROBE_MODE_CONTINUOUS BIT(0)
438 #define CCS_R_SA_STROBE_START_POINT CCI_REG16(0x0c1e)
439 #define CCS_R_TSA_STROBE_DELAY_CTRL CCI_REG16(0x0c20)
440 #define CCS_R_TSA_STROBE_WIDTH_CTRL CCI_REG16(0x0c22)
441 #define CCS_R_SA_STROBE_TRIGGER CCI_REG8(0x0c24)
442 #define CCS_R_SA_STROBE_STATUS CCI_REG8(0x0c25)
443 #define CCS_SA_STROBE_STATUS_RETIMED BIT(0)
444 #define CCS_R_TSA_STROBE_RE_DELAY_CTRL CCI_REG16(0x0c30)
445 #define CCS_R_TSA_STROBE_FE_DELAY_CTRL CCI_REG16(0x0c32)
446 #define CCS_R_PDAF_CTRL CCI_REG16(0x0d00)
447 #define CCS_PDAF_CTRL_ENABLE BIT(0)
451 #define CCS_R_PDAF_VC CCI_REG8(0x0d02)
452 #define CCS_R_PDAF_DT CCI_REG8(0x0d03)
453 #define CCS_R_PD_X_ADDR_START CCI_REG16(0x0d04)
454 #define CCS_R_PD_Y_ADDR_START CCI_REG16(0x0d06)
455 #define CCS_R_PD_X_ADDR_END CCI_REG16(0x0d08)
456 #define CCS_R_PD_Y_ADDR_END CCI_REG16(0x0d0a)
457 #define CCS_R_BRACKETING_LUT_CTRL CCI_REG8(0x0e00)
458 #define CCS_R_BRACKETING_LUT_MODE CCI_REG8(0x0e01)
459 #define CCS_BRACKETING_LUT_MODE_CONTINUE_STREAMING BIT(0)
461 #define CCS_R_BRACKETING_LUT_ENTRY_CTRL CCI_REG8(0x0e02)
462 #define CCS_R_BRACKETING_LUT_FRAME(n) CCI_REG8(0x0e10 + (n))
463 #define CCS_LIM_BRACKETING_LUT_FRAME_MIN_N 0U
465 #define CCS_R_INTEGRATION_TIME_CAPABILITY CCI_REG16(0x1000)
466 #define CCS_INTEGRATION_TIME_CAPABILITY_FINE BIT(0)
467 #define CCS_R_COARSE_INTEGRATION_TIME_MIN CCI_REG16(0x1004)
468 #define CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN CCI_REG16(0x1006)
469 #define CCS_R_FINE_INTEGRATION_TIME_MIN CCI_REG16(0x1008)
470 #define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN CCI_REG16(0x100a)
471 #define CCS_R_DIGITAL_GAIN_CAPABILITY CCI_REG8(0x1081)
472 #define CCS_DIGITAL_GAIN_CAPABILITY_NONE 0U
474 #define CCS_R_DIGITAL_GAIN_MIN CCI_REG16(0x1084)
475 #define CCS_R_DIGITAL_GAIN_MAX CCI_REG16(0x1086)
476 #define CCS_R_DIGITAL_GAIN_STEP_SIZE CCI_REG16(0x1088)
477 #define CCS_R_PEDESTAL_CAPABILITY CCI_REG8(0x10e0)
478 #define CCS_R_ADC_CAPABILITY CCI_REG8(0x10f0)
479 #define CCS_ADC_CAPABILITY_BIT_DEPTH_CTRL BIT(0)
480 #define CCS_R_ADC_BIT_DEPTH_CAPABILITY CCI_REG32(0x10f4)
481 #define CCS_R_MIN_EXT_CLK_FREQ_MHZ (CCI_REG32(0x1100) | CCS_FL_FLOAT_IREAL)
482 #define CCS_R_MAX_EXT_CLK_FREQ_MHZ (CCI_REG32(0x1104) | CCS_FL_FLOAT_IREAL)
483 #define CCS_R_MIN_PRE_PLL_CLK_DIV CCI_REG16(0x1108)
484 #define CCS_R_MAX_PRE_PLL_CLK_DIV CCI_REG16(0x110a)
485 #define CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x110c) | CCS_FL_FLOAT_IREAL)
486 #define CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x1110) | CCS_FL_FLOAT_IREAL)
487 #define CCS_R_MIN_PLL_MULTIPLIER CCI_REG16(0x1114)
488 #define CCS_R_MAX_PLL_MULTIPLIER CCI_REG16(0x1116)
489 #define CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x1118) | CCS_FL_FLOAT_IREAL)
490 #define CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x111c) | CCS_FL_FLOAT_IREAL)
491 #define CCS_R_MIN_VT_SYS_CLK_DIV CCI_REG16(0x1120)
492 #define CCS_R_MAX_VT_SYS_CLK_DIV CCI_REG16(0x1122)
493 #define CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ (CCI_REG32(0x1124) | CCS_FL_FLOAT_IREAL)
494 #define CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ (CCI_REG32(0x1128) | CCS_FL_FLOAT_IREAL)
495 #define CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ (CCI_REG32(0x112c) | CCS_FL_FLOAT_IREAL)
496 #define CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ (CCI_REG32(0x1130) | CCS_FL_FLOAT_IREAL)
497 #define CCS_R_MIN_VT_PIX_CLK_DIV CCI_REG16(0x1134)
498 #define CCS_R_MAX_VT_PIX_CLK_DIV CCI_REG16(0x1136)
499 #define CCS_R_CLOCK_CALCULATION CCI_REG8(0x1138)
500 #define CCS_CLOCK_CALCULATION_LANE_SPEED BIT(0)
504 #define CCS_R_NUM_OF_VT_LANES CCI_REG8(0x1139)
505 #define CCS_R_NUM_OF_OP_LANES CCI_REG8(0x113a)
506 #define CCS_R_OP_BITS_PER_LANE CCI_REG8(0x113b)
507 #define CCS_R_MIN_FRAME_LENGTH_LINES CCI_REG16(0x1140)
508 #define CCS_R_MAX_FRAME_LENGTH_LINES CCI_REG16(0x1142)
509 #define CCS_R_MIN_LINE_LENGTH_PCK CCI_REG16(0x1144)
510 #define CCS_R_MAX_LINE_LENGTH_PCK CCI_REG16(0x1146)
511 #define CCS_R_MIN_LINE_BLANKING_PCK CCI_REG16(0x1148)
512 #define CCS_R_MIN_FRAME_BLANKING_LINES CCI_REG16(0x114a)
513 #define CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE CCI_REG8(0x114c)
514 #define CCS_R_TIMING_MODE_CAPABILITY CCI_REG8(0x114d)
515 #define CCS_TIMING_MODE_CAPABILITY_AUTO_FRAME_LENGTH BIT(0)
519 #define CCS_R_FRAME_MARGIN_MAX_VALUE CCI_REG16(0x114e)
520 #define CCS_R_FRAME_MARGIN_MIN_VALUE CCI_REG8(0x1150)
521 #define CCS_R_GAIN_DELAY_TYPE CCI_REG8(0x1151)
522 #define CCS_GAIN_DELAY_TYPE_FIXED 0U
524 #define CCS_R_MIN_OP_SYS_CLK_DIV CCI_REG16(0x1160)
525 #define CCS_R_MAX_OP_SYS_CLK_DIV CCI_REG16(0x1162)
526 #define CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ (CCI_REG32(0x1164) | CCS_FL_FLOAT_IREAL)
527 #define CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ (CCI_REG32(0x1168) | CCS_FL_FLOAT_IREAL)
528 #define CCS_R_MIN_OP_PIX_CLK_DIV CCI_REG16(0x116c)
529 #define CCS_R_MAX_OP_PIX_CLK_DIV CCI_REG16(0x116e)
530 #define CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ (CCI_REG32(0x1170) | CCS_FL_FLOAT_IREAL)
531 #define CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ (CCI_REG32(0x1174) | CCS_FL_FLOAT_IREAL)
532 #define CCS_R_X_ADDR_MIN CCI_REG16(0x1180)
533 #define CCS_R_Y_ADDR_MIN CCI_REG16(0x1182)
534 #define CCS_R_X_ADDR_MAX CCI_REG16(0x1184)
535 #define CCS_R_Y_ADDR_MAX CCI_REG16(0x1186)
536 #define CCS_R_MIN_X_OUTPUT_SIZE CCI_REG16(0x1188)
537 #define CCS_R_MIN_Y_OUTPUT_SIZE CCI_REG16(0x118a)
538 #define CCS_R_MAX_X_OUTPUT_SIZE CCI_REG16(0x118c)
539 #define CCS_R_MAX_Y_OUTPUT_SIZE CCI_REG16(0x118e)
540 #define CCS_R_X_ADDR_START_DIV_CONSTANT CCI_REG8(0x1190)
541 #define CCS_R_Y_ADDR_START_DIV_CONSTANT CCI_REG8(0x1191)
542 #define CCS_R_X_ADDR_END_DIV_CONSTANT CCI_REG8(0x1192)
543 #define CCS_R_Y_ADDR_END_DIV_CONSTANT CCI_REG8(0x1193)
544 #define CCS_R_X_SIZE_DIV CCI_REG8(0x1194)
545 #define CCS_R_Y_SIZE_DIV CCI_REG8(0x1195)
546 #define CCS_R_X_OUTPUT_DIV CCI_REG8(0x1196)
547 #define CCS_R_Y_OUTPUT_DIV CCI_REG8(0x1197)
548 #define CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT CCI_REG8(0x1198)
549 #define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_PIX_ADDR BIT(0)
553 #define CCS_R_MIN_OP_PRE_PLL_CLK_DIV CCI_REG16(0x11a0)
554 #define CCS_R_MAX_OP_PRE_PLL_CLK_DIV CCI_REG16(0x11a2)
555 #define CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x11a4) | CCS_FL_FLOAT_IREAL)
556 #define CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x11a8) | CCS_FL_FLOAT_IREAL)
557 #define CCS_R_MIN_OP_PLL_MULTIPLIER CCI_REG16(0x11ac)
558 #define CCS_R_MAX_OP_PLL_MULTIPLIER CCI_REG16(0x11ae)
559 #define CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x11b0) | CCS_FL_FLOAT_IREAL)
560 #define CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x11b4) | CCS_FL_FLOAT_IREAL)
561 #define CCS_R_CLOCK_TREE_PLL_CAPABILITY CCI_REG8(0x11b8)
562 #define CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL BIT(0)
566 #define CCS_R_CLOCK_CAPA_TYPE_CAPABILITY CCI_REG8(0x11b9)
567 #define CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL BIT(0)
568 #define CCS_R_MIN_EVEN_INC CCI_REG16(0x11c0)
569 #define CCS_R_MIN_ODD_INC CCI_REG16(0x11c2)
570 #define CCS_R_MAX_EVEN_INC CCI_REG16(0x11c4)
571 #define CCS_R_MAX_ODD_INC CCI_REG16(0x11c6)
572 #define CCS_R_AUX_SUBSAMP_CAPABILITY CCI_REG8(0x11c8)
574 #define CCS_R_AUX_SUBSAMP_MONO_CAPABILITY CCI_REG8(0x11c9)
576 #define CCS_R_MONOCHROME_CAPABILITY CCI_REG8(0x11ca)
577 #define CCS_MONOCHROME_CAPABILITY_INC_ODD 0U
579 #define CCS_R_PIXEL_READOUT_CAPABILITY CCI_REG8(0x11cb)
580 #define CCS_PIXEL_READOUT_CAPABILITY_BAYER 0U
583 #define CCS_R_MIN_EVEN_INC_MONO CCI_REG16(0x11cc)
584 #define CCS_R_MAX_EVEN_INC_MONO CCI_REG16(0x11ce)
585 #define CCS_R_MIN_ODD_INC_MONO CCI_REG16(0x11d0)
586 #define CCS_R_MAX_ODD_INC_MONO CCI_REG16(0x11d2)
587 #define CCS_R_MIN_EVEN_INC_BC2 CCI_REG16(0x11d4)
588 #define CCS_R_MAX_EVEN_INC_BC2 CCI_REG16(0x11d6)
589 #define CCS_R_MIN_ODD_INC_BC2 CCI_REG16(0x11d8)
590 #define CCS_R_MAX_ODD_INC_BC2 CCI_REG16(0x11da)
591 #define CCS_R_MIN_EVEN_INC_MONO_BC2 CCI_REG16(0x11dc)
592 #define CCS_R_MAX_EVEN_INC_MONO_BC2 CCI_REG16(0x11de)
593 #define CCS_R_MIN_ODD_INC_MONO_BC2 CCI_REG16(0x11f0)
594 #define CCS_R_MAX_ODD_INC_MONO_BC2 CCI_REG16(0x11f2)
595 #define CCS_R_SCALING_CAPABILITY CCI_REG16(0x1200)
596 #define CCS_SCALING_CAPABILITY_NONE 0U
599 #define CCS_R_SCALER_M_MIN CCI_REG16(0x1204)
600 #define CCS_R_SCALER_M_MAX CCI_REG16(0x1206)
601 #define CCS_R_SCALER_N_MIN CCI_REG16(0x1208)
602 #define CCS_R_SCALER_N_MAX CCI_REG16(0x120a)
603 #define CCS_R_DIGITAL_CROP_CAPABILITY CCI_REG8(0x120e)
604 #define CCS_DIGITAL_CROP_CAPABILITY_NONE 0U
606 #define CCS_R_HDR_CAPABILITY_1 CCI_REG8(0x1210)
607 #define CCS_HDR_CAPABILITY_1_2X2_BINNING BIT(0)
614 #define CCS_R_MIN_HDR_BIT_DEPTH CCI_REG8(0x1211)
615 #define CCS_R_HDR_RESOLUTION_SUB_TYPES CCI_REG8(0x1212)
616 #define CCS_R_HDR_RESOLUTION_SUB_TYPE(n) CCI_REG8(0x1213 + (n))
617 #define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MIN_N 0U
619 #define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_SHIFT 0U
620 #define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_MASK 0xf
622 #define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_MASK 0xf0
623 #define CCS_R_HDR_CAPABILITY_2 CCI_REG8(0x121b)
624 #define CCS_HDR_CAPABILITY_2_COMBINED_DIGITAL_GAIN BIT(0)
628 #define CCS_R_MAX_HDR_BIT_DEPTH CCI_REG8(0x121c)
629 #define CCS_R_USL_SUPPORT_CAPABILITY CCI_REG8(0x1230)
630 #define CCS_USL_SUPPORT_CAPABILITY_CLOCK_TREE BIT(0)
633 #define CCS_R_USL_CLOCK_MODE_D_CAPABILITY CCI_REG8(0x1231)
634 #define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_STANDBY BIT(0)
640 #define CCS_R_MIN_OP_SYS_CLK_DIV_REV CCI_REG8(0x1234)
641 #define CCS_R_MAX_OP_SYS_CLK_DIV_REV CCI_REG8(0x1236)
642 #define CCS_R_MIN_OP_PIX_CLK_DIV_REV CCI_REG8(0x1238)
643 #define CCS_R_MAX_OP_PIX_CLK_DIV_REV CCI_REG8(0x123a)
644 #define CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ (CCI_REG32(0x123c) | CCS_FL_FLOAT_IREAL)
645 #define CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ (CCI_REG32(0x1240) | CCS_FL_FLOAT_IREAL)
646 #define CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ (CCI_REG32(0x1244) | CCS_FL_FLOAT_IREAL)
647 #define CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ (CCI_REG32(0x1248) | CCS_FL_FLOAT_IREAL)
648 #define CCS_R_MAX_BITRATE_REV_D_MODE_MBPS (CCI_REG32(0x124c) | CCS_FL_IREAL)
649 #define CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS (CCI_REG32(0x1250) | CCS_FL_IREAL)
650 #define CCS_R_COMPRESSION_CAPABILITY CCI_REG8(0x1300)
651 #define CCS_COMPRESSION_CAPABILITY_DPCM_PCM_SIMPLE BIT(0)
652 #define CCS_R_TEST_MODE_CAPABILITY CCI_REG16(0x1310)
653 #define CCS_TEST_MODE_CAPABILITY_SOLID_COLOR BIT(0)
658 #define CCS_R_PN9_DATA_FORMAT1 CCI_REG8(0x1312)
659 #define CCS_R_PN9_DATA_FORMAT2 CCI_REG8(0x1313)
660 #define CCS_R_PN9_DATA_FORMAT3 CCI_REG8(0x1314)
661 #define CCS_R_PN9_DATA_FORMAT4 CCI_REG8(0x1315)
662 #define CCS_R_PN9_MISC_CAPABILITY CCI_REG8(0x1316)
663 #define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_SHIFT 0U
664 #define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_MASK 0x7
666 #define CCS_R_TEST_PATTERN_CAPABILITY CCI_REG8(0x1317)
668 #define CCS_R_PATTERN_SIZE_DIV_M1 CCI_REG8(0x1318)
669 #define CCS_R_FIFO_SUPPORT_CAPABILITY CCI_REG8(0x1502)
670 #define CCS_FIFO_SUPPORT_CAPABILITY_NONE 0U
673 #define CCS_R_PHY_CTRL_CAPABILITY CCI_REG8(0x1600)
674 #define CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL BIT(0)
682 #define CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY CCI_REG8(0x1601)
683 #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
691 #define CCS_R_CSI_SIGNALING_MODE_CAPABILITY CCI_REG8(0x1602)
694 #define CCS_R_FAST_STANDBY_CAPABILITY CCI_REG8(0x1603)
695 #define CCS_FAST_STANDBY_CAPABILITY_NO_FRAME_TRUNCATION 0U
697 #define CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY CCI_REG8(0x1604)
698 #define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_CCI_ADDR_CHANGE BIT(0)
701 #define CCS_R_DATA_TYPE_CAPABILITY CCI_REG8(0x1605)
702 #define CCS_DATA_TYPE_CAPABILITY_DPCM_PROGRAMMABLE BIT(0)
706 #define CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY CCI_REG8(0x1606)
707 #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
715 #define CCS_R_EMB_DATA_CAPABILITY CCI_REG8(0x1607)
716 #define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW16 BIT(0)
722 #define CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(n) (CCI_REG32(0x1608 + ((n) < 4 ? (n) * 4 : 0x…
723 #define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MIN_N 0U
725 #define CCS_R_TEMP_SENSOR_CAPABILITY CCI_REG8(0x1618)
726 #define CCS_TEMP_SENSOR_CAPABILITY_SUPPORTED BIT(0)
729 #define CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(n) (CCI_REG32(0x161a + ((n) < 4 ? (n) * 4 : 0x…
730 #define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MIN_N 0U
732 #define CCS_R_DPHY_EQUALIZATION_CAPABILITY CCI_REG8(0x162b)
733 #define CCS_DPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
736 #define CCS_R_CPHY_EQUALIZATION_CAPABILITY CCI_REG8(0x162c)
737 #define CCS_CPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
738 #define CCS_R_DPHY_PREAMBLE_CAPABILITY CCI_REG8(0x162d)
739 #define CCS_DPHY_PREAMBLE_CAPABILITY_PREAMBLE_SEQ_CTRL BIT(0)
740 #define CCS_R_DPHY_SSC_CAPABILITY CCI_REG8(0x162e)
741 #define CCS_DPHY_SSC_CAPABILITY_SUPPORTED BIT(0)
742 #define CCS_R_CPHY_CALIBRATION_CAPABILITY CCI_REG8(0x162f)
743 #define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
748 #define CCS_R_DPHY_CALIBRATION_CAPABILITY CCI_REG8(0x1630)
749 #define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
752 #define CCS_R_PHY_CTRL_CAPABILITY_2 CCI_REG8(0x1631)
753 #define CCS_PHY_CTRL_CAPABILITY_2_TGR_LENGTH BIT(0)
761 #define CCS_R_LRTE_CPHY_CAPABILITY CCI_REG8(0x1632)
762 #define CCS_LRTE_CPHY_CAPABILITY_PDQ_SHORT BIT(0)
767 #define CCS_R_LRTE_DPHY_CAPABILITY CCI_REG8(0x1633)
768 #define CCS_LRTE_DPHY_CAPABILITY_PDQ_SHORT_OPT1 BIT(0)
776 #define CCS_R_ALPS_CAPABILITY_DPHY CCI_REG8(0x1634)
777 #define CCS_ALPS_CAPABILITY_DPHY_LVLP_NOT_SUPPORTED 0U
780 #define CCS_R_ALPS_CAPABILITY_CPHY CCI_REG8(0x1635)
781 #define CCS_ALPS_CAPABILITY_CPHY_LVLP_NOT_SUPPORTED 0U
784 #define CCS_ALPS_CAPABILITY_CPHY_ALP_NOT_SUPPORTED 0xc
785 #define CCS_ALPS_CAPABILITY_CPHY_ALP_SUPPORTED 0xd
786 #define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_ALP 0xe
787 #define CCS_R_SCRAMBLING_CAPABILITY CCI_REG8(0x1636)
788 #define CCS_SCRAMBLING_CAPABILITY_SCRAMBLING_SUPPORTED BIT(0)
790 #define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_MASK 0x6
791 #define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_1 0U
794 #define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_MASK 0x38
795 #define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_0 0U
799 #define CCS_R_DPHY_MANUAL_CONSTANT CCI_REG8(0x1637)
800 #define CCS_R_CPHY_MANUAL_CONSTANT CCI_REG8(0x1638)
801 #define CCS_R_CSI2_INTERFACE_CAPABILITY_MISC CCI_REG8(0x1639)
802 #define CCS_CSI2_INTERFACE_CAPABILITY_MISC_EOTP_SHORT_PKT_OPT2 BIT(0)
803 #define CCS_R_PHY_CTRL_CAPABILITY_3 CCI_REG8(0x165c)
804 #define CCS_PHY_CTRL_CAPABILITY_3_DPHY_TIMING_NOT_MULTIPLE BIT(0)
811 #define CCS_R_DPHY_SF CCI_REG8(0x165d)
812 #define CCS_R_CPHY_SF CCI_REG8(0x165e)
813 #define CCS_CPHY_SF_TWAKEUP_SHIFT 0U
814 #define CCS_CPHY_SF_TWAKEUP_MASK 0xf
816 #define CCS_CPHY_SF_TINIT_MASK 0xf0
817 #define CCS_R_DPHY_LIMITS_1 CCI_REG8(0x165f)
818 #define CCS_DPHY_LIMITS_1_THS_PREPARE_SHIFT 0U
819 #define CCS_DPHY_LIMITS_1_THS_PREPARE_MASK 0xf
821 #define CCS_DPHY_LIMITS_1_THS_ZERO_MASK 0xf0
822 #define CCS_R_DPHY_LIMITS_2 CCI_REG8(0x1660)
823 #define CCS_DPHY_LIMITS_2_THS_TRAIL_SHIFT 0U
824 #define CCS_DPHY_LIMITS_2_THS_TRAIL_MASK 0xf
826 #define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_MASK 0xf0
827 #define CCS_R_DPHY_LIMITS_3 CCI_REG8(0x1661)
828 #define CCS_DPHY_LIMITS_3_TCLK_PREPARE_SHIFT 0U
829 #define CCS_DPHY_LIMITS_3_TCLK_PREPARE_MASK 0xf
831 #define CCS_DPHY_LIMITS_3_TCLK_ZERO_MASK 0xf0
832 #define CCS_R_DPHY_LIMITS_4 CCI_REG8(0x1662)
833 #define CCS_DPHY_LIMITS_4_TCLK_POST_SHIFT 0U
834 #define CCS_DPHY_LIMITS_4_TCLK_POST_MASK 0xf
836 #define CCS_DPHY_LIMITS_4_TLPX_MASK 0xf0
837 #define CCS_R_DPHY_LIMITS_5 CCI_REG8(0x1663)
838 #define CCS_DPHY_LIMITS_5_THS_EXIT_SHIFT 0U
839 #define CCS_DPHY_LIMITS_5_THS_EXIT_MASK 0xf
841 #define CCS_DPHY_LIMITS_5_TWAKEUP_MASK 0xf0
842 #define CCS_R_DPHY_LIMITS_6 CCI_REG8(0x1664)
843 #define CCS_DPHY_LIMITS_6_TINIT_SHIFT 0U
844 #define CCS_DPHY_LIMITS_6_TINIT_MASK 0xf
845 #define CCS_R_CPHY_LIMITS_1 CCI_REG8(0x1665)
846 #define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_SHIFT 0U
847 #define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_MASK 0xf
849 #define CCS_CPHY_LIMITS_1_T3_LPX_MAX_MASK 0xf0
850 #define CCS_R_CPHY_LIMITS_2 CCI_REG8(0x1666)
851 #define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_SHIFT 0U
852 #define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_MASK 0xf
854 #define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_MASK 0xf0
855 #define CCS_R_CPHY_LIMITS_3 CCI_REG8(0x1667)
856 #define CCS_CPHY_LIMITS_3_TINIT_MAX_SHIFT 0U
857 #define CCS_CPHY_LIMITS_3_TINIT_MAX_MASK 0xf
858 #define CCS_R_MIN_FRAME_LENGTH_LINES_BIN CCI_REG16(0x1700)
859 #define CCS_R_MAX_FRAME_LENGTH_LINES_BIN CCI_REG16(0x1702)
860 #define CCS_R_MIN_LINE_LENGTH_PCK_BIN CCI_REG16(0x1704)
861 #define CCS_R_MAX_LINE_LENGTH_PCK_BIN CCI_REG16(0x1706)
862 #define CCS_R_MIN_LINE_BLANKING_PCK_BIN CCI_REG16(0x1708)
863 #define CCS_R_FINE_INTEGRATION_TIME_MIN_BIN CCI_REG16(0x170a)
864 #define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN CCI_REG16(0x170c)
865 #define CCS_R_BINNING_CAPABILITY CCI_REG8(0x1710)
866 #define CCS_BINNING_CAPABILITY_UNSUPPORTED 0U
869 #define CCS_R_BINNING_WEIGHTING_CAPABILITY CCI_REG8(0x1711)
870 #define CCS_BINNING_WEIGHTING_CAPABILITY_AVERAGED BIT(0)
874 #define CCS_R_BINNING_SUB_TYPES CCI_REG8(0x1712)
875 #define CCS_R_BINNING_SUB_TYPE(n) CCI_REG8(0x1713 + (n))
876 #define CCS_LIM_BINNING_SUB_TYPE_MIN_N 0U
878 #define CCS_BINNING_SUB_TYPE_ROW_SHIFT 0U
879 #define CCS_BINNING_SUB_TYPE_ROW_MASK 0xf
881 #define CCS_BINNING_SUB_TYPE_COLUMN_MASK 0xf0
882 #define CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY CCI_REG8(0x1771)
883 #define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_AVERAGED BIT(0)
887 #define CCS_R_BINNING_SUB_TYPES_MONO CCI_REG8(0x1772)
888 #define CCS_R_BINNING_SUB_TYPE_MONO(n) CCI_REG8(0x1773 + (n))
889 #define CCS_LIM_BINNING_SUB_TYPE_MONO_MIN_N 0U
891 #define CCS_R_DATA_TRANSFER_IF_CAPABILITY CCI_REG8(0x1800)
892 #define CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
894 #define CCS_R_SHADING_CORRECTION_CAPABILITY CCI_REG8(0x1900)
895 #define CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING BIT(0)
897 #define CCS_R_GREEN_IMBALANCE_CAPABILITY CCI_REG8(0x1901)
898 #define CCS_GREEN_IMBALANCE_CAPABILITY_SUPPORTED BIT(0)
899 #define CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY CCI_REG8(0x1903)
900 #define CCS_R_DEFECT_CORRECTION_CAPABILITY CCI_REG16(0x1904)
901 #define CCS_DEFECT_CORRECTION_CAPABILITY_MAPPED_DEFECT BIT(0)
905 #define CCS_R_DEFECT_CORRECTION_CAPABILITY_2 CCI_REG16(0x1906)
907 #define CCS_R_NF_CAPABILITY CCI_REG8(0x1908)
908 #define CCS_NF_CAPABILITY_LUMA BIT(0)
911 #define CCS_R_OB_READOUT_CAPABILITY CCI_REG8(0x1980)
912 #define CCS_OB_READOUT_CAPABILITY_CONTROLLABLE_READOUT BIT(0)
917 #define CCS_R_COLOR_FEEDBACK_CAPABILITY CCI_REG8(0x1987)
918 #define CCS_COLOR_FEEDBACK_CAPABILITY_KELVIN BIT(0)
920 #define CCS_R_CFA_PATTERN_CAPABILITY CCI_REG8(0x1990)
921 #define CCS_CFA_PATTERN_CAPABILITY_BAYER 0U
925 #define CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY CCI_REG8(0x1991)
926 #define CCS_CFA_PATTERN_CONVERSION_CAPABILITY_BAYER BIT(0)
927 #define CCS_R_FLASH_MODE_CAPABILITY CCI_REG8(0x1a02)
928 #define CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
929 #define CCS_R_SA_STROBE_MODE_CAPABILITY CCI_REG8(0x1a03)
930 #define CCS_SA_STROBE_MODE_CAPABILITY_FIXED_WIDTH BIT(0)
932 #define CCS_R_RESET_MAX_DELAY CCI_REG8(0x1a10)
933 #define CCS_R_RESET_MIN_TIME CCI_REG8(0x1a11)
934 #define CCS_R_PDAF_CAPABILITY_1 CCI_REG8(0x1b80)
935 #define CCS_PDAF_CAPABILITY_1_SUPPORTED BIT(0)
943 #define CCS_R_PDAF_CAPABILITY_2 CCI_REG8(0x1b81)
944 #define CCS_PDAF_CAPABILITY_2_ROI BIT(0)
947 #define CCS_R_BRACKETING_LUT_CAPABILITY_1 CCI_REG8(0x1c00)
948 #define CCS_BRACKETING_LUT_CAPABILITY_1_COARSE_INTEGRATION BIT(0)
953 #define CCS_R_BRACKETING_LUT_CAPABILITY_2 CCI_REG8(0x1c01)
954 #define CCS_BRACKETING_LUT_CAPABILITY_2_SINGLE_BRACKETING_MODE BIT(0)
956 #define CCS_R_BRACKETING_LUT_SIZE CCI_REG8(0x1c02)