Lines Matching +full:clock +full:- +full:lanes

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
37  * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39  * A single branch front-end of the CCS PLL tree.
41  * @pre_pll_clk_div: Pre-PLL clock divisor
43  * @pll_ip_clk_freq_hz: PLL input clock frequency
44  * @pll_op_clk_freq_hz: PLL output clock frequency
54  * struct ccs_pll_branch_bk - CCS PLL configuration (back)
56  * A single branch back-end of the CCS PLL tree.
58  * @sys_clk_div: System clock divider
59  * @pix_clk_div: Pixel clock divider
60  * @sys_clk_freq_hz: System clock frequency
61  * @pix_clk_freq_hz: Pixel clock frequency
71  * struct ccs_pll - Full CCS PLL configuration
76  * @op_lanes: Number of operational lanes (input)
77  * @vt_lanes: Number of video timing lanes (input)
78  * @csi2: CSI-2 related parameters
79  * @csi2.lanes: The number of the CSI-2 data lanes (input)
88  * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock
90  * @vt_fr: Video timing front-end configuration (output)
91  * @vt_bk: Video timing back-end configuration (output)
92  * @op_fr: Operational timing front-end configuration (output)
93  * @op_bk: Operational timing back-end configuration (output)
104 		u8 lanes;  member
127  * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits
129  * @min_pre_pll_clk_div: Minimum pre-PLL clock divider
130  * @max_pre_pll_clk_div: Maximum pre-PLL clock divider
131  * @min_pll_ip_clk_freq_hz: Minimum PLL input clock frequency
132  * @max_pll_ip_clk_freq_hz: Maximum PLL input clock frequency
135  * @min_pll_op_clk_freq_hz: Minimum PLL output clock frequency
136  * @max_pll_op_clk_freq_hz: Maximum PLL output clock frequency
150  * struct ccs_pll_branch_limits_bk - CCS PLL back-end limits
152  * @min_sys_clk_div: Minimum system clock divider
153  * @max_sys_clk_div: Maximum system clock divider
154  * @min_sys_clk_freq_hz: Minimum system clock frequency
155  * @max_sys_clk_freq_hz: Maximum system clock frequency
156  * @min_pix_clk_div: Minimum pixel clock divider
157  * @max_pix_clk_div: Maximum pixel clock divider
158  * @min_pix_clk_freq_hz: Minimum pixel clock frequency
159  * @max_pix_clk_freq_hz: Maximum pixel clock frequency
173  * struct ccs_pll_limits - CCS PLL limits
175  * @min_ext_clk_freq_hz: Minimum external clock frequency
176  * @max_ext_clk_freq_hz: Maximum external clock frequency
177  * @vt_fr: Video timing front-end limits
178  * @vt_bk: Video timing back-end limits
179  * @op_fr: Operational timing front-end limits
180  * @op_bk: Operational timing back-end limits
202  * ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters