Lines Matching +full:0 +full:x8ff
13 * ADV7842 I2C Register Maps, Rev. 0, November 2010
16 * Decoder and Digitizer , Rev. 0, January 2011
38 MODULE_PARM_DESC(debug, "debug level (0-2)");
50 #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)
51 #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)
52 #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)
54 #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)
61 #define ADV7842_OP_CH_SEL_GBR (0 << 5)
68 #define ADV7842_OP_SWAP_CB_CR (1 << 0)
156 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) in adv7842_check_dv_timings()
157 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false)) in adv7842_check_dv_timings()
170 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
171 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
172 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
173 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
174 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
175 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
176 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
177 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
178 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
185 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
186 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
187 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
188 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
189 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
190 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
191 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
192 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
193 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
194 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
195 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
196 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
197 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
198 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
199 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
200 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
201 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
202 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
203 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
204 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
206 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
207 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
213 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
214 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
215 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
216 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
217 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
218 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
219 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
220 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
221 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
227 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
228 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
229 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
230 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
231 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
232 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
233 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
234 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
235 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
236 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
237 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
238 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
239 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
240 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
241 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
294 for (i = 0; i < 3; i++) { in adv_smbus_read_byte_data()
297 if (ret >= 0) { in adv_smbus_read_byte_data()
315 for (i = 0; i < 3; i++) { in adv_smbus_write_byte_data()
323 if (err < 0) in adv_smbus_write_byte_data()
563 adv_smbus_write_byte_no_check(client, 0xff, 0x80); in main_reset()
618 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) { in adv7842_format_info()
646 .reserved = { 0 },
657 .reserved = { 0 },
676 u8 reg = io_read(sd, 0x6f); in adv7842_read_cable_det()
677 u16 val = 0; in adv7842_read_cable_det()
679 if (reg & 0x02) in adv7842_read_cable_det()
681 if (reg & 0x01) in adv7842_read_cable_det()
693 u8 mask = 0; in adv7842_delayed_work_enable_hotplug()
695 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n", in adv7842_delayed_work_enable_hotplug()
698 if (present & (0x04 << ADV7842_EDID_PORT_A)) in adv7842_delayed_work_enable_hotplug()
699 mask |= 0x20; in adv7842_delayed_work_enable_hotplug()
700 if (present & (0x04 << ADV7842_EDID_PORT_B)) in adv7842_delayed_work_enable_hotplug()
701 mask |= 0x10; in adv7842_delayed_work_enable_hotplug()
702 io_write_and_or(sd, 0x20, 0xcf, mask); in adv7842_delayed_work_enable_hotplug()
711 int err = 0; in edid_write_vga_segment()
717 return 0; in edid_write_vga_segment()
720 io_write_and_or(sd, 0x20, 0xcf, 0x00); in edid_write_vga_segment()
723 rep_write_and_or(sd, 0x7f, 0x7f, 0x00); in edid_write_vga_segment()
726 rep_write_and_or(sd, 0x77, 0xef, 0x10); in edid_write_vga_segment()
728 for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX) in edid_write_vga_segment()
738 rep_write_and_or(sd, 0x7f, 0x7f, 0x80); in edid_write_vga_segment()
740 for (i = 0; i < 1000; i++) { in edid_write_vga_segment()
741 if (rep_read(sd, 0x79) & 0x20) in edid_write_vga_segment()
753 return 0; in edid_write_vga_segment()
764 int err = 0; in edid_write_hdmi_segment()
771 io_write_and_or(sd, 0x20, 0xcf, 0x00); in edid_write_hdmi_segment()
774 rep_write_and_or(sd, 0x77, 0xf3, 0x00); in edid_write_hdmi_segment()
778 return 0; in edid_write_hdmi_segment()
796 for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX) { in edid_write_hdmi_segment()
798 if (i % 256 == 0) in edid_write_hdmi_segment()
799 rep_write_and_or(sd, 0x77, 0xef, i >= 256 ? 0x10 : 0x00); in edid_write_hdmi_segment()
807 rep_write(sd, 0x72, pa >> 8); in edid_write_hdmi_segment()
808 rep_write(sd, 0x73, pa & 0xff); in edid_write_hdmi_segment()
810 rep_write(sd, 0x74, pa >> 8); in edid_write_hdmi_segment()
811 rep_write(sd, 0x75, pa & 0xff); in edid_write_hdmi_segment()
813 rep_write(sd, 0x76, spa_loc & 0xff); in edid_write_hdmi_segment()
814 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40); in edid_write_hdmi_segment()
819 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present); in edid_write_hdmi_segment()
821 for (i = 0; i < 1000; i++) { in edid_write_hdmi_segment()
822 if (rep_read(sd, 0x7d) & state->hdmi_edid.present) in edid_write_hdmi_segment()
836 return 0; in edid_write_hdmi_segment()
844 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); in adv7842_inv_register()
845 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); in adv7842_inv_register()
846 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); in adv7842_inv_register()
847 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); in adv7842_inv_register()
848 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); in adv7842_inv_register()
849 v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); in adv7842_inv_register()
850 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); in adv7842_inv_register()
851 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); in adv7842_inv_register()
852 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); in adv7842_inv_register()
853 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); in adv7842_inv_register()
854 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); in adv7842_inv_register()
855 v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); in adv7842_inv_register()
863 case 0: in adv7842_g_register()
864 reg->val = io_read(sd, reg->reg & 0xff); in adv7842_g_register()
867 reg->val = avlink_read(sd, reg->reg & 0xff); in adv7842_g_register()
870 reg->val = cec_read(sd, reg->reg & 0xff); in adv7842_g_register()
873 reg->val = infoframe_read(sd, reg->reg & 0xff); in adv7842_g_register()
876 reg->val = sdp_io_read(sd, reg->reg & 0xff); in adv7842_g_register()
879 reg->val = sdp_read(sd, reg->reg & 0xff); in adv7842_g_register()
882 reg->val = afe_read(sd, reg->reg & 0xff); in adv7842_g_register()
885 reg->val = rep_read(sd, reg->reg & 0xff); in adv7842_g_register()
888 reg->val = edid_read(sd, reg->reg & 0xff); in adv7842_g_register()
891 reg->val = hdmi_read(sd, reg->reg & 0xff); in adv7842_g_register()
893 case 0xa: in adv7842_g_register()
894 reg->val = cp_read(sd, reg->reg & 0xff); in adv7842_g_register()
896 case 0xb: in adv7842_g_register()
897 reg->val = vdp_read(sd, reg->reg & 0xff); in adv7842_g_register()
904 return 0; in adv7842_g_register()
910 u8 val = reg->val & 0xff; in adv7842_s_register()
913 case 0: in adv7842_s_register()
914 io_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
917 avlink_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
920 cec_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
923 infoframe_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
926 sdp_io_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
929 sdp_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
932 afe_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
935 rep_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
938 edid_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
941 hdmi_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
943 case 0xa: in adv7842_s_register()
944 cp_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
946 case 0xb: in adv7842_s_register()
947 vdp_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
954 return 0; in adv7842_s_register()
963 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det); in adv7842_s_detect_tx_5v_ctrl()
975 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { in find_and_set_predefined_video_timings()
980 io_write(sd, 0x00, predef_vid_timings[i].vid_std); in find_and_set_predefined_video_timings()
982 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode); in find_and_set_predefined_video_timings()
983 return 0; in find_and_set_predefined_video_timings()
998 io_write(sd, 0x16, 0x43); in configure_predefined_video_timings()
999 io_write(sd, 0x17, 0x5a); in configure_predefined_video_timings()
1001 cp_write_and_or(sd, 0x81, 0xef, 0x00); in configure_predefined_video_timings()
1002 cp_write(sd, 0x26, 0x00); in configure_predefined_video_timings()
1003 cp_write(sd, 0x27, 0x00); in configure_predefined_video_timings()
1004 cp_write(sd, 0x28, 0x00); in configure_predefined_video_timings()
1005 cp_write(sd, 0x29, 0x00); in configure_predefined_video_timings()
1006 cp_write(sd, 0x8f, 0x40); in configure_predefined_video_timings()
1007 cp_write(sd, 0x90, 0x00); in configure_predefined_video_timings()
1008 cp_write(sd, 0xa5, 0x00); in configure_predefined_video_timings()
1009 cp_write(sd, 0xa6, 0x00); in configure_predefined_video_timings()
1010 cp_write(sd, 0xa7, 0x00); in configure_predefined_video_timings()
1011 cp_write(sd, 0xab, 0x00); in configure_predefined_video_timings()
1012 cp_write(sd, 0xac, 0x00); in configure_predefined_video_timings()
1018 0x01, adv7842_prim_mode_comp, timings); in configure_predefined_video_timings()
1021 0x02, adv7842_prim_mode_gr, timings); in configure_predefined_video_timings()
1025 0x05, adv7842_prim_mode_hdmi_comp, timings); in configure_predefined_video_timings()
1028 0x06, adv7842_prim_mode_hdmi_gr, timings); in configure_predefined_video_timings()
1052 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? in configure_custom_video_timings()
1053 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; in configure_custom_video_timings()
1055 0xc0 | ((width >> 8) & 0x1f), in configure_custom_video_timings()
1056 width & 0xff in configure_custom_video_timings()
1065 io_write(sd, 0x00, 0x07); /* video std */ in configure_custom_video_timings()
1066 io_write(sd, 0x01, 0x02); /* prim mode */ in configure_custom_video_timings()
1068 cp_write_and_or(sd, 0x81, 0xef, 0x10); in configure_custom_video_timings()
1072 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ in configure_custom_video_timings()
1073 if (i2c_smbus_write_i2c_block_data(client, 0x16, 2, pll)) { in configure_custom_video_timings()
1074 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); in configure_custom_video_timings()
1079 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf); in configure_custom_video_timings()
1080 cp_write(sd, 0x27, (cp_start_sav & 0xff)); in configure_custom_video_timings()
1081 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf); in configure_custom_video_timings()
1082 cp_write(sd, 0x29, (cp_start_eav & 0xff)); in configure_custom_video_timings()
1085 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); in configure_custom_video_timings()
1086 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | in configure_custom_video_timings()
1087 ((cp_end_vbi >> 8) & 0xf)); in configure_custom_video_timings()
1088 cp_write(sd, 0xa7, cp_end_vbi & 0xff); in configure_custom_video_timings()
1093 io_write(sd, 0x00, 0x02); /* video std */ in configure_custom_video_timings()
1094 io_write(sd, 0x01, 0x06); /* prim mode */ in configure_custom_video_timings()
1102 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); in configure_custom_video_timings()
1103 cp_write(sd, 0x90, ch1_fr_ll & 0xff); in configure_custom_video_timings()
1104 cp_write(sd, 0xab, (height >> 4) & 0xff); in configure_custom_video_timings()
1105 cp_write(sd, 0xac, (height & 0x0f) << 4); in configure_custom_video_timings()
1114 offset_a = 0x3ff; in adv7842_set_offset()
1115 offset_b = 0x3ff; in adv7842_set_offset()
1116 offset_c = 0x3ff; in adv7842_set_offset()
1119 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", in adv7842_set_offset()
1123 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); in adv7842_set_offset()
1124 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); in adv7842_set_offset()
1125 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); in adv7842_set_offset()
1126 offset_buf[3] = offset_c & 0x0ff; in adv7842_set_offset()
1129 if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf)) in adv7842_set_offset()
1130 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); in adv7842_set_offset()
1141 gain_man = 0; in adv7842_set_gain()
1142 agc_mode_man = 0; in adv7842_set_gain()
1143 gain_a = 0x100; in adv7842_set_gain()
1144 gain_b = 0x100; in adv7842_set_gain()
1145 gain_c = 0x100; in adv7842_set_gain()
1148 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", in adv7842_set_gain()
1152 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); in adv7842_set_gain()
1153 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); in adv7842_set_gain()
1154 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); in adv7842_set_gain()
1155 gain_buf[3] = ((gain_c & 0x0ff)); in adv7842_set_gain()
1158 if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf)) in adv7842_set_gain()
1159 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); in adv7842_set_gain()
1165 bool rgb_output = io_read(sd, 0x02) & 0x02; in set_rgb_quantization_range()
1166 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; in set_rgb_quantization_range()
1169 if (hdmi_signal && (io_read(sd, 0x60) & 1)) in set_rgb_quantization_range()
1170 y = infoframe_read(sd, 0x01) >> 5; in set_rgb_quantization_range()
1176 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0); in set_rgb_quantization_range()
1177 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0); in set_rgb_quantization_range()
1178 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4); in set_rgb_quantization_range()
1184 * Set RGB full range (0-255) */ in set_rgb_quantization_range()
1185 io_write_and_or(sd, 0x02, 0x0f, 0x10); in set_rgb_quantization_range()
1192 io_write_and_or(sd, 0x02, 0x0f, 0xf0); in set_rgb_quantization_range()
1199 io_write_and_or(sd, 0x02, 0x0f, 0xf0); in set_rgb_quantization_range()
1208 io_write_and_or(sd, 0x02, 0x0f, 0x00); in set_rgb_quantization_range()
1210 /* RGB full range (0-255) */ in set_rgb_quantization_range()
1211 io_write_and_or(sd, 0x02, 0x0f, 0x10); in set_rgb_quantization_range()
1214 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); in set_rgb_quantization_range()
1216 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); in set_rgb_quantization_range()
1217 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); in set_rgb_quantization_range()
1224 io_write_and_or(sd, 0x02, 0x0f, 0x20); in set_rgb_quantization_range()
1232 io_write_and_or(sd, 0x02, 0x0f, 0x00); in set_rgb_quantization_range()
1237 /* YCrCb full range (0-255) */ in set_rgb_quantization_range()
1238 io_write_and_or(sd, 0x02, 0x0f, 0x60); in set_rgb_quantization_range()
1245 /* RGB full range (0-255) */ in set_rgb_quantization_range()
1246 io_write_and_or(sd, 0x02, 0x0f, 0x10); in set_rgb_quantization_range()
1253 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); in set_rgb_quantization_range()
1255 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); in set_rgb_quantization_range()
1256 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); in set_rgb_quantization_range()
1274 cp_write(sd, 0x3c, ctrl->val); in adv7842_s_ctrl()
1275 sdp_write(sd, 0x14, ctrl->val); in adv7842_s_ctrl()
1276 /* ignore lsb sdp 0x17[3:2] */ in adv7842_s_ctrl()
1277 return 0; in adv7842_s_ctrl()
1279 cp_write(sd, 0x3a, ctrl->val); in adv7842_s_ctrl()
1280 sdp_write(sd, 0x13, ctrl->val); in adv7842_s_ctrl()
1281 /* ignore lsb sdp 0x17[1:0] */ in adv7842_s_ctrl()
1282 return 0; in adv7842_s_ctrl()
1284 cp_write(sd, 0x3b, ctrl->val); in adv7842_s_ctrl()
1285 sdp_write(sd, 0x15, ctrl->val); in adv7842_s_ctrl()
1286 /* ignore lsb sdp 0x17[5:4] */ in adv7842_s_ctrl()
1287 return 0; in adv7842_s_ctrl()
1289 cp_write(sd, 0x3d, ctrl->val); in adv7842_s_ctrl()
1290 sdp_write(sd, 0x16, ctrl->val); in adv7842_s_ctrl()
1291 /* ignore lsb sdp 0x17[7:6] */ in adv7842_s_ctrl()
1292 return 0; in adv7842_s_ctrl()
1295 afe_write(sd, 0xc8, ctrl->val); in adv7842_s_ctrl()
1296 return 0; in adv7842_s_ctrl()
1298 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); in adv7842_s_ctrl()
1299 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); in adv7842_s_ctrl()
1300 return 0; in adv7842_s_ctrl()
1302 u8 R = (ctrl->val & 0xff0000) >> 16; in adv7842_s_ctrl()
1303 u8 G = (ctrl->val & 0x00ff00) >> 8; in adv7842_s_ctrl()
1304 u8 B = (ctrl->val & 0x0000ff); in adv7842_s_ctrl()
1323 cp_write(sd, 0xc1, R); in adv7842_s_ctrl()
1324 cp_write(sd, 0xc0, G); in adv7842_s_ctrl()
1325 cp_write(sd, 0xc2, B); in adv7842_s_ctrl()
1327 sdp_write(sd, 0xde, Y); in adv7842_s_ctrl()
1328 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f)); in adv7842_s_ctrl()
1329 return 0; in adv7842_s_ctrl()
1334 return 0; in adv7842_s_ctrl()
1345 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80)) in adv7842_g_volatile_ctrl()
1346 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; in adv7842_g_volatile_ctrl()
1347 return 0; in adv7842_g_volatile_ctrl()
1354 return io_read(sd, 0x0c) & 0x24; in no_power()
1359 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80); in no_cp_signal()
1364 return hdmi_read(sd, 0x05) & 0x80; in is_hdmi()
1371 *status = 0; in adv7842_g_input_status()
1373 if (io_read(sd, 0x0c) & 0x24) in adv7842_g_input_status()
1378 if (!(sdp_read(sd, 0x5A) & 0x01)) in adv7842_g_input_status()
1381 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n", in adv7842_g_input_status()
1383 return 0; in adv7842_g_input_status()
1386 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 || in adv7842_g_input_status()
1387 !(cp_read(sd, 0xb1) & 0x80)) in adv7842_g_input_status()
1391 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03)) in adv7842_g_input_status()
1394 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", in adv7842_g_input_status()
1397 return 0; in adv7842_g_input_status()
1415 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { in stdi2dv_timings()
1432 return 0; in stdi2dv_timings()
1436 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, in stdi2dv_timings()
1437 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | in stdi2dv_timings()
1438 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1440 return 0; in stdi2dv_timings()
1442 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | in stdi2dv_timings()
1443 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1446 return 0; in stdi2dv_timings()
1465 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); in read_stdi()
1466 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); in read_stdi()
1467 stdi->lcvs = cp_read(sd, 0xb3) >> 3; in read_stdi()
1469 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) { in read_stdi()
1470 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? in read_stdi()
1471 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); in read_stdi()
1472 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? in read_stdi()
1473 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); in read_stdi()
1478 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; in read_stdi()
1480 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { in read_stdi()
1491 return 0; in read_stdi()
1497 if (timings->pad != 0) in adv7842_enum_dv_timings()
1507 if (cap->pad != 0) in adv7842_dv_timings_cap()
1511 return 0; in adv7842_dv_timings_cap()
1530 struct stdi_readback stdi = { 0 }; in adv7842_query_dv_timings()
1534 if (pad != 0) in adv7842_query_dv_timings()
1537 memset(timings, 0, sizeof(struct v4l2_dv_timings)); in adv7842_query_dv_timings()
1559 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); in adv7842_query_dv_timings()
1560 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); in adv7842_query_dv_timings()
1561 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000; in adv7842_query_dv_timings()
1562 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813); in adv7842_query_dv_timings()
1565 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8); in adv7842_query_dv_timings()
1568 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + in adv7842_query_dv_timings()
1569 hdmi_read(sd, 0x21); in adv7842_query_dv_timings()
1570 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + in adv7842_query_dv_timings()
1571 hdmi_read(sd, 0x23); in adv7842_query_dv_timings()
1572 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + in adv7842_query_dv_timings()
1573 hdmi_read(sd, 0x25); in adv7842_query_dv_timings()
1574 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + in adv7842_query_dv_timings()
1575 hdmi_read(sd, 0x2b)) / 2; in adv7842_query_dv_timings()
1576 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + in adv7842_query_dv_timings()
1577 hdmi_read(sd, 0x2f)) / 2; in adv7842_query_dv_timings()
1578 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + in adv7842_query_dv_timings()
1579 hdmi_read(sd, 0x33)) / 2; in adv7842_query_dv_timings()
1580 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv7842_query_dv_timings()
1581 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); in adv7842_query_dv_timings()
1583 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + in adv7842_query_dv_timings()
1584 hdmi_read(sd, 0x0c); in adv7842_query_dv_timings()
1585 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + in adv7842_query_dv_timings()
1586 hdmi_read(sd, 0x2d)) / 2; in adv7842_query_dv_timings()
1587 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + in adv7842_query_dv_timings()
1588 hdmi_read(sd, 0x31)) / 2; in adv7842_query_dv_timings()
1589 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + in adv7842_query_dv_timings()
1590 hdmi_read(sd, 0x35)) / 2; in adv7842_query_dv_timings()
1592 bt->il_vfrontporch = 0; in adv7842_query_dv_timings()
1593 bt->il_vsync = 0; in adv7842_query_dv_timings()
1594 bt->il_vbackporch = 0; in adv7842_query_dv_timings()
1632 cp_write_and_or(sd, 0x86, 0xf9, 0x00); in adv7842_query_dv_timings()
1634 cp_write_and_or(sd, 0x86, 0xf9, 0x04); in adv7842_query_dv_timings()
1636 cp_write_and_or(sd, 0x86, 0xf9, 0x02); in adv7842_query_dv_timings()
1650 return 0; in adv7842_query_dv_timings()
1662 if (pad != 0) in adv7842_s_dv_timings()
1668 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { in adv7842_s_dv_timings()
1670 return 0; in adv7842_s_dv_timings()
1683 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00); in adv7842_s_dv_timings()
1699 return 0; in adv7842_s_dv_timings()
1707 if (pad != 0) in adv7842_g_dv_timings()
1713 return 0; in adv7842_g_dv_timings()
1725 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ in enable_input()
1728 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ in enable_input()
1729 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ in enable_input()
1730 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ in enable_input()
1741 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */ in disable_input()
1743 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ in disable_input()
1744 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ in disable_input()
1751 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); in sdp_csc_coeff()
1757 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); in sdp_csc_coeff()
1760 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); in sdp_csc_coeff()
1761 sdp_io_write(sd, 0xe1, c->A1); in sdp_csc_coeff()
1762 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); in sdp_csc_coeff()
1763 sdp_io_write(sd, 0xe3, c->A2); in sdp_csc_coeff()
1764 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); in sdp_csc_coeff()
1765 sdp_io_write(sd, 0xe5, c->A3); in sdp_csc_coeff()
1768 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); in sdp_csc_coeff()
1769 sdp_io_write(sd, 0xe7, c->A4); in sdp_csc_coeff()
1772 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); in sdp_csc_coeff()
1773 sdp_io_write(sd, 0xe9, c->B1); in sdp_csc_coeff()
1774 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); in sdp_csc_coeff()
1775 sdp_io_write(sd, 0xeb, c->B2); in sdp_csc_coeff()
1776 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); in sdp_csc_coeff()
1777 sdp_io_write(sd, 0xed, c->B3); in sdp_csc_coeff()
1780 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); in sdp_csc_coeff()
1781 sdp_io_write(sd, 0xef, c->B4); in sdp_csc_coeff()
1784 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); in sdp_csc_coeff()
1785 sdp_io_write(sd, 0xf1, c->C1); in sdp_csc_coeff()
1786 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); in sdp_csc_coeff()
1787 sdp_io_write(sd, 0xf3, c->C2); in sdp_csc_coeff()
1788 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); in sdp_csc_coeff()
1789 sdp_io_write(sd, 0xf5, c->C3); in sdp_csc_coeff()
1792 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); in sdp_csc_coeff()
1793 sdp_io_write(sd, 0xf7, c->C4); in sdp_csc_coeff()
1803 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */ in select_input()
1804 io_write(sd, 0x01, 0); /* prim mode */ in select_input()
1806 cp_write_and_or(sd, 0x81, 0xef, 0x10); in select_input()
1808 afe_write(sd, 0x00, 0x00); /* power up ADC */ in select_input()
1809 afe_write(sd, 0xc8, 0x00); /* phase control */ in select_input()
1811 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */ in select_input()
1812 /* script says register 0xde, which don't exist in manual */ in select_input()
1815 afe_write_and_or(sd, 0x02, 0x7f, 0x80); in select_input()
1817 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ in select_input()
1818 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ in select_input()
1820 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ in select_input()
1821 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ in select_input()
1823 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ in select_input()
1824 afe_write(sd, 0x12, 0x63); /* ADI recommend write */ in select_input()
1826 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ in select_input()
1827 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ in select_input()
1830 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */ in select_input()
1831 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */ in select_input()
1833 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */ in select_input()
1834 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */ in select_input()
1835 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */ in select_input()
1836 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */ in select_input()
1837 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */ in select_input()
1838 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */ in select_input()
1839 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ in select_input()
1842 sdp_write_and_or(sd, 0x12, 0xf6, 0x09); in select_input()
1849 afe_write_and_or(sd, 0x02, 0x7f, 0x00); in select_input()
1851 io_write(sd, 0x00, vid_std_select); /* video std */ in select_input()
1852 io_write(sd, 0x01, 0x02); /* prim mode */ in select_input()
1853 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs in select_input()
1856 afe_write(sd, 0x00, 0x00); /* power up ADC */ in select_input()
1857 afe_write(sd, 0xc8, 0x00); /* phase control */ in select_input()
1860 io_write_and_or(sd, 0x02, 0x0f, 0x60); in select_input()
1863 io_write_and_or(sd, 0x02, 0x0f, 0x10); in select_input()
1869 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ in select_input()
1870 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ in select_input()
1873 cp_write(sd, 0x73, 0x10); in select_input()
1874 cp_write(sd, 0x74, 0x04); in select_input()
1875 cp_write(sd, 0x75, 0x01); in select_input()
1876 cp_write(sd, 0x76, 0x00); in select_input()
1878 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ in select_input()
1879 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ in select_input()
1880 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ in select_input()
1885 afe_write_and_or(sd, 0x02, 0x7f, 0x00); in select_input()
1888 hdmi_write(sd, 0x00, 0x02); /* select port A */ in select_input()
1890 hdmi_write(sd, 0x00, 0x03); /* select port B */ in select_input()
1891 io_write(sd, 0x00, vid_std_select); /* video std */ in select_input()
1892 io_write(sd, 0x01, 5); /* prim mode */ in select_input()
1893 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs in select_input()
1899 hdmi_write(sd, 0xc0, 0x00); in select_input()
1900 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */ in select_input()
1901 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */ in select_input()
1902 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */ in select_input()
1903 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */ in select_input()
1904 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ in select_input()
1905 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ in select_input()
1906 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */ in select_input()
1907 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */ in select_input()
1908 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit, in select_input()
1910 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */ in select_input()
1911 hdmi_write(sd, 0x85, 0x1f); /* equaliser */ in select_input()
1912 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */ in select_input()
1913 hdmi_write(sd, 0x89, 0x04); /* equaliser */ in select_input()
1914 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */ in select_input()
1915 hdmi_write(sd, 0x93, 0x04); /* equaliser */ in select_input()
1916 hdmi_write(sd, 0x94, 0x1e); /* equaliser */ in select_input()
1917 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */ in select_input()
1918 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */ in select_input()
1919 hdmi_write(sd, 0x9d, 0x02); /* equaliser */ in select_input()
1921 afe_write(sd, 0x00, 0xff); /* power down ADC */ in select_input()
1922 afe_write(sd, 0xc8, 0x40); /* phase control */ in select_input()
1925 cp_write(sd, 0x73, 0x10); in select_input()
1926 cp_write(sd, 0x74, 0x04); in select_input()
1927 cp_write(sd, 0x75, 0x01); in select_input()
1928 cp_write(sd, 0x76, 0x00); in select_input()
1933 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ in select_input()
1934 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ in select_input()
1935 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ in select_input()
1938 cp_write(sd, 0xc3, 0x33); /* Component mode */ in select_input()
1941 io_write_and_or(sd, 0x02, 0x0f, 0xf0); in select_input()
1995 return 0; in adv7842_s_routing()
2005 return 0; in adv7842_enum_mbus_code()
2011 memset(format, 0, sizeof(*format)); in adv7842_fill_format()
2032 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
2064 io_write_clr_set(sd, 0x02, 0x02, in adv7842_setup_format()
2065 state->format->rgb_out ? ADV7842_RGB_OUT : 0); in adv7842_setup_format()
2066 io_write(sd, 0x03, state->format->op_format_sel | in adv7842_setup_format()
2068 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state)); in adv7842_setup_format()
2069 io_write_clr_set(sd, 0x05, 0x01, in adv7842_setup_format()
2070 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0); in adv7842_setup_format()
2085 if (!(sdp_read(sd, 0x5a) & 0x01)) in adv7842_get_format()
2095 return 0; in adv7842_get_format()
2109 return 0; in adv7842_get_format()
2142 return 0; in adv7842_set_format()
2149 io_write(sd, 0x46, 0x9c); in adv7842_irq_enable()
2151 io_write(sd, 0x5a, 0x10); in adv7842_irq_enable()
2153 io_write(sd, 0x73, 0x03); in adv7842_irq_enable()
2155 io_write(sd, 0x78, 0x03); in adv7842_irq_enable()
2157 io_write(sd, 0xa0, 0x09); in adv7842_irq_enable()
2159 io_write(sd, 0x69, 0x08); in adv7842_irq_enable()
2161 io_write(sd, 0x46, 0x0); in adv7842_irq_enable()
2162 io_write(sd, 0x5a, 0x0); in adv7842_irq_enable()
2163 io_write(sd, 0x73, 0x0); in adv7842_irq_enable()
2164 io_write(sd, 0x78, 0x0); in adv7842_irq_enable()
2165 io_write(sd, 0xa0, 0x0); in adv7842_irq_enable()
2166 io_write(sd, 0x69, 0x0); in adv7842_irq_enable()
2175 if ((cec_read(sd, 0x11) & 0x01) == 0) { in adv7842_cec_tx_raw_status()
2180 if (tx_raw_status & 0x02) { in adv7842_cec_tx_raw_status()
2184 1, 0, 0, 0); in adv7842_cec_tx_raw_status()
2187 if (tx_raw_status & 0x04) { in adv7842_cec_tx_raw_status()
2198 nack_cnt = cec_read(sd, 0x14) & 0xf; in adv7842_cec_tx_raw_status()
2201 low_drive_cnt = cec_read(sd, 0x14) >> 4; in adv7842_cec_tx_raw_status()
2205 0, nack_cnt, low_drive_cnt, 0); in adv7842_cec_tx_raw_status()
2208 if (tx_raw_status & 0x01) { in adv7842_cec_tx_raw_status()
2210 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); in adv7842_cec_tx_raw_status()
2220 cec_irq = io_read(sd, 0x93) & 0x0f; in adv7842_cec_isr()
2224 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq); in adv7842_cec_isr()
2226 if (cec_irq & 0x08) { in adv7842_cec_isr()
2230 msg.len = cec_read(sd, 0x25) & 0x1f; in adv7842_cec_isr()
2237 for (i = 0; i < msg.len; i++) in adv7842_cec_isr()
2238 msg.msg[i] = cec_read(sd, i + 0x15); in adv7842_cec_isr()
2239 cec_write(sd, 0x26, 0x01); /* re-enable rx */ in adv7842_cec_isr()
2244 io_write(sd, 0x94, cec_irq); in adv7842_cec_isr()
2256 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */ in adv7842_cec_adap_enable()
2257 cec_write(sd, 0x2c, 0x01); /* cec soft reset */ in adv7842_cec_adap_enable()
2258 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */ in adv7842_cec_adap_enable()
2264 io_write_clr_set(sd, 0x96, 0x0f, 0x0f); in adv7842_cec_adap_enable()
2265 cec_write(sd, 0x26, 0x01); /* enable rx */ in adv7842_cec_adap_enable()
2268 io_write_clr_set(sd, 0x96, 0x0f, 0x00); in adv7842_cec_adap_enable()
2270 cec_write_clr_set(sd, 0x27, 0x70, 0x00); in adv7842_cec_adap_enable()
2272 cec_write_clr_set(sd, 0x2a, 0x01, 0x00); in adv7842_cec_adap_enable()
2273 state->cec_valid_addrs = 0; in adv7842_cec_adap_enable()
2276 return 0; in adv7842_cec_adap_enable()
2286 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; in adv7842_cec_adap_log_addr()
2289 cec_write_clr_set(sd, 0x27, 0x70, 0); in adv7842_cec_adap_log_addr()
2290 state->cec_valid_addrs = 0; in adv7842_cec_adap_log_addr()
2291 return 0; in adv7842_cec_adap_log_addr()
2294 for (i = 0; i < ADV7842_MAX_ADDRS; i++) { in adv7842_cec_adap_log_addr()
2300 return 0; in adv7842_cec_adap_log_addr()
2311 case 0: in adv7842_cec_adap_log_addr()
2312 /* enable address mask 0 */ in adv7842_cec_adap_log_addr()
2313 cec_write_clr_set(sd, 0x27, 0x10, 0x10); in adv7842_cec_adap_log_addr()
2314 /* set address for mask 0 */ in adv7842_cec_adap_log_addr()
2315 cec_write_clr_set(sd, 0x28, 0x0f, addr); in adv7842_cec_adap_log_addr()
2319 cec_write_clr_set(sd, 0x27, 0x20, 0x20); in adv7842_cec_adap_log_addr()
2321 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4); in adv7842_cec_adap_log_addr()
2325 cec_write_clr_set(sd, 0x27, 0x40, 0x40); in adv7842_cec_adap_log_addr()
2327 cec_write_clr_set(sd, 0x29, 0x0f, addr); in adv7842_cec_adap_log_addr()
2330 return 0; in adv7842_cec_adap_log_addr()
2343 * at least once. It's not clear if a value of 0 is allowed, so in adv7842_cec_adap_transmit()
2346 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); in adv7842_cec_adap_transmit()
2354 for (i = 0; i < len; i++) in adv7842_cec_adap_transmit()
2358 cec_write(sd, 0x10, len); in adv7842_cec_adap_transmit()
2360 cec_write(sd, 0x11, 0x01); in adv7842_cec_adap_transmit()
2361 return 0; in adv7842_cec_adap_transmit()
2380 irq_status[0] = io_read(sd, 0x43); in adv7842_isr()
2381 irq_status[1] = io_read(sd, 0x57); in adv7842_isr()
2382 irq_status[2] = io_read(sd, 0x70); in adv7842_isr()
2383 irq_status[3] = io_read(sd, 0x75); in adv7842_isr()
2384 irq_status[4] = io_read(sd, 0x9d); in adv7842_isr()
2385 irq_status[5] = io_read(sd, 0x66); in adv7842_isr()
2388 if (irq_status[0]) in adv7842_isr()
2389 io_write(sd, 0x44, irq_status[0]); in adv7842_isr()
2391 io_write(sd, 0x58, irq_status[1]); in adv7842_isr()
2393 io_write(sd, 0x71, irq_status[2]); in adv7842_isr()
2395 io_write(sd, 0x76, irq_status[3]); in adv7842_isr()
2397 io_write(sd, 0x9e, irq_status[4]); in adv7842_isr()
2399 io_write(sd, 0x67, irq_status[5]); in adv7842_isr()
2404 irq_status[0], irq_status[1], irq_status[2], in adv7842_isr()
2408 fmt_change_cp = irq_status[0] & 0x9c; in adv7842_isr()
2412 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09); in adv7842_isr()
2414 fmt_change_sdp = 0; in adv7842_isr()
2418 fmt_change_digital = irq_status[3] & 0x03; in adv7842_isr()
2420 fmt_change_digital = 0; in adv7842_isr()
2425 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n", in adv7842_isr()
2434 if (irq_status[5] & 0x08) { in adv7842_isr()
2436 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI"); in adv7842_isr()
2448 if (irq_status[2] & 0x3) { in adv7842_isr()
2454 return 0; in adv7842_isr()
2460 u32 blocks = 0; in adv7842_get_edid()
2463 memset(edid->reserved, 0, sizeof(edid->reserved)); in adv7842_get_edid()
2468 if (state->hdmi_edid.present & (0x04 << edid->pad)) { in adv7842_get_edid()
2483 if (edid->start_block == 0 && edid->blocks == 0) { in adv7842_get_edid()
2485 return 0; in adv7842_get_edid()
2499 return 0; in adv7842_get_edid()
2503 * If the VGA_EDID_ENABLE bit is set (Repeater Map 0x7f, bit 7), then
2513 int err = 0; in adv7842_set_edid()
2515 memset(e->reserved, 0, sizeof(e->reserved)); in adv7842_set_edid()
2519 if (e->start_block != 0) in adv7842_set_edid()
2532 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15], in adv7842_set_edid()
2533 e->edid[0x16]); in adv7842_set_edid()
2537 memset(state->vga_edid.edid, 0, sizeof(state->vga_edid.edid)); in adv7842_set_edid()
2539 state->vga_edid.present = e->blocks ? 0x1 : 0x0; in adv7842_set_edid()
2546 memset(state->hdmi_edid.edid, 0, sizeof(state->hdmi_edid.edid)); in adv7842_set_edid()
2549 state->hdmi_edid.present |= 0x04 << e->pad; in adv7842_set_edid()
2552 state->hdmi_edid.present &= ~(0x04 << e->pad); in adv7842_set_edid()
2560 if (err < 0) in adv7842_set_edid()
2573 { "AVI", 0x01, 0xe0, 0x00 },
2574 { "Audio", 0x02, 0xe3, 0x1c },
2575 { "SDP", 0x04, 0xe6, 0x2a },
2576 { "Vendor", 0x10, 0xec, 0x54 }
2585 if (!(io_read(sd, 0x60) & cri->present_mask)) { in adv7842_read_infoframe_buf()
2591 for (i = 0; i < 3; i++) in adv7842_read_infoframe_buf()
2602 for (i = 0; i < len; i++) in adv7842_read_infoframe_buf()
2615 if (!(hdmi_read(sd, 0x05) & 0x80)) { in adv7842_log_infoframes()
2620 for (i = 0; i < ARRAY_SIZE(adv7842_cri); i++) { in adv7842_log_infoframes()
2622 if (len < 0) in adv7842_log_infoframes()
2625 if (hdmi_infoframe_unpack(&frame, buffer, len) < 0) in adv7842_log_infoframes()
2633 #if 0
2658 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01; in adv7842_sdp_log_status()
2661 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", in adv7842_sdp_log_status()
2662 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); in adv7842_sdp_log_status()
2665 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off"); in adv7842_sdp_log_status()
2684 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); in adv7842_sdp_log_status()
2686 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz"); in adv7842_sdp_log_status()
2688 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive"); in adv7842_sdp_log_status()
2690 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled"); in adv7842_sdp_log_status()
2692 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual"); in adv7842_sdp_log_status()
2694 return 0; in adv7842_sdp_log_status()
2702 u8 reg_io_0x02 = io_read(sd, 0x02); in adv7842_cp_log_status()
2703 u8 reg_io_0x21 = io_read(sd, 0x21); in adv7842_cp_log_status()
2704 u8 reg_rep_0x77 = rep_read(sd, 0x77); in adv7842_cp_log_status()
2705 u8 reg_rep_0x7d = rep_read(sd, 0x7d); in adv7842_cp_log_status()
2706 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; in adv7842_cp_log_status()
2707 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; in adv7842_cp_log_status()
2708 bool audio_mute = io_read(sd, 0x65) & 0x40; in adv7842_cp_log_status()
2717 "RGB limited range (16-235)", "RGB full range (0-255)", in adv7842_cp_log_status()
2720 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", in adv7842_cp_log_status()
2727 "RGB full range (0-255)", in adv7842_cp_log_status()
2741 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ? in adv7842_cp_log_status()
2743 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ? in adv7842_cp_log_status()
2746 reg_io_0x21 & 0x02 ? "enabled" : "disabled", in adv7842_cp_log_status()
2747 reg_io_0x21 & 0x01 ? "enabled" : "disabled"); in adv7842_cp_log_status()
2753 for (i = 0; i < ADV7842_MAX_ADDRS; i++) { in adv7842_cp_log_status()
2757 v4l2_info(sd, "CEC Logical Address: 0x%x\n", in adv7842_cp_log_status()
2765 io_read(sd, 0x6f) & 0x02 ? "true" : "false"); in adv7842_cp_log_status()
2767 (io_read(sd, 0x6a) & 0x02) ? "true" : "false"); in adv7842_cp_log_status()
2769 (io_read(sd, 0x6a) & 0x20) ? "true" : "false"); in adv7842_cp_log_status()
2772 io_read(sd, 0x6f) & 0x01 ? "true" : "false"); in adv7842_cp_log_status()
2774 (io_read(sd, 0x6a) & 0x01) ? "true" : "false"); in adv7842_cp_log_status()
2776 (io_read(sd, 0x6a) & 0x10) ? "true" : "false"); in adv7842_cp_log_status()
2779 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); in adv7842_cp_log_status()
2780 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", in adv7842_cp_log_status()
2781 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, in adv7842_cp_log_status()
2782 (io_read(sd, 0x01) & 0x70) >> 4); in adv7842_cp_log_status()
2788 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); in adv7842_cp_log_status()
2789 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); in adv7842_cp_log_status()
2790 u32 lcvs = cp_read(sd, 0xb3) >> 3; in adv7842_cp_log_status()
2791 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9); in adv7842_cp_log_status()
2792 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? in adv7842_cp_log_status()
2793 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); in adv7842_cp_log_status()
2794 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? in adv7842_cp_log_status()
2795 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); in adv7842_cp_log_status()
2799 (cp_read(sd, 0xb1) & 0x40) ? in adv7842_cp_log_status()
2803 if (adv7842_query_dv_timings(sd, 0, &timings)) in adv7842_cp_log_status()
2812 return 0; in adv7842_cp_log_status()
2820 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", in adv7842_cp_log_status()
2821 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? in adv7842_cp_log_status()
2822 "(16-235)" : "(0-255)", in adv7842_cp_log_status()
2823 (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); in adv7842_cp_log_status()
2825 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]); in adv7842_cp_log_status()
2828 return 0; in adv7842_cp_log_status()
2832 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); in adv7842_cp_log_status()
2834 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", in adv7842_cp_log_status()
2835 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); in adv7842_cp_log_status()
2837 return 0; in adv7842_cp_log_status()
2845 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); in adv7842_cp_log_status()
2847 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + in adv7842_cp_log_status()
2848 (hdmi_read(sd, 0x5c) << 8) + in adv7842_cp_log_status()
2849 (hdmi_read(sd, 0x5d) & 0xf0)); in adv7842_cp_log_status()
2850 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + in adv7842_cp_log_status()
2851 (hdmi_read(sd, 0x5e) << 8) + in adv7842_cp_log_status()
2852 hdmi_read(sd, 0x5f)); in adv7842_cp_log_status()
2854 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); in adv7842_cp_log_status()
2856 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]); in adv7842_cp_log_status()
2860 return 0; in adv7842_cp_log_status()
2881 if (!(sdp_read(sd, 0x5A) & 0x01)) { in adv7842_querystd()
2882 *std = 0; in adv7842_querystd()
2884 return 0; in adv7842_querystd()
2887 switch (sdp_read(sd, 0x52) & 0x0f) { in adv7842_querystd()
2888 case 0: in adv7842_querystd()
2908 case 0xc: in adv7842_querystd()
2912 case 0xe: in adv7842_querystd()
2916 case 0xf: in adv7842_querystd()
2924 return 0; in adv7842_querystd()
2930 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); in adv7842_s_sdp_io()
2931 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); in adv7842_s_sdp_io()
2932 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); in adv7842_s_sdp_io()
2933 sdp_io_write(sd, 0x97, s->hs_width & 0xff); in adv7842_s_sdp_io()
2934 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); in adv7842_s_sdp_io()
2935 sdp_io_write(sd, 0x99, s->de_beg & 0xff); in adv7842_s_sdp_io()
2936 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); in adv7842_s_sdp_io()
2937 sdp_io_write(sd, 0x9b, s->de_end & 0xff); in adv7842_s_sdp_io()
2938 sdp_io_write(sd, 0xa8, s->vs_beg_o); in adv7842_s_sdp_io()
2939 sdp_io_write(sd, 0xa9, s->vs_beg_e); in adv7842_s_sdp_io()
2940 sdp_io_write(sd, 0xaa, s->vs_end_o); in adv7842_s_sdp_io()
2941 sdp_io_write(sd, 0xab, s->vs_end_e); in adv7842_s_sdp_io()
2942 sdp_io_write(sd, 0xac, s->de_v_beg_o); in adv7842_s_sdp_io()
2943 sdp_io_write(sd, 0xad, s->de_v_beg_e); in adv7842_s_sdp_io()
2944 sdp_io_write(sd, 0xae, s->de_v_end_o); in adv7842_s_sdp_io()
2945 sdp_io_write(sd, 0xaf, s->de_v_end_e); in adv7842_s_sdp_io()
2948 sdp_io_write(sd, 0x94, 0x00); in adv7842_s_sdp_io()
2949 sdp_io_write(sd, 0x95, 0x00); in adv7842_s_sdp_io()
2950 sdp_io_write(sd, 0x96, 0x00); in adv7842_s_sdp_io()
2951 sdp_io_write(sd, 0x97, 0x20); in adv7842_s_sdp_io()
2952 sdp_io_write(sd, 0x98, 0x00); in adv7842_s_sdp_io()
2953 sdp_io_write(sd, 0x99, 0x00); in adv7842_s_sdp_io()
2954 sdp_io_write(sd, 0x9a, 0x00); in adv7842_s_sdp_io()
2955 sdp_io_write(sd, 0x9b, 0x00); in adv7842_s_sdp_io()
2956 sdp_io_write(sd, 0xa8, 0x04); in adv7842_s_sdp_io()
2957 sdp_io_write(sd, 0xa9, 0x04); in adv7842_s_sdp_io()
2958 sdp_io_write(sd, 0xaa, 0x04); in adv7842_s_sdp_io()
2959 sdp_io_write(sd, 0xab, 0x04); in adv7842_s_sdp_io()
2960 sdp_io_write(sd, 0xac, 0x04); in adv7842_s_sdp_io()
2961 sdp_io_write(sd, 0xad, 0x04); in adv7842_s_sdp_io()
2962 sdp_io_write(sd, 0xae, 0x04); in adv7842_s_sdp_io()
2963 sdp_io_write(sd, 0xaf, 0x04); in adv7842_s_sdp_io()
2986 return 0; in adv7842_s_std()
3001 return 0; in adv7842_g_std()
3010 hdmi_write(sd, 0x48, in adv7842_core_init()
3011 (pdata->disable_pwrdnb ? 0x80 : 0) | in adv7842_core_init()
3012 (pdata->disable_cable_det_rst ? 0x40 : 0)); in adv7842_core_init()
3020 rep_write_and_or(sd, 0x77, 0xd3, 0x20); in adv7842_core_init()
3023 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ in adv7842_core_init()
3024 io_write(sd, 0x15, 0x80); /* Power up pads */ in adv7842_core_init()
3027 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3); in adv7842_core_init()
3028 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | in adv7842_core_init()
3034 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ in adv7842_core_init()
3037 io_write_and_or(sd, 0x14, 0xc0, in adv7842_core_init()
3043 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable | in adv7842_core_init()
3047 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force | in adv7842_core_init()
3053 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ in adv7842_core_init()
3054 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */ in adv7842_core_init()
3055 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ in adv7842_core_init()
3056 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ in adv7842_core_init()
3058 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ in adv7842_core_init()
3059 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); in adv7842_core_init()
3065 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */ in adv7842_core_init()
3068 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ in adv7842_core_init()
3069 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ in adv7842_core_init()
3070 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ in adv7842_core_init()
3071 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ in adv7842_core_init()
3072 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ in adv7842_core_init()
3074 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ in adv7842_core_init()
3075 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ in adv7842_core_init()
3076 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, in adv7842_core_init()
3078 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ in adv7842_core_init()
3079 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ in adv7842_core_init()
3080 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ in adv7842_core_init()
3081 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ in adv7842_core_init()
3085 * Manual UG-214, rev 0 is bit confusing on this bit in adv7842_core_init()
3088 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ in adv7842_core_init()
3097 hdmi_write(sd, 0x69, 0x5c); in adv7842_core_init()
3100 hdmi_write(sd, 0x69, 0xa3); in adv7842_core_init()
3102 io_write_and_or(sd, 0x20, 0xcf, 0x00); in adv7842_core_init()
3106 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); in adv7842_core_init()
3107 io_write(sd, 0x33, 0x40); in adv7842_core_init()
3110 io_write(sd, 0x40, 0xf2); /* Configure INT1 */ in adv7842_core_init()
3128 int pass = 0; in adv7842_ddr_ram_test()
3129 int fail = 0; in adv7842_ddr_ram_test()
3130 int complete = 0; in adv7842_ddr_ram_test()
3132 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */ in adv7842_ddr_ram_test()
3133 io_write(sd, 0x01, 0x00); /* Program SDP mode */ in adv7842_ddr_ram_test()
3134 afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */ in adv7842_ddr_ram_test()
3135 afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */ in adv7842_ddr_ram_test()
3136 afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */ in adv7842_ddr_ram_test()
3137 afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */ in adv7842_ddr_ram_test()
3138 afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */ in adv7842_ddr_ram_test()
3139 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3140 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */ in adv7842_ddr_ram_test()
3141 io_write(sd, 0x15, 0xBA); /* Enable outputs */ in adv7842_ddr_ram_test()
3142 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ in adv7842_ddr_ram_test()
3143 io_write(sd, 0xFF, 0x04); /* Reset memory controller */ in adv7842_ddr_ram_test()
3147 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ in adv7842_ddr_ram_test()
3148 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3149 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3150 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3151 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3152 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3153 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3154 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3155 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3156 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3157 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3161 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ in adv7842_ddr_ram_test()
3162 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ in adv7842_ddr_ram_test()
3166 for (i = 0; i < 10; i++) { in adv7842_ddr_ram_test()
3167 u8 result = sdp_io_read(sd, 0xdb); in adv7842_ddr_ram_test()
3168 if (result & 0x10) { in adv7842_ddr_ram_test()
3170 if (result & 0x20) in adv7842_ddr_ram_test()
3184 return 0; in adv7842_ddr_ram_test()
3190 io_write(sd, 0xf1, pdata->i2c_sdp << 1); in adv7842_rewrite_i2c_addresses()
3191 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); in adv7842_rewrite_i2c_addresses()
3192 io_write(sd, 0xf3, pdata->i2c_avlink << 1); in adv7842_rewrite_i2c_addresses()
3193 io_write(sd, 0xf4, pdata->i2c_cec << 1); in adv7842_rewrite_i2c_addresses()
3194 io_write(sd, 0xf5, pdata->i2c_infoframe << 1); in adv7842_rewrite_i2c_addresses()
3196 io_write(sd, 0xf8, pdata->i2c_afe << 1); in adv7842_rewrite_i2c_addresses()
3197 io_write(sd, 0xf9, pdata->i2c_repeater << 1); in adv7842_rewrite_i2c_addresses()
3198 io_write(sd, 0xfa, pdata->i2c_edid << 1); in adv7842_rewrite_i2c_addresses()
3199 io_write(sd, 0xfb, pdata->i2c_hdmi << 1); in adv7842_rewrite_i2c_addresses()
3201 io_write(sd, 0xfd, pdata->i2c_cp << 1); in adv7842_rewrite_i2c_addresses()
3202 io_write(sd, 0xfe, pdata->i2c_vdp << 1); in adv7842_rewrite_i2c_addresses()
3211 int ret = 0; in adv7842_command_ram_test()
3247 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings)); in adv7842_command_ram_test()
3249 adv7842_s_dv_timings(sd, 0, &timings); in adv7842_command_ram_test()
3287 return 0; in adv7842_debugfs_if_read()
3291 index = 0; in adv7842_debugfs_if_read()
3303 return 0; in adv7842_debugfs_if_read()
3307 if (len > 0) in adv7842_debugfs_if_read()
3309 return len < 0 ? 0 : len; in adv7842_debugfs_if_read()
3400 .min = 0,
3401 .max = 0x1f,
3403 .def = 0,
3421 .max = 0xffffff,
3422 .step = 0x1,
3462 if (addr == 0) { in adv7842_dummy_client()
3469 v4l2_err(sd, "register %s on i2c addr 0x%x failed with %ld\n", in adv7842_dummy_client()
3482 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3); in adv7842_register_clients()
3483 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4); in adv7842_register_clients()
3484 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5); in adv7842_register_clients()
3485 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2); in adv7842_register_clients()
3486 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1); in adv7842_register_clients()
3487 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8); in adv7842_register_clients()
3488 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9); in adv7842_register_clients()
3489 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa); in adv7842_register_clients()
3490 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb); in adv7842_register_clients()
3491 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd); in adv7842_register_clients()
3492 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe); in adv7842_register_clients()
3507 return 0; in adv7842_register_clients()
3527 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n", in adv7842_probe()
3554 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | in adv7842_probe()
3555 adv_smbus_read_byte_data_check(client, 0xeb, false); in adv7842_probe()
3556 if (rev != 0x2012) { in adv7842_probe()
3557 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev); in adv7842_probe()
3558 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | in adv7842_probe()
3559 adv_smbus_read_byte_data_check(client, 0xeb, false); in adv7842_probe()
3561 if (rev != 0x2012) { in adv7842_probe()
3562 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n", in adv7842_probe()
3576 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); in adv7842_probe()
3578 V4L2_CID_CONTRAST, 0, 255, 1, 128); in adv7842_probe()
3580 V4L2_CID_SATURATION, 0, 255, 1, 128); in adv7842_probe()
3582 V4L2_CID_HUE, 0, 128, 1, 0); in adv7842_probe()
3585 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); in adv7842_probe()
3591 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0); in adv7842_probe()
3601 0, V4L2_DV_RGB_RANGE_AUTO); in adv7842_probe()
3612 if (adv7842_register_clients(sd) < 0) { in adv7842_probe()
3623 for (i = 0; i < ADV7842_PAD_SOURCE; ++i) in adv7842_probe()
3644 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, in adv7842_probe()
3646 return 0; in adv7842_probe()