Lines Matching +full:adc +full:- +full:alt +full:- +full:channel
1 // SPDX-License-Identifier: GPL-2.0-only
3 * adv7604 - Analog Devices ADV7604 video decoder driver
11 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
13 * REF_02 - Analog devices, Register map documentation, Documentation of
15 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
26 #include <linux/v4l2-dv-timings.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-device.h>
36 #include <media/v4l2-event.h>
37 #include <media/v4l2-dv-timings.h>
38 #include <media/v4l2-fwnode.h>
42 MODULE_PARM_DESC(debug, "debug level (0-2)");
218 return state->info->has_afe; in adv76xx_has_afe()
325 /* ----------------------------------------------------------------------- */
342 /* ----------------------------------------------------------------------- */
347 struct i2c_client *client = state->i2c_clients[client_page]; in adv76xx_read_check()
351 err = regmap_read(state->regmap[client_page], reg, &val); in adv76xx_read_check()
355 client->addr, reg); in adv76xx_read_check()
371 struct regmap *regmap = state->regmap[client_page]; in adv76xx_write_block()
379 /* ----------------------------------------------------------------------- */
392 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); in io_write()
412 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); in avlink_write()
426 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); in cec_write()
446 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); in infoframe_write()
460 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); in afe_write()
474 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); in rep_write()
493 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); in edid_write()
508 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? in edid_write_block()
510 (total_len - i); in edid_write_block()
522 const struct adv76xx_chip_info *info = state->info; in adv76xx_set_hpd()
525 if (info->type == ADV7604) { in adv76xx_set_hpd()
526 for (i = 0; i < state->info->num_dv_ports; ++i) in adv76xx_set_hpd()
527 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); in adv76xx_set_hpd()
529 for (i = 0; i < state->info->num_dv_ports; ++i) in adv76xx_set_hpd()
530 io_write_clr_set(&state->sd, 0x20, 0x80 >> i, in adv76xx_set_hpd()
531 (!!(hpd & BIT(i))) << (7 - i)); in adv76xx_set_hpd()
534 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); in adv76xx_set_hpd()
542 struct v4l2_subdev *sd = &state->sd; in adv76xx_delayed_work_enable_hotplug()
546 adv76xx_set_hpd(state, state->edid.present); in adv76xx_delayed_work_enable_hotplug()
565 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); in hdmi_write()
577 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); in test_write()
596 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); in cp_write()
615 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); in vdp_write()
629 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) in adv76xx_read_reg()
630 return -EINVAL; in adv76xx_read_reg()
633 err = regmap_read(state->regmap[page], reg, &val); in adv76xx_read_reg()
644 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) in adv76xx_write_reg()
645 return -EINVAL; in adv76xx_write_reg()
649 return regmap_write(state->regmap[page], reg, val); in adv76xx_write_reg()
661 /* -----------------------------------------------------------------------------
757 for (i = 0; i < state->info->nformats; ++i) { in adv76xx_format_info()
758 if (state->info->formats[i].code == code) in adv76xx_format_info()
759 return &state->info->formats[i]; in adv76xx_format_info()
765 /* ----------------------------------------------------------------------- */
771 return state->selected_input == ADV7604_PAD_VGA_RGB || in is_analog_input()
772 state->selected_input == ADV7604_PAD_VGA_COMP; in is_analog_input()
779 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || in is_digital_input()
780 state->selected_input == ADV7604_PAD_HDMI_PORT_B || in is_digital_input()
781 state->selected_input == ADV7604_PAD_HDMI_PORT_C || in is_digital_input()
782 state->selected_input == ADV7604_PAD_HDMI_PORT_D; in is_digital_input()
809 * case, pad value -1 returns the capabilities for the currently selected input.
814 if (pad == -1) { in adv76xx_get_dv_timings_cap()
817 pad = state->selected_input; in adv76xx_get_dv_timings_cap()
835 /* ----------------------------------------------------------------------- */
840 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); in adv76xx_inv_register()
841 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); in adv76xx_inv_register()
842 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); in adv76xx_inv_register()
843 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); in adv76xx_inv_register()
844 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); in adv76xx_inv_register()
845 v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); in adv76xx_inv_register()
846 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); in adv76xx_inv_register()
847 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); in adv76xx_inv_register()
848 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); in adv76xx_inv_register()
849 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); in adv76xx_inv_register()
850 v4l2_info(sd, "0xa00-0xaff: Test Map\n"); in adv76xx_inv_register()
851 v4l2_info(sd, "0xb00-0xbff: CP Map\n"); in adv76xx_inv_register()
852 v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); in adv76xx_inv_register()
860 ret = adv76xx_read_reg(sd, reg->reg); in adv76xx_g_register()
862 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); in adv76xx_g_register()
867 reg->size = 1; in adv76xx_g_register()
868 reg->val = ret; in adv76xx_g_register()
878 ret = adv76xx_write_reg(sd, reg->reg, reg->val); in adv76xx_s_register()
880 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); in adv76xx_s_register()
919 const struct adv76xx_chip_info *info = state->info; in adv76xx_s_detect_tx_5v_ctrl()
920 u16 cable_det = info->read_cable_det(sd); in adv76xx_s_detect_tx_5v_ctrl()
922 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det); in adv76xx_s_detect_tx_5v_ctrl()
942 return -1; in find_and_set_predefined_video_timings()
985 __func__, state->selected_input); in configure_predefined_video_timings()
986 err = -1; in configure_predefined_video_timings()
999 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; in configure_custom_video_timings()
1000 u16 cp_start_eav = width - bt->hfrontporch; in configure_custom_video_timings()
1001 u16 cp_start_vbi = height - bt->vfrontporch; in configure_custom_video_timings()
1002 u16 cp_end_vbi = bt->vsync + bt->vbackporch; in configure_custom_video_timings()
1003 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? in configure_custom_video_timings()
1004 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; in configure_custom_video_timings()
1019 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ in configure_custom_video_timings()
1021 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ in configure_custom_video_timings()
1022 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO], in configure_custom_video_timings()
1026 /* active video - horizontal timing */ in configure_custom_video_timings()
1032 /* active video - vertical timing */ in configure_custom_video_timings()
1044 __func__, state->selected_input); in configure_custom_video_timings()
1074 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], in adv76xx_set_offset()
1104 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], in adv76xx_set_gain()
1120 __func__, state->rgb_quantization_range, in set_rgb_quantization_range()
1127 switch (state->rgb_quantization_range) { in set_rgb_quantization_range()
1129 if (state->selected_input == ADV7604_PAD_VGA_RGB) { in set_rgb_quantization_range()
1131 * Set RGB full range (0-255) */ in set_rgb_quantization_range()
1136 if (state->selected_input == ADV7604_PAD_VGA_COMP) { in set_rgb_quantization_range()
1150 /* Receiving DVI-D signal in set_rgb_quantization_range()
1153 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { in set_rgb_quantization_range()
1154 /* RGB limited range (16-235) */ in set_rgb_quantization_range()
1157 /* RGB full range (0-255) */ in set_rgb_quantization_range()
1169 if (state->selected_input == ADV7604_PAD_VGA_COMP) { in set_rgb_quantization_range()
1170 /* YCrCb limited range (16-235) */ in set_rgb_quantization_range()
1178 /* RGB limited range (16-235) */ in set_rgb_quantization_range()
1183 if (state->selected_input == ADV7604_PAD_VGA_COMP) { in set_rgb_quantization_range()
1184 /* YCrCb full range (0-255) */ in set_rgb_quantization_range()
1192 /* RGB full range (0-255) */ in set_rgb_quantization_range()
1198 /* Adjust gain/offset for DVI-D signals only */ in set_rgb_quantization_range()
1212 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; in adv76xx_s_ctrl()
1216 switch (ctrl->id) { in adv76xx_s_ctrl()
1218 cp_write(sd, 0x3c, ctrl->val); in adv76xx_s_ctrl()
1221 cp_write(sd, 0x3a, ctrl->val); in adv76xx_s_ctrl()
1224 cp_write(sd, 0x3b, ctrl->val); in adv76xx_s_ctrl()
1227 cp_write(sd, 0x3d, ctrl->val); in adv76xx_s_ctrl()
1230 state->rgb_quantization_range = ctrl->val; in adv76xx_s_ctrl()
1235 return -EINVAL; in adv76xx_s_ctrl()
1240 afe_write(sd, 0xc8, ctrl->val); in adv76xx_s_ctrl()
1245 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); in adv76xx_s_ctrl()
1248 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); in adv76xx_s_ctrl()
1249 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); in adv76xx_s_ctrl()
1250 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); in adv76xx_s_ctrl()
1253 return -EINVAL; in adv76xx_s_ctrl()
1259 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; in adv76xx_g_volatile_ctrl()
1261 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { in adv76xx_g_volatile_ctrl()
1262 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; in adv76xx_g_volatile_ctrl()
1264 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; in adv76xx_g_volatile_ctrl()
1267 return -EINVAL; in adv76xx_g_volatile_ctrl()
1270 /* ----------------------------------------------------------------------- */
1282 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); in no_signal_tmds()
1288 const struct adv76xx_chip_info *info = state->info; in no_lock_tmds()
1290 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; in no_lock_tmds()
1309 /* TODO channel 2 */ in no_lock_sspd()
1315 /* TODO channel 2 */ in no_lock_stdi()
1367 /* ----------------------------------------------------------------------- */
1380 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; in stdi2dv_timings()
1388 adv76xx_get_dv_timings_cap(sd, -1), in stdi2dv_timings()
1391 if (vtotal(bt) != stdi->lcf + 1) in stdi2dv_timings()
1393 if (bt->vsync != stdi->lcvs) in stdi2dv_timings()
1398 if ((pix_clk < bt->pixelclock + 1000000) && in stdi2dv_timings()
1399 (pix_clk > bt->pixelclock - 1000000)) { in stdi2dv_timings()
1405 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, in stdi2dv_timings()
1406 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | in stdi2dv_timings()
1407 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1410 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, in stdi2dv_timings()
1411 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | in stdi2dv_timings()
1412 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1413 false, state->aspect_ratio, timings)) in stdi2dv_timings()
1418 __func__, stdi->lcvs, stdi->lcf, stdi->bl, in stdi2dv_timings()
1419 stdi->hs_pol, stdi->vs_pol); in stdi2dv_timings()
1420 return -1; in stdi2dv_timings()
1427 const struct adv76xx_chip_info *info = state->info; in read_stdi()
1432 return -1; in read_stdi()
1436 stdi->bl = cp_read16(sd, 0xb1, 0x3fff); in read_stdi()
1437 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); in read_stdi()
1438 stdi->lcvs = cp_read(sd, 0xb3) >> 3; in read_stdi()
1439 stdi->interlaced = io_read(sd, 0x12) & 0x10; in read_stdi()
1445 stdi->hs_pol = polarity & 0x10 in read_stdi()
1446 ? (polarity & 0x08 ? '+' : '-') : 'x'; in read_stdi()
1447 stdi->vs_pol = polarity & 0x40 in read_stdi()
1448 ? (polarity & 0x20 ? '+' : '-') : 'x'; in read_stdi()
1450 stdi->hs_pol = 'x'; in read_stdi()
1451 stdi->vs_pol = 'x'; in read_stdi()
1455 stdi->hs_pol = polarity & 0x20 ? '+' : '-'; in read_stdi()
1456 stdi->vs_pol = polarity & 0x10 ? '+' : '-'; in read_stdi()
1462 return -1; in read_stdi()
1465 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { in read_stdi()
1468 return -1; in read_stdi()
1472 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", in read_stdi()
1473 __func__, stdi->lcf, stdi->bl, stdi->lcvs, in read_stdi()
1474 stdi->hs_pol, stdi->vs_pol, in read_stdi()
1475 stdi->interlaced ? "interlaced" : "progressive"); in read_stdi()
1485 if (timings->pad >= state->source_pad) in adv76xx_enum_dv_timings()
1486 return -EINVAL; in adv76xx_enum_dv_timings()
1489 adv76xx_get_dv_timings_cap(sd, timings->pad), in adv76xx_enum_dv_timings()
1497 unsigned int pad = cap->pad; in adv76xx_dv_timings_cap()
1499 if (cap->pad >= state->source_pad) in adv76xx_dv_timings_cap()
1500 return -EINVAL; in adv76xx_dv_timings_cap()
1503 cap->pad = pad; in adv76xx_dv_timings_cap()
1513 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1), in adv76xx_fill_optional_dv_timings_fields()
1545 const struct adv76xx_chip_info *info = state->info; in adv76xx_read_hdmi_pixelclock()
1548 freq = info->read_hdmi_pixelclock(sd); in adv76xx_read_hdmi_pixelclock()
1564 const struct adv76xx_chip_info *info = state->info; in adv76xx_query_dv_timings()
1565 struct v4l2_bt_timings *bt = &timings->bt; in adv76xx_query_dv_timings()
1569 return -EINVAL; in adv76xx_query_dv_timings()
1574 state->restart_stdi_once = true; in adv76xx_query_dv_timings()
1576 return -ENOLINK; in adv76xx_query_dv_timings()
1582 return -ENOLINK; in adv76xx_query_dv_timings()
1584 bt->interlaced = stdi.interlaced ? in adv76xx_query_dv_timings()
1592 w = hdmi_read16(sd, 0x07, info->linewidth_mask); in adv76xx_query_dv_timings()
1593 h = hdmi_read16(sd, 0x09, info->field0_height_mask); in adv76xx_query_dv_timings()
1599 bt->width == w && bt->height == h) in adv76xx_query_dv_timings()
1602 timings->type = V4L2_DV_BT_656_1120; in adv76xx_query_dv_timings()
1604 bt->width = w; in adv76xx_query_dv_timings()
1605 bt->height = h; in adv76xx_query_dv_timings()
1606 bt->pixelclock = adv76xx_read_hdmi_pixelclock(sd); in adv76xx_query_dv_timings()
1607 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); in adv76xx_query_dv_timings()
1608 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); in adv76xx_query_dv_timings()
1609 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); in adv76xx_query_dv_timings()
1610 bt->vfrontporch = hdmi_read16(sd, 0x2a, in adv76xx_query_dv_timings()
1611 info->field0_vfrontporch_mask) / 2; in adv76xx_query_dv_timings()
1612 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; in adv76xx_query_dv_timings()
1613 bt->vbackporch = hdmi_read16(sd, 0x32, in adv76xx_query_dv_timings()
1614 info->field0_vbackporch_mask) / 2; in adv76xx_query_dv_timings()
1615 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv76xx_query_dv_timings()
1617 if (bt->interlaced == V4L2_DV_INTERLACED) { in adv76xx_query_dv_timings()
1618 bt->height += hdmi_read16(sd, 0x0b, in adv76xx_query_dv_timings()
1619 info->field1_height_mask); in adv76xx_query_dv_timings()
1620 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, in adv76xx_query_dv_timings()
1621 info->field1_vfrontporch_mask) / 2; in adv76xx_query_dv_timings()
1622 bt->il_vsync = hdmi_read16(sd, 0x30, in adv76xx_query_dv_timings()
1623 info->field1_vsync_mask) / 2; in adv76xx_query_dv_timings()
1624 bt->il_vbackporch = hdmi_read16(sd, 0x34, in adv76xx_query_dv_timings()
1625 info->field1_vbackporch_mask) / 2; in adv76xx_query_dv_timings()
1630 * Since LCVS values are inaccurate [REF_03, p. 275-276], in adv76xx_query_dv_timings()
1631 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. in adv76xx_query_dv_timings()
1639 stdi.lcvs -= 2; in adv76xx_query_dv_timings()
1640 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); in adv76xx_query_dv_timings()
1651 if (state->restart_stdi_once) { in adv76xx_query_dv_timings()
1653 /* TODO restart STDI for Sync Channel 2 */ in adv76xx_query_dv_timings()
1654 /* enter one-shot mode */ in adv76xx_query_dv_timings()
1660 state->restart_stdi_once = false; in adv76xx_query_dv_timings()
1661 return -ENOLINK; in adv76xx_query_dv_timings()
1664 return -ERANGE; in adv76xx_query_dv_timings()
1666 state->restart_stdi_once = true; in adv76xx_query_dv_timings()
1673 return -ENOLINK; in adv76xx_query_dv_timings()
1676 if ((is_analog_input(sd) && bt->pixelclock > 170000000) || in adv76xx_query_dv_timings()
1677 (is_digital_input(sd) && bt->pixelclock > 225000000)) { in adv76xx_query_dv_timings()
1679 __func__, (u32)bt->pixelclock); in adv76xx_query_dv_timings()
1680 return -ERANGE; in adv76xx_query_dv_timings()
1684 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", in adv76xx_query_dv_timings()
1698 return -EINVAL; in adv76xx_s_dv_timings()
1700 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { in adv76xx_s_dv_timings()
1705 bt = &timings->bt; in adv76xx_s_dv_timings()
1707 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1), in adv76xx_s_dv_timings()
1709 return -ERANGE; in adv76xx_s_dv_timings()
1713 state->timings = *timings; in adv76xx_s_dv_timings()
1715 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); in adv76xx_s_dv_timings()
1728 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", in adv76xx_s_dv_timings()
1738 *timings = state->timings; in adv76xx_g_dv_timings()
1759 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); in enable_input()
1760 state->info->set_termination(sd, true); in enable_input()
1765 __func__, state->selected_input); in enable_input()
1776 state->info->set_termination(sd, false); in disable_input()
1782 const struct adv76xx_chip_info *info = state->info; in select_input()
1785 adv76xx_write_reg_seq(sd, info->recommended_settings[0]); in select_input()
1787 afe_write(sd, 0x00, 0x08); /* power up ADC */ in select_input()
1791 hdmi_write(sd, 0x00, state->selected_input & 0x03); in select_input()
1793 adv76xx_write_reg_seq(sd, info->recommended_settings[1]); in select_input()
1796 afe_write(sd, 0x00, 0xff); /* power down ADC */ in select_input()
1801 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ in select_input()
1803 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ in select_input()
1806 __func__, state->selected_input); in select_input()
1819 __func__, input, state->selected_input); in adv76xx_s_routing()
1821 if (input == state->selected_input) in adv76xx_s_routing()
1824 if (input > state->info->max_port) in adv76xx_s_routing()
1825 return -EINVAL; in adv76xx_s_routing()
1827 state->selected_input = input; in adv76xx_s_routing()
1844 if (code->index >= state->info->nformats) in adv76xx_enum_mbus_code()
1845 return -EINVAL; in adv76xx_enum_mbus_code()
1847 code->code = state->info->formats[code->index].code; in adv76xx_enum_mbus_code()
1857 format->width = state->timings.bt.width; in adv76xx_fill_format()
1858 format->height = state->timings.bt.height; in adv76xx_fill_format()
1859 format->field = V4L2_FIELD_NONE; in adv76xx_fill_format()
1860 format->colorspace = V4L2_COLORSPACE_SRGB; in adv76xx_fill_format()
1862 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) in adv76xx_fill_format()
1863 format->colorspace = (state->timings.bt.height <= 576) ? in adv76xx_fill_format()
1877 * ----------+-------------------------------------------------
1879 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1880 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1881 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1894 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), in adv76xx_op_ch_sel()
1895 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), in adv76xx_op_ch_sel()
1896 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), in adv76xx_op_ch_sel()
1901 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; in adv76xx_op_ch_sel()
1906 struct v4l2_subdev *sd = &state->sd; in adv76xx_setup_format()
1909 state->format->rgb_out ? ADV76XX_RGB_OUT : 0); in adv76xx_setup_format()
1910 io_write(sd, 0x03, state->format->op_format_sel | in adv76xx_setup_format()
1911 state->pdata.op_format_mode_sel); in adv76xx_setup_format()
1914 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); in adv76xx_setup_format()
1924 if (format->pad != state->source_pad) in adv76xx_get_format()
1925 return -EINVAL; in adv76xx_get_format()
1927 adv76xx_fill_format(state, &format->format); in adv76xx_get_format()
1929 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { in adv76xx_get_format()
1932 fmt = v4l2_subdev_state_get_format(sd_state, format->pad); in adv76xx_get_format()
1933 format->format.code = fmt->code; in adv76xx_get_format()
1935 format->format.code = state->format->code; in adv76xx_get_format()
1947 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) in adv76xx_get_selection()
1948 return -EINVAL; in adv76xx_get_selection()
1950 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS) in adv76xx_get_selection()
1951 return -EINVAL; in adv76xx_get_selection()
1953 sel->r.left = 0; in adv76xx_get_selection()
1954 sel->r.top = 0; in adv76xx_get_selection()
1955 sel->r.width = state->timings.bt.width; in adv76xx_get_selection()
1956 sel->r.height = state->timings.bt.height; in adv76xx_get_selection()
1968 if (format->pad != state->source_pad) in adv76xx_set_format()
1969 return -EINVAL; in adv76xx_set_format()
1971 info = adv76xx_format_info(state, format->format.code); in adv76xx_set_format()
1975 adv76xx_fill_format(state, &format->format); in adv76xx_set_format()
1976 format->format.code = info->code; in adv76xx_set_format()
1978 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { in adv76xx_set_format()
1981 fmt = v4l2_subdev_state_get_format(sd_state, format->pad); in adv76xx_set_format()
1982 fmt->code = format->format.code; in adv76xx_set_format()
1984 state->format = info; in adv76xx_set_format()
2004 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, in adv76xx_cec_tx_raw_status()
2025 cec_transmit_done(state->cec_adap, status, in adv76xx_cec_tx_raw_status()
2031 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); in adv76xx_cec_tx_raw_status()
2039 const struct adv76xx_chip_info *info = state->info; in adv76xx_cec_isr()
2043 cec_irq = io_read(sd, info->cec_irq_status) & 0x0f; in adv76xx_cec_isr()
2061 cec_write(sd, info->cec_rx_enable, in adv76xx_cec_isr()
2062 info->cec_rx_enable_mask); /* re-enable rx */ in adv76xx_cec_isr()
2063 cec_received_msg(state->cec_adap, &msg); in adv76xx_cec_isr()
2067 if (info->cec_irq_swap) { in adv76xx_cec_isr()
2075 io_write(sd, info->cec_irq_status + 1, cec_irq); in adv76xx_cec_isr()
2084 const struct adv76xx_chip_info *info = state->info; in adv76xx_cec_adap_enable()
2085 struct v4l2_subdev *sd = &state->sd; in adv76xx_cec_adap_enable()
2087 if (!state->cec_enabled_adap && enable) { in adv76xx_cec_adap_enable()
2096 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f); in adv76xx_cec_adap_enable()
2097 cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask); in adv76xx_cec_adap_enable()
2098 } else if (state->cec_enabled_adap && !enable) { in adv76xx_cec_adap_enable()
2100 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00); in adv76xx_cec_adap_enable()
2101 /* disable address mask 1-3 */ in adv76xx_cec_adap_enable()
2105 state->cec_valid_addrs = 0; in adv76xx_cec_adap_enable()
2107 state->cec_enabled_adap = enable; in adv76xx_cec_adap_enable()
2115 struct v4l2_subdev *sd = &state->sd; in adv76xx_cec_adap_log_addr()
2118 if (!state->cec_enabled_adap) in adv76xx_cec_adap_log_addr()
2119 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; in adv76xx_cec_adap_log_addr()
2123 state->cec_valid_addrs = 0; in adv76xx_cec_adap_log_addr()
2128 bool is_valid = state->cec_valid_addrs & (1 << i); in adv76xx_cec_adap_log_addr()
2132 if (is_valid && state->cec_addr[i] == addr) in adv76xx_cec_adap_log_addr()
2138 return -ENXIO; in adv76xx_cec_adap_log_addr()
2140 state->cec_addr[i] = addr; in adv76xx_cec_adap_log_addr()
2141 state->cec_valid_addrs |= 1 << i; in adv76xx_cec_adap_log_addr()
2170 struct v4l2_subdev *sd = &state->sd; in adv76xx_cec_adap_transmit()
2171 u8 len = msg->len; in adv76xx_cec_adap_transmit()
2175 * The number of retries is the number of attempts - 1, but retry in adv76xx_cec_adap_transmit()
2179 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); in adv76xx_cec_adap_transmit()
2183 return -EINVAL; in adv76xx_cec_adap_transmit()
2188 cec_write(sd, i, msg->msg[i]); in adv76xx_cec_adap_transmit()
2207 const struct adv76xx_chip_info *info = state->info; in adv76xx_isr()
2227 ? irq_reg_0x6b & info->fmt_change_digital_mask in adv76xx_isr()
2255 tx_5v = irq_reg_0x70 & info->cable_det_mask; in adv76xx_isr()
2270 adv76xx_isr(&state->sd, 0, &handled); in adv76xx_irq_handler()
2280 memset(edid->reserved, 0, sizeof(edid->reserved)); in adv76xx_get_edid()
2282 switch (edid->pad) { in adv76xx_get_edid()
2287 if (state->edid.present & (1 << edid->pad)) in adv76xx_get_edid()
2288 data = state->edid.edid; in adv76xx_get_edid()
2291 return -EINVAL; in adv76xx_get_edid()
2294 if (edid->start_block == 0 && edid->blocks == 0) { in adv76xx_get_edid()
2295 edid->blocks = data ? state->edid.blocks : 0; in adv76xx_get_edid()
2300 return -ENODATA; in adv76xx_get_edid()
2302 if (edid->start_block >= state->edid.blocks) in adv76xx_get_edid()
2303 return -EINVAL; in adv76xx_get_edid()
2305 if (edid->start_block + edid->blocks > state->edid.blocks) in adv76xx_get_edid()
2306 edid->blocks = state->edid.blocks - edid->start_block; in adv76xx_get_edid()
2308 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); in adv76xx_get_edid()
2316 const struct adv76xx_chip_info *info = state->info; in adv76xx_set_edid()
2322 memset(edid->reserved, 0, sizeof(edid->reserved)); in adv76xx_set_edid()
2324 if (edid->pad > ADV7604_PAD_HDMI_PORT_D) in adv76xx_set_edid()
2325 return -EINVAL; in adv76xx_set_edid()
2326 if (edid->start_block != 0) in adv76xx_set_edid()
2327 return -EINVAL; in adv76xx_set_edid()
2328 if (edid->blocks == 0) { in adv76xx_set_edid()
2330 state->edid.present &= ~(1 << edid->pad); in adv76xx_set_edid()
2331 adv76xx_set_hpd(state, state->edid.present); in adv76xx_set_edid()
2332 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); in adv76xx_set_edid()
2335 state->aspect_ratio.numerator = 16; in adv76xx_set_edid()
2336 state->aspect_ratio.denominator = 9; in adv76xx_set_edid()
2338 if (!state->edid.present) { in adv76xx_set_edid()
2339 state->edid.blocks = 0; in adv76xx_set_edid()
2340 cec_phys_addr_invalidate(state->cec_adap); in adv76xx_set_edid()
2344 __func__, edid->pad, state->edid.present); in adv76xx_set_edid()
2347 if (edid->blocks > ADV76XX_MAX_EDID_BLOCKS) { in adv76xx_set_edid()
2348 edid->blocks = ADV76XX_MAX_EDID_BLOCKS; in adv76xx_set_edid()
2349 return -E2BIG; in adv76xx_set_edid()
2352 pa = v4l2_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc); in adv76xx_set_edid()
2363 pa = (edid->edid[spa_loc] << 8) | edid->edid[spa_loc + 1]; in adv76xx_set_edid()
2367 __func__, edid->pad, state->edid.present); in adv76xx_set_edid()
2370 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); in adv76xx_set_edid()
2372 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); in adv76xx_set_edid()
2374 switch (edid->pad) { in adv76xx_set_edid()
2376 state->spa_port_a[0] = pa >> 8; in adv76xx_set_edid()
2377 state->spa_port_a[1] = pa & 0xff; in adv76xx_set_edid()
2380 rep_write(sd, info->edid_spa_port_b_reg, pa >> 8); in adv76xx_set_edid()
2381 rep_write(sd, info->edid_spa_port_b_reg + 1, pa & 0xff); in adv76xx_set_edid()
2384 rep_write(sd, info->edid_spa_port_b_reg + 2, pa >> 8); in adv76xx_set_edid()
2385 rep_write(sd, info->edid_spa_port_b_reg + 3, pa & 0xff); in adv76xx_set_edid()
2388 rep_write(sd, info->edid_spa_port_b_reg + 4, pa >> 8); in adv76xx_set_edid()
2389 rep_write(sd, info->edid_spa_port_b_reg + 5, pa & 0xff); in adv76xx_set_edid()
2392 return -EINVAL; in adv76xx_set_edid()
2395 if (info->edid_spa_loc_reg) { in adv76xx_set_edid()
2396 u8 mask = info->edid_spa_loc_msb_mask; in adv76xx_set_edid()
2398 rep_write(sd, info->edid_spa_loc_reg, spa_loc & 0xff); in adv76xx_set_edid()
2399 rep_write_clr_set(sd, info->edid_spa_loc_reg + 1, in adv76xx_set_edid()
2403 edid->edid[spa_loc] = state->spa_port_a[0]; in adv76xx_set_edid()
2404 edid->edid[spa_loc + 1] = state->spa_port_a[1]; in adv76xx_set_edid()
2406 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); in adv76xx_set_edid()
2407 state->edid.blocks = edid->blocks; in adv76xx_set_edid()
2408 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], in adv76xx_set_edid()
2409 edid->edid[0x16]); in adv76xx_set_edid()
2410 state->edid.present |= 1 << edid->pad; in adv76xx_set_edid()
2412 rep_write_clr_set(sd, info->edid_segment_reg, in adv76xx_set_edid()
2413 info->edid_segment_mask, 0); in adv76xx_set_edid()
2414 err = edid_write_block(sd, 128 * min(edid->blocks, 2U), state->edid.edid); in adv76xx_set_edid()
2416 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); in adv76xx_set_edid()
2419 if (edid->blocks > 2) { in adv76xx_set_edid()
2420 rep_write_clr_set(sd, info->edid_segment_reg, in adv76xx_set_edid()
2421 info->edid_segment_mask, in adv76xx_set_edid()
2422 info->edid_segment_mask); in adv76xx_set_edid()
2423 err = edid_write_block(sd, 128 * (edid->blocks - 2), in adv76xx_set_edid()
2424 state->edid.edid + 256); in adv76xx_set_edid()
2427 err, edid->pad); in adv76xx_set_edid()
2434 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); in adv76xx_set_edid()
2437 if (rep_read(sd, info->edid_status_reg) & state->edid.present) in adv76xx_set_edid()
2442 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); in adv76xx_set_edid()
2443 return -EIO; in adv76xx_set_edid()
2445 cec_s_phys_addr(state->cec_adap, parent_pa, false); in adv76xx_set_edid()
2448 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10); in adv76xx_set_edid()
2452 /*********** avi info frame CEA-861-E **************/
2471 return -ENOENT; in adv76xx_read_infoframe()
2483 return -ENOENT; in adv76xx_read_infoframe()
2493 return -ENOENT; in adv76xx_read_infoframe()
2503 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); in adv76xx_log_infoframes()
2512 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame); in adv76xx_log_infoframes()
2519 const struct adv76xx_chip_info *info = state->info; in adv76xx_log_status()
2527 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", in adv76xx_log_status()
2528 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", in adv76xx_log_status()
2529 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", in adv76xx_log_status()
2533 "RGB limited range (16-235)", "RGB full range (0-255)", in adv76xx_log_status()
2534 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", in adv76xx_log_status()
2536 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", in adv76xx_log_status()
2541 "RGB limited range (16-235)", "RGB full range (0-255)", in adv76xx_log_status()
2542 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", in adv76xx_log_status()
2544 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", in adv76xx_log_status()
2550 "RGB limited range (16-235)", in adv76xx_log_status()
2551 "RGB full range (0-255)", in adv76xx_log_status()
2554 "8-bits per channel", in adv76xx_log_status()
2555 "10-bits per channel", in adv76xx_log_status()
2556 "12-bits per channel", in adv76xx_log_status()
2557 "16-bits per channel (not supported)" in adv76xx_log_status()
2560 v4l2_info(sd, "-----Chip status-----\n"); in adv76xx_log_status()
2562 edid_enabled = rep_read(sd, info->edid_status_reg); in adv76xx_log_status()
2568 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? in adv76xx_log_status()
2570 if (state->cec_enabled_adap) { in adv76xx_log_status()
2574 bool is_valid = state->cec_valid_addrs & (1 << i); in adv76xx_log_status()
2578 state->cec_addr[i]); in adv76xx_log_status()
2582 v4l2_info(sd, "-----Signal status-----\n"); in adv76xx_log_status()
2583 cable_det = info->read_cable_det(sd); in adv76xx_log_status()
2598 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", in adv76xx_log_status()
2602 v4l2_info(sd, "-----Video Timings-----\n"); in adv76xx_log_status()
2606 …v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync… in adv76xx_log_status()
2613 v4l2_print_dv_timings(sd->name, "Detected format: ", in adv76xx_log_status()
2615 v4l2_print_dv_timings(sd->name, "Configured format: ", in adv76xx_log_status()
2616 &state->timings, true); in adv76xx_log_status()
2621 v4l2_info(sd, "-----Color space-----\n"); in adv76xx_log_status()
2623 rgb_quantization_range_txt[state->rgb_quantization_range]); in adv76xx_log_status()
2626 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n", in adv76xx_log_status()
2629 "(16-235)" : "(0-255)", in adv76xx_log_status()
2632 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); in adv76xx_log_status()
2637 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); in adv76xx_log_status()
2656 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); in adv76xx_log_status()
2679 switch (sub->type) { in adv76xx_subscribe_event()
2685 return -EINVAL; in adv76xx_subscribe_event()
2695 err = cec_register_adapter(state->cec_adap, &client->dev); in adv76xx_registered()
2697 cec_delete_adapter(state->cec_adap); in adv76xx_registered()
2705 cec_unregister_adapter(state->cec_adap); in adv76xx_unregistered()
2708 /* ----------------------------------------------------------------------- */
2756 /* -------------------------- custom ctrls ---------------------------------- */
2791 /* ----------------------------------------------------------------------- */
2817 const struct adv76xx_chip_info *info = state->info; in adv76xx_core_init()
2818 struct adv76xx_platform_data *pdata = &state->pdata; in adv76xx_core_init()
2821 (pdata->disable_pwrdnb ? 0x80 : 0) | in adv76xx_core_init()
2822 (pdata->disable_cable_det_rst ? 0x40 : 0)); in adv76xx_core_init()
2826 if (pdata->default_input >= 0 && in adv76xx_core_init()
2827 pdata->default_input < state->source_pad) { in adv76xx_core_init()
2828 state->selected_input = pdata->default_input; in adv76xx_core_init()
2839 if (info->type != ADV7604) { in adv76xx_core_init()
2851 io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3); in adv76xx_core_init()
2852 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | in adv76xx_core_init()
2853 pdata->insert_av_codes << 2 | in adv76xx_core_init()
2854 pdata->replicate_av_codes << 1); in adv76xx_core_init()
2860 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | in adv76xx_core_init()
2861 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); in adv76xx_core_init()
2864 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | in adv76xx_core_init()
2865 pdata->dr_str_clk << 2 | in adv76xx_core_init()
2866 pdata->dr_str_sync); in adv76xx_core_init()
2868 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ in adv76xx_core_init()
2870 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - in adv76xx_core_init()
2872 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - in adv76xx_core_init()
2878 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ in adv76xx_core_init()
2880 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ in adv76xx_core_init()
2886 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ in adv76xx_core_init()
2887 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); in adv76xx_core_init()
2891 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ in adv76xx_core_init()
2893 …io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts … in adv76xx_core_init()
2894 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ in adv76xx_core_init()
2895 info->setup_irqs(sd); in adv76xx_core_init()
2897 return v4l2_ctrl_handler_setup(sd->ctrl_handler); in adv76xx_core_init()
2919 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) in adv76xx_unregister_clients()
2920 i2c_unregister_device(state->i2c_clients[i]); in adv76xx_unregister_clients()
2928 struct adv76xx_platform_data *pdata = &state->pdata; in adv76xx_dummy_client()
2932 if (pdata && pdata->i2c_addresses[page]) in adv76xx_dummy_client()
2933 new_client = i2c_new_dummy_device(client->adapter, in adv76xx_dummy_client()
2934 pdata->i2c_addresses[page]); in adv76xx_dummy_client()
2941 io_write(sd, io_reg, new_client->addr << 1); in adv76xx_dummy_client()
2951 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2964 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2966 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2968 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2977 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2990 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
3205 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; in adv76xx_parse_dt()
3208 endpoint = of_graph_get_endpoint_by_regs(np, -1, -1); in adv76xx_parse_dt()
3210 return -EINVAL; in adv76xx_parse_dt()
3217 if (!of_property_read_u32(np, "default-input", &v)) in adv76xx_parse_dt()
3218 state->pdata.default_input = v; in adv76xx_parse_dt()
3220 state->pdata.default_input = -1; in adv76xx_parse_dt()
3225 state->pdata.inv_hs_pol = 1; in adv76xx_parse_dt()
3228 state->pdata.inv_vs_pol = 1; in adv76xx_parse_dt()
3231 state->pdata.inv_llc_pol = 1; in adv76xx_parse_dt()
3234 state->pdata.insert_av_codes = 1; in adv76xx_parse_dt()
3236 /* Disable the interrupt for now as no DT-based board uses it. */ in adv76xx_parse_dt()
3237 state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH; in adv76xx_parse_dt()
3240 state->pdata.disable_pwrdnb = 0; in adv76xx_parse_dt()
3241 state->pdata.disable_cable_det_rst = 0; in adv76xx_parse_dt()
3242 state->pdata.blank_data = 1; in adv76xx_parse_dt()
3243 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; in adv76xx_parse_dt()
3244 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; in adv76xx_parse_dt()
3245 state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH; in adv76xx_parse_dt()
3246 state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH; in adv76xx_parse_dt()
3247 state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH; in adv76xx_parse_dt()
3364 if (!state->i2c_clients[region]) in configure_regmap()
3365 return -ENODEV; in configure_regmap()
3367 state->regmap[region] = in configure_regmap()
3368 devm_regmap_init_i2c(state->i2c_clients[region], in configure_regmap()
3371 if (IS_ERR(state->regmap[region])) { in configure_regmap()
3372 err = PTR_ERR(state->regmap[region]); in configure_regmap()
3373 v4l_err(state->i2c_clients[region], in configure_regmap()
3376 return -EINVAL; in configure_regmap()
3388 if (err && (err != -ENODEV)) in configure_regmaps()
3396 if (state->reset_gpio) { in adv76xx_reset()
3398 gpiod_set_value_cansleep(state->reset_gpio, 0); in adv76xx_reset()
3400 gpiod_set_value_cansleep(state->reset_gpio, 1); in adv76xx_reset()
3421 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) in adv76xx_probe()
3422 return -EIO; in adv76xx_probe()
3424 client->addr << 1); in adv76xx_probe()
3426 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); in adv76xx_probe()
3428 return -ENOMEM; in adv76xx_probe()
3430 state->i2c_clients[ADV76XX_PAGE_IO] = client; in adv76xx_probe()
3433 state->restart_stdi_once = true; in adv76xx_probe()
3434 state->selected_input = ~0; in adv76xx_probe()
3436 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { in adv76xx_probe()
3439 oid = of_match_node(adv76xx_of_id, client->dev.of_node); in adv76xx_probe()
3440 state->info = oid->data; in adv76xx_probe()
3447 } else if (client->dev.platform_data) { in adv76xx_probe()
3448 struct adv76xx_platform_data *pdata = client->dev.platform_data; in adv76xx_probe()
3450 state->info = (const struct adv76xx_chip_info *)id->driver_data; in adv76xx_probe()
3451 state->pdata = *pdata; in adv76xx_probe()
3454 return -ENODEV; in adv76xx_probe()
3458 for (i = 0; i < state->info->num_dv_ports; ++i) { in adv76xx_probe()
3459 state->hpd_gpio[i] = in adv76xx_probe()
3460 devm_gpiod_get_index_optional(&client->dev, "hpd", i, in adv76xx_probe()
3462 if (IS_ERR(state->hpd_gpio[i])) in adv76xx_probe()
3463 return PTR_ERR(state->hpd_gpio[i]); in adv76xx_probe()
3465 if (state->hpd_gpio[i]) in adv76xx_probe()
3468 state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", in adv76xx_probe()
3470 if (IS_ERR(state->reset_gpio)) in adv76xx_probe()
3471 return PTR_ERR(state->reset_gpio); in adv76xx_probe()
3475 state->timings = cea640x480; in adv76xx_probe()
3476 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); in adv76xx_probe()
3478 sd = &state->sd; in adv76xx_probe()
3480 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", in adv76xx_probe()
3481 id->name, i2c_adapter_id(client->adapter), in adv76xx_probe()
3482 client->addr); in adv76xx_probe()
3483 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; in adv76xx_probe()
3484 sd->internal_ops = &adv76xx_int_ops; in adv76xx_probe()
3491 return -ENODEV; in adv76xx_probe()
3499 switch (state->info->type) { in adv76xx_probe()
3501 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val); in adv76xx_probe()
3504 return -ENODEV; in adv76xx_probe()
3508 client->addr << 1); in adv76xx_probe()
3509 return -ENODEV; in adv76xx_probe()
3514 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], in adv76xx_probe()
3519 return -ENODEV; in adv76xx_probe()
3522 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], in adv76xx_probe()
3527 return -ENODEV; in adv76xx_probe()
3530 if ((state->info->type == ADV7611 && val != 0x2051) || in adv76xx_probe()
3531 (state->info->type == ADV7612 && val != 0x2041)) { in adv76xx_probe()
3533 state->info->type == ADV7611 ? "ADV7610/11" : "ADV7612", in adv76xx_probe()
3534 client->addr << 1); in adv76xx_probe()
3535 return -ENODEV; in adv76xx_probe()
3541 hdl = &state->hdl; in adv76xx_probe()
3545 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); in adv76xx_probe()
3556 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; in adv76xx_probe()
3558 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, in adv76xx_probe()
3560 (1 << state->info->num_dv_ports) - 1, 0, 0); in adv76xx_probe()
3561 state->rgb_quantization_range_ctrl = in adv76xx_probe()
3568 state->analog_sampling_phase_ctrl = in adv76xx_probe()
3570 state->free_run_color_manual_ctrl = in adv76xx_probe()
3572 state->free_run_color_ctrl = in adv76xx_probe()
3575 sd->ctrl_handler = hdl; in adv76xx_probe()
3576 if (hdl->error) { in adv76xx_probe()
3577 err = hdl->error; in adv76xx_probe()
3581 err = -ENODEV; in adv76xx_probe()
3588 if (!(BIT(i) & state->info->page_mask)) in adv76xx_probe()
3598 state->i2c_clients[i] = dummy_client; in adv76xx_probe()
3601 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, in adv76xx_probe()
3604 state->source_pad = state->info->num_dv_ports in adv76xx_probe()
3605 + (state->info->has_afe ? 2 : 0); in adv76xx_probe()
3606 for (i = 0; i < state->source_pad; ++i) in adv76xx_probe()
3607 state->pads[i].flags = MEDIA_PAD_FL_SINK; in adv76xx_probe()
3608 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; in adv76xx_probe()
3609 sd->entity.function = MEDIA_ENT_F_DV_DECODER; in adv76xx_probe()
3611 err = media_entity_pads_init(&sd->entity, state->source_pad + 1, in adv76xx_probe()
3612 state->pads); in adv76xx_probe()
3625 if (client->irq) { in adv76xx_probe()
3626 err = devm_request_threaded_irq(&client->dev, in adv76xx_probe()
3627 client->irq, in adv76xx_probe()
3630 client->name, state); in adv76xx_probe()
3636 state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops, in adv76xx_probe()
3637 state, dev_name(&client->dev), in adv76xx_probe()
3639 err = PTR_ERR_OR_ZERO(state->cec_adap); in adv76xx_probe()
3644 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, in adv76xx_probe()
3645 client->addr << 1, client->adapter->name); in adv76xx_probe()
3654 media_entity_cleanup(&sd->entity); in adv76xx_probe()
3656 cancel_delayed_work(&state->delayed_work_enable_hotplug); in adv76xx_probe()
3664 /* ----------------------------------------------------------------------- */
3678 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); in adv76xx_remove()
3680 media_entity_cleanup(&sd->entity); in adv76xx_remove()
3682 v4l2_ctrl_handler_free(sd->ctrl_handler); in adv76xx_remove()
3685 /* ----------------------------------------------------------------------- */