Lines Matching +full:0 +full:xc500

37 	{ 2572,	0 },
73 { 1548, 0 },
109 { 4870, 0x3000 },
110 { 4850, 0x3C00 },
111 { 4800, 0x4500 },
112 { 4750, 0x4800 },
113 { 4700, 0x4B00 },
114 { 4650, 0x4D00 },
115 { 4600, 0x4F00 },
116 { 4550, 0x5100 },
117 { 4500, 0x5200 },
118 { 4420, 0x5500 },
119 { 4316, 0x5800 },
120 { 4200, 0x5B00 },
121 { 4119, 0x5D00 },
122 { 3999, 0x6000 },
123 { 3950, 0x6100 },
124 { 3876, 0x6300 },
125 { 3755, 0x6600 },
126 { 3641, 0x6900 },
127 { 3567, 0x6B00 },
128 { 3425, 0x6F00 },
129 { 3350, 0x7100 },
130 { 3236, 0x7400 },
131 { 3118, 0x7700 },
132 { 3004, 0x7A00 },
133 { 2917, 0x7C00 },
134 { 2776, 0x7F00 },
135 { 2635, 0x8200 },
136 { 2516, 0x8500 },
137 { 2406, 0x8800 },
138 { 2290, 0x8B00 },
139 { 2170, 0x8E00 },
140 { 2073, 0x9100 },
141 { 1949, 0x9400 },
142 { 1836, 0x9700 },
143 { 1712, 0x9A00 },
144 { 1631, 0x9C00 },
145 { 1515, 0x9F00 },
146 { 1400, 0xA200 },
147 { 1323, 0xA400 },
148 { 1203, 0xA700 },
149 { 1091, 0xAA00 },
150 { 1011, 0xAC00 },
151 { 904, 0xAF00 },
152 { 787, 0xB200 },
153 { 685, 0xB500 },
154 { 571, 0xB800 },
155 { 464, 0xBB00 },
156 { 374, 0xBE00 },
157 { 275, 0xC200 },
158 { 181, 0xC600 },
159 { 102, 0xCC00 },
160 { 49, 0xD900 }
169 { 7082, 0x3000 },
170 { 7052, 0x4000 },
171 { 7007, 0x4600 },
172 { 6954, 0x4A00 },
173 { 6909, 0x4D00 },
174 { 6833, 0x5100 },
175 { 6753, 0x5400 },
176 { 6659, 0x5700 },
177 { 6561, 0x5A00 },
178 { 6472, 0x5C00 },
179 { 6366, 0x5F00 },
180 { 6259, 0x6100 },
181 { 6151, 0x6400 },
182 { 6026, 0x6700 },
183 { 5920, 0x6900 },
184 { 5835, 0x6B00 },
185 { 5770, 0x6C00 },
186 { 5681, 0x6E00 },
187 { 5596, 0x7000 },
188 { 5503, 0x7200 },
189 { 5429, 0x7300 },
190 { 5319, 0x7500 },
191 { 5220, 0x7700 },
192 { 5111, 0x7900 },
193 { 4983, 0x7B00 },
194 { 4876, 0x7D00 },
195 { 4755, 0x7F00 },
196 { 4635, 0x8100 },
197 { 4499, 0x8300 },
198 { 4405, 0x8500 },
199 { 4323, 0x8600 },
200 { 4233, 0x8800 },
201 { 4156, 0x8A00 },
202 { 4038, 0x8C00 },
203 { 3935, 0x8E00 },
204 { 3823, 0x9000 },
205 { 3712, 0x9200 },
206 { 3601, 0x9500 },
207 { 3511, 0x9700 },
208 { 3413, 0x9900 },
209 { 3309, 0x9B00 },
210 { 3213, 0x9D00 },
211 { 3088, 0x9F00 },
212 { 2992, 0xA100 },
213 { 2878, 0xA400 },
214 { 2769, 0xA700 },
215 { 2645, 0xAA00 },
216 { 2538, 0xAD00 },
217 { 2441, 0xB000 },
218 { 2350, 0xB600 },
219 { 2237, 0xBA00 },
220 { 2137, 0xBF00 },
221 { 2039, 0xC500 },
222 { 1938, 0xDF00 },
223 { 1927, 0xFF00 }
228 { 7070, 0x3000 },
229 { 7028, 0x4000 },
230 { 7019, 0x4600 },
231 { 6900, 0x4A00 },
232 { 6811, 0x4D00 },
233 { 6763, 0x5100 },
234 { 6690, 0x5400 },
235 { 6644, 0x5700 },
236 { 6617, 0x5A00 },
237 { 6598, 0x5C00 },
238 { 6462, 0x5F00 },
239 { 6348, 0x6100 },
240 { 6197, 0x6400 },
241 { 6154, 0x6700 },
242 { 6098, 0x6900 },
243 { 5893, 0x6B00 },
244 { 5812, 0x6C00 },
245 { 5773, 0x6E00 },
246 { 5723, 0x7000 },
247 { 5661, 0x7200 },
248 { 5579, 0x7300 },
249 { 5460, 0x7500 },
250 { 5308, 0x7700 },
251 { 5099, 0x7900 },
252 { 4910, 0x7B00 },
253 { 4800, 0x7D00 },
254 { 4785, 0x7F00 },
255 { 4635, 0x8100 },
256 { 4466, 0x8300 },
257 { 4314, 0x8500 },
258 { 4295, 0x8600 },
259 { 4144, 0x8800 },
260 { 3920, 0x8A00 },
261 { 3889, 0x8C00 },
262 { 3771, 0x8E00 },
263 { 3655, 0x9000 },
264 { 3446, 0x9200 },
265 { 3298, 0x9500 },
266 { 3083, 0x9700 },
267 { 3015, 0x9900 },
268 { 2833, 0x9B00 },
269 { 2746, 0x9D00 },
270 { 2632, 0x9F00 },
271 { 2598, 0xA100 },
272 { 2480, 0xA400 },
273 { 2236, 0xA700 },
274 { 2171, 0xAA00 },
275 { 2060, 0xAD00 },
276 { 1999, 0xB000 },
277 { 1974, 0xB600 },
278 { 1820, 0xBA00 },
279 { 1741, 0xBF00 },
280 { 1655, 0xC500 },
281 { 1444, 0xDF00 },
282 { 1325, 0xFF00 },
298 struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, in i2c_read()
306 return 0; in i2c_read()
311 struct i2c_msg msg = {.addr = adr, .flags = 0, in i2c_write()
318 return 0; in i2c_write()
326 d[0] = reg; in write_regs()
344 int status = 0; in wait_for_call_done()
347 while (lock_retry_count > 0) { in wait_for_call_done()
351 if (status < 0) in wait_for_call_done()
354 if ((regval & mask) == 0) in wait_for_call_done()
366 u32 clkdiv = 0; in init_state()
367 u32 agcmode = 0; in init_state()
369 u32 agcset = 0xffffffff; in init_state()
370 u32 bbmode = 0xffffffff; in init_state()
372 state->reg[0] = 0x08; in init_state()
373 state->reg[1] = 0x41; in init_state()
374 state->reg[2] = 0x8f; in init_state()
375 state->reg[3] = 0x00; in init_state()
376 state->reg[4] = 0xce; in init_state()
377 state->reg[5] = 0x54; in init_state()
378 state->reg[6] = 0x55; in init_state()
379 state->reg[7] = 0x45; in init_state()
380 state->reg[8] = 0x46; in init_state()
381 state->reg[9] = 0xbd; in init_state()
382 state->reg[10] = 0x11; in init_state()
387 state->reg[0x00] |= (clkdiv & 0x03); in init_state()
389 state->reg[0x03] |= (agcmode << 5); in init_state()
390 if (agcmode == 0x01) in init_state()
391 state->reg[0x01] |= 0x30; in init_state()
394 state->reg[0x01] = (state->reg[0x01] & ~0x30) | (bbmode << 4); in init_state()
396 state->reg[0x03] |= agcref; in init_state()
398 state->reg[0x02] = (state->reg[0x02] & ~0x1F) | agcset | 0x40; in init_state()
403 if (write_regs(state, 0, 11)) in attach_init()
405 return 0; in attach_init()
418 int stat = 0; in set_bandwidth()
424 if ((state->reg[0x08] & ~0xFC) == ((index - 6) << 2)) in set_bandwidth()
425 return 0; in set_bandwidth()
427 state->reg[0x08] = (state->reg[0x08] & ~0xFC) | ((index - 6) << 2); in set_bandwidth()
428 state->reg[0x09] = (state->reg[0x09] & ~0x0C) | 0x08; in set_bandwidth()
432 write_regs(state, 0x08, 2); in set_bandwidth()
433 wait_for_call_done(state, 0x08); in set_bandwidth()
436 fe->ops.i2c_gate_ctrl(fe, 0); in set_bandwidth()
444 u32 p = 1, psel = 0, fvco, div, frac; in set_lof()
457 psel = 0; in set_lof()
462 frac = muldiv32(frac, 0x40000, state->ref_freq); in set_lof()
464 icp = 0; in set_lof()
466 icp = 0; in set_lof()
480 state->reg[0x02] |= 0x80; /* LNA IIP3 Mode */ in set_lof()
482 state->reg[0x03] = (state->reg[0x03] & ~0x80) | (psel << 7); in set_lof()
483 state->reg[0x04] = (div & 0xFF); in set_lof()
484 state->reg[0x05] = (((div >> 8) & 0x01) | ((frac & 0x7F) << 1)) & 0xff; in set_lof()
485 state->reg[0x06] = ((frac >> 7) & 0xFF); in set_lof()
486 state->reg[0x07] = (state->reg[0x07] & ~0x07) | ((frac >> 15) & 0x07); in set_lof()
487 state->reg[0x07] = (state->reg[0x07] & ~0xE0) | (icp << 5); in set_lof()
489 state->reg[0x08] = (state->reg[0x08] & ~0xFC) | ((index - 6) << 2); in set_lof()
491 state->reg[0x09] = (state->reg[0x09] & ~0x0C) | 0x0C; in set_lof()
494 wait_for_call_done(state, 0x0C); in set_lof()
498 read_reg(state, 0x03, &tmp); in set_lof()
499 if (tmp & 0x10) { in set_lof()
500 state->reg[0x02] &= ~0x80; /* LNA NF Mode */ in set_lof()
503 read_reg(state, 0x08, &tmp); in set_lof()
507 return 0; in set_lof()
515 int stat = 0; in set_params()
528 fe->ops.i2c_gate_ctrl(fe, 0); in set_params()
529 return 0; in set_params()
537 int imin = 0; in table_lookup()
541 /* Assumes Table[0].RegValue < Table[imax].RegValue */ in table_lookup()
542 if (reg_value <= table[0].reg_value) { in table_lookup()
543 gain = table[0].value; in table_lookup()
557 if (reg_diff != 0) in table_lookup()
571 if ((state->reg[0x03] & 0x60) == 0) { in get_rf_strength()
573 u8 reg = 0; in get_rf_strength()
574 int stat = 0; in get_rf_strength()
579 write_reg(state, 0x02, state->reg[0x02] | 0x20); in get_rf_strength()
581 if (reg & 0x20) in get_rf_strength()
585 fe->ops.i2c_gate_ctrl(fe, 0); in get_rf_strength()
587 if ((state->reg[0x02] & 0x80) == 0) in get_rf_strength()
591 reg & 0x1F); in get_rf_strength()
596 reg & 0x1F); in get_rf_strength()
604 if ((state->reg[0x02] & 0x80) == 0) { in get_rf_strength()
620 if (state->frequency > 0) in get_rf_strength()
625 gain += (s32)((state->reg[0x01] & 0xC0) >> 6) * 600 - 1300; in get_rf_strength()
627 if (gain < 0) in get_rf_strength()
628 gain = 0; in get_rf_strength()
634 return 0; in get_rf_strength()
654 int gatestat = 0; in stv6111_attach()
669 fe->ops.i2c_gate_ctrl(fe, 0); in stv6111_attach()
670 if (stat < 0) { in stv6111_attach()