Lines Matching refs:regoff
85 u16 regoff; member
472 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3); in get_cur_symbol_rate()
473 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2); in get_cur_symbol_rate()
474 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1); in get_cur_symbol_rate()
475 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0); in get_cur_symbol_rate()
476 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2); in get_cur_symbol_rate()
477 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1); in get_cur_symbol_rate()
478 read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0); in get_cur_symbol_rate()
504 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); in get_signal_parameters()
510 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); in get_signal_parameters()
540 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp); in tracking_optimization()
554 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp); in tracking_optimization()
568 state->regoff, aclc); in tracking_optimization()
571 state->regoff, 0x2a); in tracking_optimization()
573 state->regoff, aclc); in tracking_optimization()
576 state->regoff, 0x2a); in tracking_optimization()
578 state->regoff, aclc); in tracking_optimization()
581 state->regoff, 0x2a); in tracking_optimization()
583 state->regoff, aclc); in tracking_optimization()
640 read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff, in get_signal_to_noise()
642 read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff, in get_signal_to_noise()
647 read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff, in get_signal_to_noise()
649 read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff, in get_signal_to_noise()
665 RSTV0910_P2_ERRCNT12 + state->regoff, in get_bit_error_rate_s()
679 state->regoff, in get_bit_error_rate_s()
685 state->regoff, 0x20 | in get_bit_error_rate_s()
739 int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff, in get_bit_error_rate_s2()
754 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, in get_bit_error_rate_s2()
759 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, in get_bit_error_rate_s2()
855 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in stop()
857 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp); in stop()
859 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp); in stop()
861 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B); in stop()
863 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c); in stop()
876 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff, in set_pls()
878 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff, in set_pls()
880 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff, in set_pls()
894 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff, in set_isi()
896 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff); in set_isi()
953 return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val); in enable_puncture_rate()
964 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth_default()
965 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth_default()
966 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth_default()
967 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth_default()
968 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth_default()
969 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth_default()
986 RSTV0910_P2_NNOSDATAT1 + state->regoff, in set_vth()
996 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth()
997 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth()
998 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth()
999 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth()
1000 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth()
1001 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth()
1019 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C); in start()
1045 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff, in start()
1047 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF)); in start()
1050 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits); in start()
1053 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd); in start()
1054 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, in start()
1061 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00); in start()
1062 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F); in start()
1067 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B); in start()
1068 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A); in start()
1069 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84); in start()
1070 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84); in start()
1071 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C); in start()
1072 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79); in start()
1074 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29); in start()
1075 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09); in start()
1076 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84); in start()
1077 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84); in start()
1088 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1090 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46); in start()
1098 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff, in start()
1100 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff)); in start()
1103 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff, in start()
1105 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff)); in start()
1108 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0); in start()
1109 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0); in start()
1111 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1113 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15); in start()
1292 read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff, in manage_matype_info()
1347 read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2); in read_signal_strength()
1352 read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2); in read_signal_strength()
1376 read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state); in read_status()
1379 read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus); in read_status()
1409 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1412 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1414 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1422 RSTV0910_P2_PDELSTATUS1 + state->regoff, in read_status()
1429 RSTV0910_P2_VSTATUSVIT + state->regoff, in read_status()
1452 RSTV0910_P2_DEMOD + state->regoff, in read_status()
1455 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1460 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1465 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1473 RSTV0910_P2_ERRCTRL1 + state->regoff, in read_status()
1481 RSTV0910_P2_ERRCTRL1 + state->regoff, in read_status()
1486 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00); in read_status()
1492 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1); in read_status()
1505 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, in read_status()
1565 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); in get_frontend()
1571 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); in get_frontend()
1779 state->regoff = state->nr ? 0 : 0x200; in stv0910_attach()